1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #ifndef _MT7620_REGS_H_ 14 #define _MT7620_REGS_H_ 15 16 #define MT7620_SYSC_BASE 0x10000000 17 18 #define SYSC_REG_CHIP_NAME0 0x00 19 #define SYSC_REG_CHIP_NAME1 0x04 20 #define SYSC_REG_CHIP_REV 0x0c 21 #define SYSC_REG_SYSTEM_CONFIG0 0x10 22 #define SYSC_REG_SYSTEM_CONFIG1 0x14 23 #define SYSC_REG_CLKCFG0 0x2c 24 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c 25 #define SYSC_REG_CPLL_CONFIG0 0x54 26 #define SYSC_REG_CPLL_CONFIG1 0x58 27 28 #define MT7620N_CHIP_NAME0 0x33365452 29 #define MT7620N_CHIP_NAME1 0x20203235 30 31 #define MT7620A_CHIP_NAME0 0x3637544d 32 #define MT7620A_CHIP_NAME1 0x20203032 33 34 #define SYSCFG0_XTAL_FREQ_SEL BIT(6) 35 36 #define CHIP_REV_PKG_MASK 0x1 37 #define CHIP_REV_PKG_SHIFT 16 38 #define CHIP_REV_VER_MASK 0xf 39 #define CHIP_REV_VER_SHIFT 8 40 #define CHIP_REV_ECO_MASK 0xf 41 42 #define CLKCFG0_PERI_CLK_SEL BIT(4) 43 44 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 45 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf 46 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ 47 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ 48 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ 49 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ 50 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ 51 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ 52 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ 53 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ 54 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ 55 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 56 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f 57 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 58 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f 59 60 #define CPLL_CFG0_SW_CFG BIT(31) 61 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 62 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 63 #define CPLL_CFG0_LC_CURFCK BIT(15) 64 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14) 65 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 66 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 67 68 #define CPLL_CFG1_CPU_AUX1 BIT(25) 69 #define CPLL_CFG1_CPU_AUX0 BIT(24) 70 71 #define SYSCFG0_DRAM_TYPE_MASK 0x3 72 #define SYSCFG0_DRAM_TYPE_SHIFT 4 73 #define SYSCFG0_DRAM_TYPE_SDRAM 0 74 #define SYSCFG0_DRAM_TYPE_DDR1 1 75 #define SYSCFG0_DRAM_TYPE_DDR2 2 76 77 #define MT7620_DRAM_BASE 0x0 78 #define MT7620_SDRAM_SIZE_MIN 2 79 #define MT7620_SDRAM_SIZE_MAX 64 80 #define MT7620_DDR1_SIZE_MIN 32 81 #define MT7620_DDR1_SIZE_MAX 128 82 #define MT7620_DDR2_SIZE_MIN 32 83 #define MT7620_DDR2_SIZE_MAX 256 84 85 #define MT7620_GPIO_MODE_I2C BIT(0) 86 #define MT7620_GPIO_MODE_UART0_SHIFT 2 87 #define MT7620_GPIO_MODE_UART0_MASK 0x7 88 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) 89 #define MT7620_GPIO_MODE_UARTF 0x0 90 #define MT7620_GPIO_MODE_PCM_UARTF 0x1 91 #define MT7620_GPIO_MODE_PCM_I2S 0x2 92 #define MT7620_GPIO_MODE_I2S_UARTF 0x3 93 #define MT7620_GPIO_MODE_PCM_GPIO 0x4 94 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5 95 #define MT7620_GPIO_MODE_GPIO_I2S 0x6 96 #define MT7620_GPIO_MODE_GPIO 0x7 97 #define MT7620_GPIO_MODE_UART1 BIT(5) 98 #define MT7620_GPIO_MODE_MDIO BIT(8) 99 #define MT7620_GPIO_MODE_RGMII1 BIT(9) 100 #define MT7620_GPIO_MODE_RGMII2 BIT(10) 101 #define MT7620_GPIO_MODE_SPI BIT(11) 102 #define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12) 103 #define MT7620_GPIO_MODE_WLED BIT(13) 104 #define MT7620_GPIO_MODE_JTAG BIT(15) 105 #define MT7620_GPIO_MODE_EPHY BIT(15) 106 #define MT7620_GPIO_MODE_WDT BIT(22) 107 108 #endif 109