1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Chris Dearman (chris@mips.com) 7 * Copyright (C) 2007 Mips Technologies, Inc. 8 * Copyright (C) 2014 Imagination Technologies Ltd. 9 */ 10 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H 11 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H 12 13 /* 14 * Prepare segments for EVA boot: 15 * 16 * This is in case the processor boots in legacy configuration 17 * (SI_EVAReset is de-asserted and CONFIG5.K == 0) 18 * 19 * On entry, t1 is loaded with CP0_CONFIG 20 * 21 * ========================= Mappings ============================= 22 * Virtual memory Physical memory Mapping 23 * 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 24 * Flat 2GB physical memory 25 * 26 * 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 27 * 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 28 * 0xc0000000 - 0xdfffffff - MK (kseg2) 29 * 0xe0000000 - 0xffffffff - MK (kseg3) 30 * 31 * 32 * Lowmem is expanded to 2GB 33 */ 34 .macro eva_entry 35 /* 36 * Get Config.K0 value and use it to program 37 * the segmentation registers 38 */ 39 andi t1, 0x7 /* CCA */ 40 move t2, t1 41 ins t2, t1, 16, 3 42 /* SegCtl0 */ 43 li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ 44 (0 << MIPS_SEGCFG_PA_SHIFT) | \ 45 (1 << MIPS_SEGCFG_EU_SHIFT)) | \ 46 (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ 47 (0 << MIPS_SEGCFG_PA_SHIFT) | \ 48 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 49 or t0, t2 50 mtc0 t0, $5, 2 51 52 /* SegCtl1 */ 53 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 54 (0 << MIPS_SEGCFG_PA_SHIFT) | \ 55 (2 << MIPS_SEGCFG_C_SHIFT) | \ 56 (1 << MIPS_SEGCFG_EU_SHIFT)) | \ 57 (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 58 (0 << MIPS_SEGCFG_PA_SHIFT) | \ 59 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 60 ins t0, t1, 16, 3 61 mtc0 t0, $5, 3 62 63 /* SegCtl2 */ 64 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 65 (6 << MIPS_SEGCFG_PA_SHIFT) | \ 66 (1 << MIPS_SEGCFG_EU_SHIFT)) | \ 67 (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 68 (4 << MIPS_SEGCFG_PA_SHIFT) | \ 69 (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 70 or t0, t2 71 mtc0 t0, $5, 4 72 73 jal mips_ihb 74 mfc0 t0, $16, 5 75 li t2, 0x40000000 /* K bit */ 76 or t0, t0, t2 77 mtc0 t0, $16, 5 78 sync 79 jal mips_ihb 80 .endm 81 82 .macro kernel_entry_setup 83 #ifdef CONFIG_MIPS_MT_SMTC 84 mfc0 t0, CP0_CONFIG 85 bgez t0, 9f 86 mfc0 t0, CP0_CONFIG, 1 87 bgez t0, 9f 88 mfc0 t0, CP0_CONFIG, 2 89 bgez t0, 9f 90 mfc0 t0, CP0_CONFIG, 3 91 and t0, 1<<2 92 bnez t0, 0f 93 9: 94 /* Assume we came from YAMON... */ 95 PTR_LA v0, 0x9fc00534 /* YAMON print */ 96 lw v0, (v0) 97 move a0, zero 98 PTR_LA a1, nonmt_processor 99 jal v0 100 101 PTR_LA v0, 0x9fc00520 /* YAMON exit */ 102 lw v0, (v0) 103 li a0, 1 104 jal v0 105 106 1: b 1b 107 108 __INITDATA 109 nonmt_processor: 110 .asciz "SMTC kernel requires the MT ASE to run\n" 111 __FINIT 112 #endif 113 114 #ifdef CONFIG_EVA 115 sync 116 ehb 117 118 mfc0 t1, CP0_CONFIG 119 bgez t1, 9f 120 mfc0 t0, CP0_CONFIG, 1 121 bgez t0, 9f 122 mfc0 t0, CP0_CONFIG, 2 123 bgez t0, 9f 124 mfc0 t0, CP0_CONFIG, 3 125 sll t0, t0, 6 /* SC bit */ 126 bgez t0, 9f 127 128 eva_entry 129 b 0f 130 9: 131 /* Assume we came from YAMON... */ 132 PTR_LA v0, 0x9fc00534 /* YAMON print */ 133 lw v0, (v0) 134 move a0, zero 135 PTR_LA a1, nonsc_processor 136 jal v0 137 138 PTR_LA v0, 0x9fc00520 /* YAMON exit */ 139 lw v0, (v0) 140 li a0, 1 141 jal v0 142 143 1: b 1b 144 nop 145 __INITDATA 146 nonsc_processor: 147 .asciz "EVA kernel requires a MIPS core with Segment Control implemented\n" 148 __FINIT 149 #endif /* CONFIG_EVA */ 150 0: 151 .endm 152 153 /* 154 * Do SMP slave processor setup necessary before we can safely execute C code. 155 */ 156 .macro smp_slave_setup 157 #ifdef CONFIG_EVA 158 sync 159 ehb 160 mfc0 t1, CP0_CONFIG 161 eva_entry 162 #endif 163 .endm 164 165 #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ 166