1 /*
2  * Read/Write Loongson Extension Registers
3  */
4 
5 #ifndef _LOONGSON_REGS_H_
6 #define _LOONGSON_REGS_H_
7 
8 #include <linux/types.h>
9 #include <linux/bits.h>
10 
11 #include <asm/mipsregs.h>
12 #include <asm/cpu.h>
13 
14 static inline bool cpu_has_cfg(void)
15 {
16 	return ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G);
17 }
18 
19 static inline u32 read_cpucfg(u32 reg)
20 {
21 	u32 __res;
22 
23 	__asm__ __volatile__(
24 		"parse_r __res,%0\n\t"
25 		"parse_r reg,%1\n\t"
26 		".insn \n\t"
27 		".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
28 		:"=r"(__res)
29 		:"r"(reg)
30 		:
31 		);
32 	return __res;
33 }
34 
35 /* Bit Domains for CFG registers */
36 #define LOONGSON_CFG0	0x0
37 #define LOONGSON_CFG0_PRID GENMASK(31, 0)
38 
39 #define LOONGSON_CFG1 0x1
40 #define LOONGSON_CFG1_FP	BIT(0)
41 #define LOONGSON_CFG1_FPREV	GENMASK(3, 1)
42 #define LOONGSON_CFG1_MMI	BIT(4)
43 #define LOONGSON_CFG1_MSA1	BIT(5)
44 #define LOONGSON_CFG1_MSA2	BIT(6)
45 #define LOONGSON_CFG1_CGP	BIT(7)
46 #define LOONGSON_CFG1_WRP	BIT(8)
47 #define LOONGSON_CFG1_LSX1	BIT(9)
48 #define LOONGSON_CFG1_LSX2	BIT(10)
49 #define LOONGSON_CFG1_LASX	BIT(11)
50 #define LOONGSON_CFG1_R6FXP	BIT(12)
51 #define LOONGSON_CFG1_R6CRCP	BIT(13)
52 #define LOONGSON_CFG1_R6FPP	BIT(14)
53 #define LOONGSON_CFG1_CNT64	BIT(15)
54 #define LOONGSON_CFG1_LSLDR0	BIT(16)
55 #define LOONGSON_CFG1_LSPREF	BIT(17)
56 #define LOONGSON_CFG1_LSPREFX	BIT(18)
57 #define LOONGSON_CFG1_LSSYNCI	BIT(19)
58 #define LOONGSON_CFG1_LSUCA	BIT(20)
59 #define LOONGSON_CFG1_LLSYNC	BIT(21)
60 #define LOONGSON_CFG1_TGTSYNC	BIT(22)
61 #define LOONGSON_CFG1_LLEXC	BIT(23)
62 #define LOONGSON_CFG1_SCRAND	BIT(24)
63 #define LOONGSON_CFG1_MUALP	BIT(25)
64 #define LOONGSON_CFG1_KMUALEN	BIT(26)
65 #define LOONGSON_CFG1_ITLBT	BIT(27)
66 #define LOONGSON_CFG1_LSUPERF	BIT(28)
67 #define LOONGSON_CFG1_SFBP	BIT(29)
68 #define LOONGSON_CFG1_CDMAP	BIT(30)
69 
70 #define LOONGSON_CFG2 0x2
71 #define LOONGSON_CFG2_LEXT1	BIT(0)
72 #define LOONGSON_CFG2_LEXT2	BIT(1)
73 #define LOONGSON_CFG2_LEXT3	BIT(2)
74 #define LOONGSON_CFG2_LSPW	BIT(3)
75 #define LOONGSON_CFG2_LBT1	BIT(4)
76 #define LOONGSON_CFG2_LBT2	BIT(5)
77 #define LOONGSON_CFG2_LBT3	BIT(6)
78 #define LOONGSON_CFG2_LBTMMU	BIT(7)
79 #define LOONGSON_CFG2_LPMP	BIT(8)
80 #define LOONGSON_CFG2_LPMPREV	GENMASK(11, 9)
81 #define LOONGSON_CFG2_LAMO	BIT(12)
82 #define LOONGSON_CFG2_LPIXU	BIT(13)
83 #define LOONGSON_CFG2_LPIXUN	BIT(14)
84 #define LOONGSON_CFG2_LZVP	BIT(15)
85 #define LOONGSON_CFG2_LZVREV	GENMASK(18, 16)
86 #define LOONGSON_CFG2_LGFTP	BIT(19)
87 #define LOONGSON_CFG2_LGFTPREV	GENMASK(22, 20)
88 #define LOONGSON_CFG2_LLFTP	BIT(23)
89 #define LOONGSON_CFG2_LLFTPREV	GENMASK(26, 24)
90 #define LOONGSON_CFG2_LCSRP	BIT(27)
91 #define LOONGSON_CFG2_LDISBLIKELY	BIT(28)
92 
93 #define LOONGSON_CFG3 0x3
94 #define LOONGSON_CFG3_LCAMP	BIT(0)
95 #define LOONGSON_CFG3_LCAMREV	GENMASK(3, 1)
96 #define LOONGSON_CFG3_LCAMNUM	GENMASK(11, 4)
97 #define LOONGSON_CFG3_LCAMKW	GENMASK(19, 12)
98 #define LOONGSON_CFG3_LCAMVW	GENMASK(27, 20)
99 
100 #define LOONGSON_CFG4 0x4
101 #define LOONGSON_CFG4_CCFREQ	GENMASK(31, 0)
102 
103 #define LOONGSON_CFG5 0x5
104 #define LOONGSON_CFG5_CFM	GENMASK(15, 0)
105 #define LOONGSON_CFG5_CFD	GENMASK(31, 16)
106 
107 #define LOONGSON_CFG6 0x6
108 
109 #define LOONGSON_CFG7 0x7
110 #define LOONGSON_CFG7_GCCAEQRP	BIT(0)
111 #define LOONGSON_CFG7_UCAWINP	BIT(1)
112 
113 static inline bool cpu_has_csr(void)
114 {
115 	if (cpu_has_cfg())
116 		return (read_cpucfg(LOONGSON_CFG2) & LOONGSON_CFG2_LCSRP);
117 
118 	return false;
119 }
120 
121 static inline u32 csr_readl(u32 reg)
122 {
123 	u32 __res;
124 
125 	/* RDCSR reg, val */
126 	__asm__ __volatile__(
127 		"parse_r __res,%0\n\t"
128 		"parse_r reg,%1\n\t"
129 		".insn \n\t"
130 		".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t"
131 		:"=r"(__res)
132 		:"r"(reg)
133 		:
134 		);
135 	return __res;
136 }
137 
138 static inline u64 csr_readq(u32 reg)
139 {
140 	u64 __res;
141 
142 	/* DWRCSR reg, val */
143 	__asm__ __volatile__(
144 		"parse_r __res,%0\n\t"
145 		"parse_r reg,%1\n\t"
146 		".insn \n\t"
147 		".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t"
148 		:"=r"(__res)
149 		:"r"(reg)
150 		:
151 		);
152 	return __res;
153 }
154 
155 static inline void csr_writel(u32 val, u32 reg)
156 {
157 	/* WRCSR reg, val */
158 	__asm__ __volatile__(
159 		"parse_r reg,%0\n\t"
160 		"parse_r val,%1\n\t"
161 		".insn \n\t"
162 		".word (0xc8010118 | (reg << 21) | (val << 11))\n\t"
163 		:
164 		:"r"(reg),"r"(val)
165 		:
166 		);
167 }
168 
169 static inline void csr_writeq(u64 val, u32 reg)
170 {
171 	/* DWRCSR reg, val */
172 	__asm__ __volatile__(
173 		"parse_r reg,%0\n\t"
174 		"parse_r val,%1\n\t"
175 		".insn \n\t"
176 		".word (0xc8030118 | (reg << 21) | (val << 11))\n\t"
177 		:
178 		:"r"(reg),"r"(val)
179 		:
180 		);
181 }
182 
183 /* Public CSR Register can also be accessed with regular addresses */
184 #define CSR_PUBLIC_MMIO_BASE 0x1fe00000
185 
186 #define MMIO_CSR(x)		(void *)TO_UNCAC(CSR_PUBLIC_MMIO_BASE + x)
187 
188 #define LOONGSON_CSR_FEATURES	0x8
189 #define LOONGSON_CSRF_TEMP	BIT(0)
190 #define LOONGSON_CSRF_NODECNT	BIT(1)
191 #define LOONGSON_CSRF_MSI	BIT(2)
192 #define LOONGSON_CSRF_EXTIOI	BIT(3)
193 #define LOONGSON_CSRF_IPI	BIT(4)
194 #define LOONGSON_CSRF_FREQ	BIT(5)
195 
196 #define LOONGSON_CSR_VENDOR	0x10 /* Vendor name string, should be "Loongson" */
197 #define LOONGSON_CSR_CPUNAME	0x20 /* Processor name string */
198 #define LOONGSON_CSR_NODECNT	0x408
199 #define LOONGSON_CSR_CPUTEMP	0x428
200 
201 /* PerCore CSR, only accessable by local cores */
202 #define LOONGSON_CSR_IPI_STATUS	0x1000
203 #define LOONGSON_CSR_IPI_EN	0x1004
204 #define LOONGSON_CSR_IPI_SET	0x1008
205 #define LOONGSON_CSR_IPI_CLEAR	0x100c
206 #define LOONGSON_CSR_IPI_SEND	0x1040
207 #define CSR_IPI_SEND_IP_SHIFT	0
208 #define CSR_IPI_SEND_CPU_SHIFT	16
209 #define CSR_IPI_SEND_BLOCK	BIT(31)
210 
211 static inline u64 drdtime(void)
212 {
213 	int rID = 0;
214 	u64 val = 0;
215 
216 	__asm__ __volatile__(
217 		"parse_r rID,%0\n\t"
218 		"parse_r val,%1\n\t"
219 		".insn \n\t"
220 		".word (0xc8090118 | (rID << 21) | (val << 11))\n\t"
221 		:"=r"(rID),"=r"(val)
222 		:
223 		);
224 	return val;
225 }
226 
227 #endif
228