1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_MACH_LOONGSON64_IRQ_H_
3 #define __ASM_MACH_LOONGSON64_IRQ_H_
4 
5 #include <boot_param.h>
6 
7 /* cpu core interrupt numbers */
8 #define MIPS_CPU_IRQ_BASE 56
9 
10 #define LOONGSON_UART_IRQ   (MIPS_CPU_IRQ_BASE + 2) /* UART */
11 #define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
12 #define LOONGSON_TIMER_IRQ  (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
13 
14 #define LOONGSON_HT1_CFG_BASE		loongson_sysconf.ht_control_base
15 #define LOONGSON_HT1_INT_VECTOR_BASE	(LOONGSON_HT1_CFG_BASE + 0x80)
16 #define LOONGSON_HT1_INT_EN_BASE	(LOONGSON_HT1_CFG_BASE + 0xa0)
17 #define LOONGSON_HT1_INT_VECTOR(n)	\
18 		LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
19 #define LOONGSON_HT1_INTN_EN(n)		\
20 		LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
21 
22 #define LOONGSON_INT_ROUTER_OFFSET	0x1400
23 #define LOONGSON_INT_ROUTER_INTEN	\
24 	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
25 #define LOONGSON_INT_ROUTER_INTENSET	\
26 	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
27 #define LOONGSON_INT_ROUTER_INTENCLR	\
28 	  LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
29 #define LOONGSON_INT_ROUTER_ENTRY(n)	\
30 	  LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
31 #define LOONGSON_INT_ROUTER_LPC		LOONGSON_INT_ROUTER_ENTRY(0x0a)
32 #define LOONGSON_INT_ROUTER_HT1(n)	LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
33 
34 #define LOONGSON_INT_COREx_INTy(x, y)	(1<<(x) | 1<<(y+4))	/* route to int y of core x */
35 
36 extern void fixup_irqs(void);
37 extern void loongson3_ipi_interrupt(struct pt_regs *regs);
38 
39 #include_next <irq.h>
40 #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
41