1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 29bdcf336SManuel Lauss /* 39bdcf336SManuel Lauss * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. 49bdcf336SManuel Lauss * 59bdcf336SManuel Lauss * All Alchemy development boards (except, of course, the weird PB1000) 69bdcf336SManuel Lauss * have a few registers in a CPLD with standardised layout; they mostly 79bdcf336SManuel Lauss * only differ in base address and bit meanings in the RESETS and BOARD 89bdcf336SManuel Lauss * registers. 99bdcf336SManuel Lauss * 109bdcf336SManuel Lauss * All data taken from the official AMD board documentation sheets. 119bdcf336SManuel Lauss */ 129bdcf336SManuel Lauss 139bdcf336SManuel Lauss #ifndef _DB1XXX_BCSR_H_ 149bdcf336SManuel Lauss #define _DB1XXX_BCSR_H_ 159bdcf336SManuel Lauss 169bdcf336SManuel Lauss 179bdcf336SManuel Lauss /* BCSR base addresses on various boards. BCSR base 2 refers to the 189bdcf336SManuel Lauss * physical address of the first HEXLEDS register, which is usually 199bdcf336SManuel Lauss * a variable offset from the WHOAMI register. 209bdcf336SManuel Lauss */ 219bdcf336SManuel Lauss 229bdcf336SManuel Lauss /* DB1000, DB1100, DB1500, PB1100, PB1500 */ 239bdcf336SManuel Lauss #define DB1000_BCSR_PHYS_ADDR 0x0E000000 249bdcf336SManuel Lauss #define DB1000_BCSR_HEXLED_OFS 0x01000000 259bdcf336SManuel Lauss 269bdcf336SManuel Lauss #define DB1550_BCSR_PHYS_ADDR 0x0F000000 279bdcf336SManuel Lauss #define DB1550_BCSR_HEXLED_OFS 0x00400000 289bdcf336SManuel Lauss 299bdcf336SManuel Lauss #define PB1550_BCSR_PHYS_ADDR 0x0F000000 309bdcf336SManuel Lauss #define PB1550_BCSR_HEXLED_OFS 0x00800000 319bdcf336SManuel Lauss 329bdcf336SManuel Lauss #define DB1200_BCSR_PHYS_ADDR 0x19800000 339bdcf336SManuel Lauss #define DB1200_BCSR_HEXLED_OFS 0x00400000 349bdcf336SManuel Lauss 359bdcf336SManuel Lauss #define PB1200_BCSR_PHYS_ADDR 0x0D800000 369bdcf336SManuel Lauss #define PB1200_BCSR_HEXLED_OFS 0x00400000 379bdcf336SManuel Lauss 3864cd04d0SManuel Lauss #define DB1300_BCSR_PHYS_ADDR 0x19800000 3964cd04d0SManuel Lauss #define DB1300_BCSR_HEXLED_OFS 0x00400000 409bdcf336SManuel Lauss 419bdcf336SManuel Lauss enum bcsr_id { 429bdcf336SManuel Lauss /* BCSR base 1 */ 439bdcf336SManuel Lauss BCSR_WHOAMI = 0, 449bdcf336SManuel Lauss BCSR_STATUS, 459bdcf336SManuel Lauss BCSR_SWITCHES, 469bdcf336SManuel Lauss BCSR_RESETS, 479bdcf336SManuel Lauss BCSR_PCMCIA, 489bdcf336SManuel Lauss BCSR_BOARD, 499bdcf336SManuel Lauss BCSR_LEDS, 509bdcf336SManuel Lauss BCSR_SYSTEM, 519bdcf336SManuel Lauss /* Au1200/1300 based boards */ 529bdcf336SManuel Lauss BCSR_INTCLR, 539bdcf336SManuel Lauss BCSR_INTSET, 549bdcf336SManuel Lauss BCSR_MASKCLR, 559bdcf336SManuel Lauss BCSR_MASKSET, 569bdcf336SManuel Lauss BCSR_SIGSTAT, 579bdcf336SManuel Lauss BCSR_INTSTAT, 589bdcf336SManuel Lauss 599bdcf336SManuel Lauss /* BCSR base 2 */ 609bdcf336SManuel Lauss BCSR_HEXLEDS, 619bdcf336SManuel Lauss BCSR_RSVD1, 629bdcf336SManuel Lauss BCSR_HEXCLEAR, 639bdcf336SManuel Lauss 649bdcf336SManuel Lauss BCSR_CNT, 659bdcf336SManuel Lauss }; 669bdcf336SManuel Lauss 679bdcf336SManuel Lauss /* register offsets, valid for all Db1xxx/Pb1xxx boards */ 689bdcf336SManuel Lauss #define BCSR_REG_WHOAMI 0x00 699bdcf336SManuel Lauss #define BCSR_REG_STATUS 0x04 709bdcf336SManuel Lauss #define BCSR_REG_SWITCHES 0x08 719bdcf336SManuel Lauss #define BCSR_REG_RESETS 0x0c 729bdcf336SManuel Lauss #define BCSR_REG_PCMCIA 0x10 739bdcf336SManuel Lauss #define BCSR_REG_BOARD 0x14 749bdcf336SManuel Lauss #define BCSR_REG_LEDS 0x18 759bdcf336SManuel Lauss #define BCSR_REG_SYSTEM 0x1c 769bdcf336SManuel Lauss /* Au1200/Au1300 based boards: CPLD IRQ muxer */ 779bdcf336SManuel Lauss #define BCSR_REG_INTCLR 0x20 789bdcf336SManuel Lauss #define BCSR_REG_INTSET 0x24 799bdcf336SManuel Lauss #define BCSR_REG_MASKCLR 0x28 809bdcf336SManuel Lauss #define BCSR_REG_MASKSET 0x2c 819bdcf336SManuel Lauss #define BCSR_REG_SIGSTAT 0x30 829bdcf336SManuel Lauss #define BCSR_REG_INTSTAT 0x34 839bdcf336SManuel Lauss 849bdcf336SManuel Lauss /* hexled control, offset from BCSR base 2 */ 859bdcf336SManuel Lauss #define BCSR_REG_HEXLEDS 0x00 869bdcf336SManuel Lauss #define BCSR_REG_HEXCLEAR 0x08 879bdcf336SManuel Lauss 889bdcf336SManuel Lauss /* 899bdcf336SManuel Lauss * Register Bits and Pieces. 909bdcf336SManuel Lauss */ 919bdcf336SManuel Lauss #define BCSR_WHOAMI_DCID(x) ((x) & 0xf) 929bdcf336SManuel Lauss #define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf) 939bdcf336SManuel Lauss #define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf) 949bdcf336SManuel Lauss 959bdcf336SManuel Lauss /* register "WHOAMI" bits 11:8 identify the board */ 969bdcf336SManuel Lauss enum bcsr_whoami_boards { 979bdcf336SManuel Lauss BCSR_WHOAMI_PB1500 = 1, 989bdcf336SManuel Lauss BCSR_WHOAMI_PB1500R2, 999bdcf336SManuel Lauss BCSR_WHOAMI_PB1100, 1009bdcf336SManuel Lauss BCSR_WHOAMI_DB1000, 1019bdcf336SManuel Lauss BCSR_WHOAMI_DB1100, 1029bdcf336SManuel Lauss BCSR_WHOAMI_DB1500, 1039bdcf336SManuel Lauss BCSR_WHOAMI_DB1550, 1049bdcf336SManuel Lauss BCSR_WHOAMI_PB1550_DDR, 1059bdcf336SManuel Lauss BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR, 1069bdcf336SManuel Lauss BCSR_WHOAMI_PB1550_SDR, 1079bdcf336SManuel Lauss BCSR_WHOAMI_PB1200_DDR1, 1089bdcf336SManuel Lauss BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 1099bdcf336SManuel Lauss BCSR_WHOAMI_PB1200_DDR2, 1109bdcf336SManuel Lauss BCSR_WHOAMI_DB1200, 11164cd04d0SManuel Lauss BCSR_WHOAMI_DB1300, 1129bdcf336SManuel Lauss }; 1139bdcf336SManuel Lauss 1149bdcf336SManuel Lauss /* STATUS reg. Unless otherwise noted, they're valid on all boards. 1159bdcf336SManuel Lauss * PB1200 = DB1200. 1169bdcf336SManuel Lauss */ 1179bdcf336SManuel Lauss #define BCSR_STATUS_PC0VS 0x0003 1189bdcf336SManuel Lauss #define BCSR_STATUS_PC1VS 0x000C 1199bdcf336SManuel Lauss #define BCSR_STATUS_PC0FI 0x0010 1209bdcf336SManuel Lauss #define BCSR_STATUS_PC1FI 0x0020 1219bdcf336SManuel Lauss #define BCSR_STATUS_PB1550_SWAPBOOT 0x0040 1229bdcf336SManuel Lauss #define BCSR_STATUS_SRAMWIDTH 0x0080 1239bdcf336SManuel Lauss #define BCSR_STATUS_FLASHBUSY 0x0100 1249bdcf336SManuel Lauss #define BCSR_STATUS_ROMBUSY 0x0400 12564cd04d0SManuel Lauss #define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ 1269bdcf336SManuel Lauss #define BCSR_STATUS_SD1WP 0x0800 1279bdcf336SManuel Lauss #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 1289bdcf336SManuel Lauss #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 12964cd04d0SManuel Lauss #define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ 13064cd04d0SManuel Lauss #define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ 1319bdcf336SManuel Lauss #define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 1329bdcf336SManuel Lauss #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 1339bdcf336SManuel Lauss #define BCSR_STATUS_FLASHDEN 0xC000 1349bdcf336SManuel Lauss #define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */ 1359bdcf336SManuel Lauss #define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */ 1369bdcf336SManuel Lauss #define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */ 1379bdcf336SManuel Lauss #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 1389bdcf336SManuel Lauss #define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 1399bdcf336SManuel Lauss 14064cd04d0SManuel Lauss #define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ 14164cd04d0SManuel Lauss #define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ 14264cd04d0SManuel Lauss #define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ 14364cd04d0SManuel Lauss #define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ 14464cd04d0SManuel Lauss #define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ 1459bdcf336SManuel Lauss 1469bdcf336SManuel Lauss /* DB/PB1000,1100,1500,1550 */ 1479bdcf336SManuel Lauss #define BCSR_RESETS_PHY0 0x0001 1489bdcf336SManuel Lauss #define BCSR_RESETS_PHY1 0x0002 1499bdcf336SManuel Lauss #define BCSR_RESETS_DC 0x0004 1509bdcf336SManuel Lauss #define BCSR_RESETS_FIR_SEL 0x2000 1519bdcf336SManuel Lauss #define BCSR_RESETS_IRDA_MODE_MASK 0xC000 1529bdcf336SManuel Lauss #define BCSR_RESETS_IRDA_MODE_FULL 0x0000 1539bdcf336SManuel Lauss #define BCSR_RESETS_PB1550_WSCFSM 0x2000 1549bdcf336SManuel Lauss #define BCSR_RESETS_IRDA_MODE_OFF 0x4000 1559bdcf336SManuel Lauss #define BCSR_RESETS_IRDA_MODE_2_3 0x8000 1569bdcf336SManuel Lauss #define BCSR_RESETS_IRDA_MODE_1_3 0xC000 1579bdcf336SManuel Lauss #define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */ 1589bdcf336SManuel Lauss 1599bdcf336SManuel Lauss #define BCSR_BOARD_PCIM66EN 0x0001 1609bdcf336SManuel Lauss #define BCSR_BOARD_SD0PWR 0x0040 1619bdcf336SManuel Lauss #define BCSR_BOARD_SD1PWR 0x0080 1629bdcf336SManuel Lauss #define BCSR_BOARD_PCIM33 0x0100 1639bdcf336SManuel Lauss #define BCSR_BOARD_PCIEXTARB 0x0200 1649bdcf336SManuel Lauss #define BCSR_BOARD_GPIO200RST 0x0400 1659bdcf336SManuel Lauss #define BCSR_BOARD_PCICLKOUT 0x0800 166851d4f5dSManuel Lauss #define BCSR_BOARD_PB1100_SD0PWR 0x0400 167851d4f5dSManuel Lauss #define BCSR_BOARD_PB1100_SD1PWR 0x0800 1689bdcf336SManuel Lauss #define BCSR_BOARD_PCICFG 0x1000 169f869d42eSManuel Lauss #define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ 1709bdcf336SManuel Lauss #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 1719bdcf336SManuel Lauss #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 1729bdcf336SManuel Lauss 1739bdcf336SManuel Lauss 17464cd04d0SManuel Lauss /* DB/PB1200/1300 */ 1759bdcf336SManuel Lauss #define BCSR_RESETS_ETH 0x0001 1769bdcf336SManuel Lauss #define BCSR_RESETS_CAMERA 0x0002 1779bdcf336SManuel Lauss #define BCSR_RESETS_DC 0x0004 1789bdcf336SManuel Lauss #define BCSR_RESETS_IDE 0x0008 17964cd04d0SManuel Lauss #define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ 1809bdcf336SManuel Lauss /* Not resets but in the same register */ 1819bdcf336SManuel Lauss #define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 1829bdcf336SManuel Lauss #define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 1839bdcf336SManuel Lauss #define BCSR_RESETS_PSC0MUX 0x1000 1849bdcf336SManuel Lauss #define BCSR_RESETS_PSC1MUX 0x2000 1859bdcf336SManuel Lauss #define BCSR_RESETS_SPISEL 0x4000 1869bdcf336SManuel Lauss #define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 1879bdcf336SManuel Lauss 18864cd04d0SManuel Lauss #define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ 18964cd04d0SManuel Lauss #define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ 19064cd04d0SManuel Lauss #define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ 19164cd04d0SManuel Lauss #define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ 19264cd04d0SManuel Lauss #define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ 19364cd04d0SManuel Lauss #define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ 19464cd04d0SManuel Lauss #define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ 19564cd04d0SManuel Lauss 1969bdcf336SManuel Lauss #define BCSR_BOARD_LCDVEE 0x0001 1979bdcf336SManuel Lauss #define BCSR_BOARD_LCDVDD 0x0002 1989bdcf336SManuel Lauss #define BCSR_BOARD_LCDBL 0x0004 1999bdcf336SManuel Lauss #define BCSR_BOARD_CAMSNAP 0x0010 2009bdcf336SManuel Lauss #define BCSR_BOARD_CAMPWR 0x0020 2019bdcf336SManuel Lauss #define BCSR_BOARD_SD0PWR 0x0040 20264cd04d0SManuel Lauss #define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ 20364cd04d0SManuel Lauss #define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ 2049bdcf336SManuel Lauss 2059bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP 0x00FF 2069bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_1 0x0080 2079bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_2 0x0040 2089bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_3 0x0020 2099bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_4 0x0010 2109bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_5 0x0008 2119bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_6 0x0004 2129bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_7 0x0002 2139bdcf336SManuel Lauss #define BCSR_SWITCHES_DIP_8 0x0001 2149bdcf336SManuel Lauss #define BCSR_SWITCHES_ROTARY 0x0F00 2159bdcf336SManuel Lauss 2169bdcf336SManuel Lauss 2179bdcf336SManuel Lauss #define BCSR_PCMCIA_PC0VPP 0x0003 2189bdcf336SManuel Lauss #define BCSR_PCMCIA_PC0VCC 0x000C 2199bdcf336SManuel Lauss #define BCSR_PCMCIA_PC0DRVEN 0x0010 2209bdcf336SManuel Lauss #define BCSR_PCMCIA_PC0RST 0x0080 2219bdcf336SManuel Lauss #define BCSR_PCMCIA_PC1VPP 0x0300 2229bdcf336SManuel Lauss #define BCSR_PCMCIA_PC1VCC 0x0C00 2239bdcf336SManuel Lauss #define BCSR_PCMCIA_PC1DRVEN 0x1000 2249bdcf336SManuel Lauss #define BCSR_PCMCIA_PC1RST 0x8000 2259bdcf336SManuel Lauss 2269bdcf336SManuel Lauss 2279bdcf336SManuel Lauss #define BCSR_LEDS_DECIMALS 0x0003 2289bdcf336SManuel Lauss #define BCSR_LEDS_LED0 0x0100 2299bdcf336SManuel Lauss #define BCSR_LEDS_LED1 0x0200 2309bdcf336SManuel Lauss #define BCSR_LEDS_LED2 0x0400 2319bdcf336SManuel Lauss #define BCSR_LEDS_LED3 0x0800 2329bdcf336SManuel Lauss 2339bdcf336SManuel Lauss 2349bdcf336SManuel Lauss #define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 2359bdcf336SManuel Lauss #define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 2369bdcf336SManuel Lauss #define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 23764cd04d0SManuel Lauss #define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ 23864cd04d0SManuel Lauss #define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ 23964cd04d0SManuel Lauss #define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ 24064cd04d0SManuel Lauss #define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ 2419bdcf336SManuel Lauss 2429bdcf336SManuel Lauss 2439bdcf336SManuel Lauss 2449bdcf336SManuel Lauss /* initialize BCSR for a board. Provide the PHYSICAL addresses of both 2459bdcf336SManuel Lauss * BCSR spaces. 2469bdcf336SManuel Lauss */ 2479bdcf336SManuel Lauss void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys); 2489bdcf336SManuel Lauss 2499bdcf336SManuel Lauss /* read a board register */ 2509bdcf336SManuel Lauss unsigned short bcsr_read(enum bcsr_id reg); 2519bdcf336SManuel Lauss 2529bdcf336SManuel Lauss /* write to a board register */ 2539bdcf336SManuel Lauss void bcsr_write(enum bcsr_id reg, unsigned short val); 2549bdcf336SManuel Lauss 2559bdcf336SManuel Lauss /* modify a register. clear bits set in 'clr', set bits set in 'set' */ 2569bdcf336SManuel Lauss void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); 2579bdcf336SManuel Lauss 25895a43796SManuel Lauss /* install CPLD IRQ demuxer (DB1200/PB1200) */ 25995a43796SManuel Lauss void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq); 26095a43796SManuel Lauss 2619bdcf336SManuel Lauss #endif 262