1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2008 Cavium Networks
7  */
8 #ifndef __OCTEON_IRQ_H__
9 #define __OCTEON_IRQ_H__
10 
11 #define NR_IRQS OCTEON_IRQ_LAST
12 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13 
14 enum octeon_irq {
15 /* 1 - 8 represent the 8 MIPS standard interrupt sources */
16 	OCTEON_IRQ_SW0 = 1,
17 	OCTEON_IRQ_SW1,
18 /* CIU0, CUI2, CIU4 are 3, 4, 5 */
19 	OCTEON_IRQ_5 = 6,
20 	OCTEON_IRQ_PERF,
21 	OCTEON_IRQ_TIMER,
22 /* sources in CIU_INTX_EN0 */
23 	OCTEON_IRQ_WORKQ0,
24 	OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
25 	OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
26 	OCTEON_IRQ_MBOX1,
27 	OCTEON_IRQ_MBOX2,
28 	OCTEON_IRQ_MBOX3,
29 	OCTEON_IRQ_PCI_INT0,
30 	OCTEON_IRQ_PCI_INT1,
31 	OCTEON_IRQ_PCI_INT2,
32 	OCTEON_IRQ_PCI_INT3,
33 	OCTEON_IRQ_PCI_MSI0,
34 	OCTEON_IRQ_PCI_MSI1,
35 	OCTEON_IRQ_PCI_MSI2,
36 	OCTEON_IRQ_PCI_MSI3,
37 
38 	OCTEON_IRQ_TWSI,
39 	OCTEON_IRQ_TWSI2,
40 	OCTEON_IRQ_RML,
41 	OCTEON_IRQ_TIMER0,
42 	OCTEON_IRQ_TIMER1,
43 	OCTEON_IRQ_TIMER2,
44 	OCTEON_IRQ_TIMER3,
45 	OCTEON_IRQ_USB0,
46 	OCTEON_IRQ_USB1,
47 #ifndef CONFIG_PCI_MSI
48 	OCTEON_IRQ_LAST = 127
49 #endif
50 };
51 
52 #ifdef CONFIG_PCI_MSI
53 /* 256 - 511 represent the MSI interrupts 0-255 */
54 #define OCTEON_IRQ_MSI_BIT0	(256)
55 
56 #define OCTEON_IRQ_MSI_LAST	 (OCTEON_IRQ_MSI_BIT0 + 255)
57 #define OCTEON_IRQ_LAST		 (OCTEON_IRQ_MSI_LAST + 1)
58 #endif
59 
60 #endif
61