xref: /openbmc/linux/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h (revision b8bb76713ec50df2f11efee386e16f93d51e1076)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004 Cavium Networks
7  */
8 #ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
9 #define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
10 
11 #include <linux/types.h>
12 #include <asm/mipsregs.h>
13 
14 /*
15  * Cavium Octeons are MIPS64v2 processors
16  */
17 #define cpu_dcache_line_size()	128
18 #define cpu_icache_line_size()	128
19 
20 
21 #define cpu_has_4kex		1
22 #define cpu_has_3k_cache	0
23 #define cpu_has_4k_cache	0
24 #define cpu_has_tx39_cache	0
25 #define cpu_has_fpu		0
26 #define cpu_has_counter		1
27 #define cpu_has_watch		1
28 #define cpu_has_divec		1
29 #define cpu_has_vce		0
30 #define cpu_has_cache_cdex_p	0
31 #define cpu_has_cache_cdex_s	0
32 #define cpu_has_prefetch	1
33 
34 /*
35  * We should disable LL/SC on non SMP systems as it is faster to
36  * disable interrupts for atomic access than a LL/SC.  Unfortunatly we
37  * cannot as this breaks asm/futex.h
38  */
39 #define cpu_has_llsc		1
40 #define cpu_has_vtag_icache	1
41 #define cpu_has_dc_aliases	0
42 #define cpu_has_ic_fills_f_dc	0
43 #define cpu_has_64bits		1
44 #define cpu_has_octeon_cache	1
45 #define cpu_has_saa		octeon_has_saa()
46 #define cpu_has_mips32r1	0
47 #define cpu_has_mips32r2	0
48 #define cpu_has_mips64r1	0
49 #define cpu_has_mips64r2	1
50 #define cpu_has_dsp		0
51 #define cpu_has_mipsmt		0
52 #define cpu_has_userlocal	0
53 #define cpu_has_vint		0
54 #define cpu_has_veic		0
55 #define ARCH_HAS_READ_CURRENT_TIMER 1
56 #define ARCH_HAS_IRQ_PER_CPU	1
57 #define ARCH_HAS_SPINLOCK_PREFETCH 1
58 #define spin_lock_prefetch(x) prefetch(x)
59 #define PREFETCH_STRIDE 128
60 
61 static inline int read_current_timer(unsigned long *result)
62 {
63 	asm volatile ("rdhwr %0,$31\n"
64 #ifndef CONFIG_64BIT
65 		      "\tsll %0, 0"
66 #endif
67 		      : "=r" (*result));
68 	return 0;
69 }
70 
71 static inline int octeon_has_saa(void)
72 {
73 	int id;
74 	asm volatile ("mfc0 %0, $15,0" : "=r" (id));
75 	return id >= 0x000d0300;
76 }
77 
78 #endif
79