1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004 Cavium Networks
7  */
8 #ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
9 #define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
10 
11 #include <linux/types.h>
12 #include <asm/mipsregs.h>
13 
14 /*
15  * Cavium Octeons are MIPS64v2 processors
16  */
17 #define cpu_dcache_line_size()	128
18 #define cpu_icache_line_size()	128
19 
20 
21 #define cpu_has_4kex		1
22 #define cpu_has_3k_cache	0
23 #define cpu_has_4k_cache	0
24 #define cpu_has_counter		1
25 #define cpu_has_watch		1
26 #define cpu_has_divec		1
27 #define cpu_has_vce		0
28 #define cpu_has_cache_cdex_p	0
29 #define cpu_has_cache_cdex_s	0
30 #define cpu_has_prefetch	1
31 
32 #define cpu_has_llsc		1
33 /*
34  * We Disable LL/SC on non SMP systems as it is faster to disable
35  * interrupts for atomic access than a LL/SC.
36  */
37 #ifdef CONFIG_SMP
38 # define kernel_uses_llsc	1
39 #else
40 # define kernel_uses_llsc	0
41 #endif
42 #define cpu_has_vtag_icache	1
43 #define cpu_has_dc_aliases	0
44 #define cpu_has_ic_fills_f_dc	0
45 #define cpu_has_64bits		1
46 #define cpu_has_octeon_cache	1
47 #define cpu_has_mips32r1	1
48 #define cpu_has_mips32r2	1
49 #define cpu_has_mips64r1	1
50 #define cpu_has_mips64r2	1
51 #define cpu_has_dsp		0
52 #define cpu_has_dsp2		0
53 #define cpu_has_mipsmt		0
54 #define cpu_has_vint		0
55 #define cpu_has_veic		0
56 #define cpu_hwrena_impl_bits	(MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
57 #define cpu_has_wsbh            1
58 
59 #define cpu_has_rixi		(cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
60 
61 #define ARCH_HAS_SPINLOCK_PREFETCH 1
62 #define spin_lock_prefetch(x) prefetch(x)
63 #define PREFETCH_STRIDE 128
64 
65 #ifdef __OCTEON__
66 /*
67  * All gcc versions that have OCTEON support define __OCTEON__ and have the
68  *  __builtin_popcount support.
69  */
70 #define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
71 #endif
72 
73 /*
74  * The last 256MB are reserved for device to device mappings and the
75  * BAR1 hole.
76  */
77 #define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
78 
79 #endif
80