1 #ifndef BCM63XX_REGS_H_ 2 #define BCM63XX_REGS_H_ 3 4 /************************************************************************* 5 * _REG relative to RSET_PERF 6 *************************************************************************/ 7 8 /* Chip Identifier / Revision register */ 9 #define PERF_REV_REG 0x0 10 #define REV_CHIPID_SHIFT 16 11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 12 #define REV_REVID_SHIFT 0 13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) 14 15 /* Clock Control register */ 16 #define PERF_CKCTL_REG 0x4 17 18 #define CKCTL_6328_PHYMIPS_EN (1 << 0) 19 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) 20 #define CKCTL_6328_ADSL_AFE_EN (1 << 2) 21 #define CKCTL_6328_ADSL_EN (1 << 3) 22 #define CKCTL_6328_MIPS_EN (1 << 4) 23 #define CKCTL_6328_SAR_EN (1 << 5) 24 #define CKCTL_6328_PCM_EN (1 << 6) 25 #define CKCTL_6328_USBD_EN (1 << 7) 26 #define CKCTL_6328_USBH_EN (1 << 8) 27 #define CKCTL_6328_HSSPI_EN (1 << 9) 28 #define CKCTL_6328_PCIE_EN (1 << 10) 29 #define CKCTL_6328_ROBOSW_EN (1 << 11) 30 31 #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \ 32 CKCTL_6328_ADSL_QPROC_EN | \ 33 CKCTL_6328_ADSL_AFE_EN | \ 34 CKCTL_6328_ADSL_EN | \ 35 CKCTL_6328_SAR_EN | \ 36 CKCTL_6328_PCM_EN | \ 37 CKCTL_6328_USBD_EN | \ 38 CKCTL_6328_USBH_EN | \ 39 CKCTL_6328_ROBOSW_EN | \ 40 CKCTL_6328_PCIE_EN) 41 42 #define CKCTL_6338_ADSLPHY_EN (1 << 0) 43 #define CKCTL_6338_MPI_EN (1 << 1) 44 #define CKCTL_6338_DRAM_EN (1 << 2) 45 #define CKCTL_6338_ENET_EN (1 << 4) 46 #define CKCTL_6338_USBS_EN (1 << 4) 47 #define CKCTL_6338_SAR_EN (1 << 5) 48 #define CKCTL_6338_SPI_EN (1 << 9) 49 50 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ 51 CKCTL_6338_MPI_EN | \ 52 CKCTL_6338_ENET_EN | \ 53 CKCTL_6338_SAR_EN | \ 54 CKCTL_6338_SPI_EN) 55 56 /* BCM6345 clock bits are shifted by 16 on the left, because of the test 57 * control register which is 16-bits wide. That way we do not have any 58 * specific BCM6345 code for handling clocks, and writing 0 to the test 59 * control register is fine. 60 */ 61 #define CKCTL_6345_CPU_EN (1 << 16) 62 #define CKCTL_6345_BUS_EN (1 << 17) 63 #define CKCTL_6345_EBI_EN (1 << 18) 64 #define CKCTL_6345_UART_EN (1 << 19) 65 #define CKCTL_6345_ADSLPHY_EN (1 << 20) 66 #define CKCTL_6345_ENET_EN (1 << 23) 67 #define CKCTL_6345_USBH_EN (1 << 24) 68 69 #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 70 CKCTL_6345_USBH_EN | \ 71 CKCTL_6345_ADSLPHY_EN) 72 73 #define CKCTL_6348_ADSLPHY_EN (1 << 0) 74 #define CKCTL_6348_MPI_EN (1 << 1) 75 #define CKCTL_6348_SDRAM_EN (1 << 2) 76 #define CKCTL_6348_M2M_EN (1 << 3) 77 #define CKCTL_6348_ENET_EN (1 << 4) 78 #define CKCTL_6348_SAR_EN (1 << 5) 79 #define CKCTL_6348_USBS_EN (1 << 6) 80 #define CKCTL_6348_USBH_EN (1 << 8) 81 #define CKCTL_6348_SPI_EN (1 << 9) 82 83 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ 84 CKCTL_6348_M2M_EN | \ 85 CKCTL_6348_ENET_EN | \ 86 CKCTL_6348_SAR_EN | \ 87 CKCTL_6348_USBS_EN | \ 88 CKCTL_6348_USBH_EN | \ 89 CKCTL_6348_SPI_EN) 90 91 #define CKCTL_6358_ENET_EN (1 << 4) 92 #define CKCTL_6358_ADSLPHY_EN (1 << 5) 93 #define CKCTL_6358_PCM_EN (1 << 8) 94 #define CKCTL_6358_SPI_EN (1 << 9) 95 #define CKCTL_6358_USBS_EN (1 << 10) 96 #define CKCTL_6358_SAR_EN (1 << 11) 97 #define CKCTL_6358_EMUSB_EN (1 << 17) 98 #define CKCTL_6358_ENET0_EN (1 << 18) 99 #define CKCTL_6358_ENET1_EN (1 << 19) 100 #define CKCTL_6358_USBSU_EN (1 << 20) 101 #define CKCTL_6358_EPHY_EN (1 << 21) 102 103 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ 104 CKCTL_6358_ADSLPHY_EN | \ 105 CKCTL_6358_PCM_EN | \ 106 CKCTL_6358_SPI_EN | \ 107 CKCTL_6358_USBS_EN | \ 108 CKCTL_6358_SAR_EN | \ 109 CKCTL_6358_EMUSB_EN | \ 110 CKCTL_6358_ENET0_EN | \ 111 CKCTL_6358_ENET1_EN | \ 112 CKCTL_6358_USBSU_EN | \ 113 CKCTL_6358_EPHY_EN) 114 115 #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) 116 #define CKCTL_6368_VDSL_AFE_EN (1 << 3) 117 #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) 118 #define CKCTL_6368_VDSL_EN (1 << 5) 119 #define CKCTL_6368_PHYMIPS_EN (1 << 6) 120 #define CKCTL_6368_SWPKT_USB_EN (1 << 7) 121 #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) 122 #define CKCTL_6368_SPI_EN (1 << 9) 123 #define CKCTL_6368_USBD_EN (1 << 10) 124 #define CKCTL_6368_SAR_EN (1 << 11) 125 #define CKCTL_6368_ROBOSW_EN (1 << 12) 126 #define CKCTL_6368_UTOPIA_EN (1 << 13) 127 #define CKCTL_6368_PCM_EN (1 << 14) 128 #define CKCTL_6368_USBH_EN (1 << 15) 129 #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) 130 #define CKCTL_6368_NAND_EN (1 << 17) 131 #define CKCTL_6368_IPSEC_EN (1 << 18) 132 133 #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ 134 CKCTL_6368_SWPKT_SAR_EN | \ 135 CKCTL_6368_SPI_EN | \ 136 CKCTL_6368_USBD_EN | \ 137 CKCTL_6368_SAR_EN | \ 138 CKCTL_6368_ROBOSW_EN | \ 139 CKCTL_6368_UTOPIA_EN | \ 140 CKCTL_6368_PCM_EN | \ 141 CKCTL_6368_USBH_EN | \ 142 CKCTL_6368_DISABLE_GLESS_EN | \ 143 CKCTL_6368_NAND_EN | \ 144 CKCTL_6368_IPSEC_EN) 145 146 /* System PLL Control register */ 147 #define PERF_SYS_PLL_CTL_REG 0x8 148 #define SYS_PLL_SOFT_RESET 0x1 149 150 /* Interrupt Mask register */ 151 #define PERF_IRQMASK_6328_REG 0x20 152 #define PERF_IRQMASK_6338_REG 0xc 153 #define PERF_IRQMASK_6345_REG 0xc 154 #define PERF_IRQMASK_6348_REG 0xc 155 #define PERF_IRQMASK_6358_REG 0xc 156 #define PERF_IRQMASK_6368_REG 0x20 157 158 /* Interrupt Status register */ 159 #define PERF_IRQSTAT_6328_REG 0x28 160 #define PERF_IRQSTAT_6338_REG 0x10 161 #define PERF_IRQSTAT_6345_REG 0x10 162 #define PERF_IRQSTAT_6348_REG 0x10 163 #define PERF_IRQSTAT_6358_REG 0x10 164 #define PERF_IRQSTAT_6368_REG 0x28 165 166 /* External Interrupt Configuration register */ 167 #define PERF_EXTIRQ_CFG_REG_6328 0x18 168 #define PERF_EXTIRQ_CFG_REG_6338 0x14 169 #define PERF_EXTIRQ_CFG_REG_6345 0x14 170 #define PERF_EXTIRQ_CFG_REG_6348 0x14 171 #define PERF_EXTIRQ_CFG_REG_6358 0x14 172 #define PERF_EXTIRQ_CFG_REG_6368 0x18 173 174 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c 175 176 /* for 6348 only */ 177 #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) 178 #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5)) 179 #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10)) 180 #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15)) 181 #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20)) 182 #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25)) 183 #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10) 184 #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15) 185 186 /* for all others */ 187 #define EXTIRQ_CFG_SENSE(x) (1 << (x)) 188 #define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) 189 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) 190 #define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) 191 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) 192 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) 193 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) 194 #define EXTIRQ_CFG_MASK_ALL (0xf << 12) 195 196 /* Soft Reset register */ 197 #define PERF_SOFTRESET_REG 0x28 198 #define PERF_SOFTRESET_6328_REG 0x10 199 #define PERF_SOFTRESET_6358_REG 0x34 200 #define PERF_SOFTRESET_6368_REG 0x10 201 202 #define SOFTRESET_6328_SPI_MASK (1 << 0) 203 #define SOFTRESET_6328_EPHY_MASK (1 << 1) 204 #define SOFTRESET_6328_SAR_MASK (1 << 2) 205 #define SOFTRESET_6328_ENETSW_MASK (1 << 3) 206 #define SOFTRESET_6328_USBS_MASK (1 << 4) 207 #define SOFTRESET_6328_USBH_MASK (1 << 5) 208 #define SOFTRESET_6328_PCM_MASK (1 << 6) 209 #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7) 210 #define SOFTRESET_6328_PCIE_MASK (1 << 8) 211 #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9) 212 #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10) 213 214 #define SOFTRESET_6338_SPI_MASK (1 << 0) 215 #define SOFTRESET_6338_ENET_MASK (1 << 2) 216 #define SOFTRESET_6338_USBH_MASK (1 << 3) 217 #define SOFTRESET_6338_USBS_MASK (1 << 4) 218 #define SOFTRESET_6338_ADSL_MASK (1 << 5) 219 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) 220 #define SOFTRESET_6338_SAR_MASK (1 << 7) 221 #define SOFTRESET_6338_ACLC_MASK (1 << 8) 222 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) 223 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ 224 SOFTRESET_6338_ENET_MASK | \ 225 SOFTRESET_6338_USBH_MASK | \ 226 SOFTRESET_6338_USBS_MASK | \ 227 SOFTRESET_6338_ADSL_MASK | \ 228 SOFTRESET_6338_DMAMEM_MASK | \ 229 SOFTRESET_6338_SAR_MASK | \ 230 SOFTRESET_6338_ACLC_MASK | \ 231 SOFTRESET_6338_ADSLMIPSPLL_MASK) 232 233 #define SOFTRESET_6348_SPI_MASK (1 << 0) 234 #define SOFTRESET_6348_ENET_MASK (1 << 2) 235 #define SOFTRESET_6348_USBH_MASK (1 << 3) 236 #define SOFTRESET_6348_USBS_MASK (1 << 4) 237 #define SOFTRESET_6348_ADSL_MASK (1 << 5) 238 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) 239 #define SOFTRESET_6348_SAR_MASK (1 << 7) 240 #define SOFTRESET_6348_ACLC_MASK (1 << 8) 241 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) 242 243 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ 244 SOFTRESET_6348_ENET_MASK | \ 245 SOFTRESET_6348_USBH_MASK | \ 246 SOFTRESET_6348_USBS_MASK | \ 247 SOFTRESET_6348_ADSL_MASK | \ 248 SOFTRESET_6348_DMAMEM_MASK | \ 249 SOFTRESET_6348_SAR_MASK | \ 250 SOFTRESET_6348_ACLC_MASK | \ 251 SOFTRESET_6348_ADSLMIPSPLL_MASK) 252 253 #define SOFTRESET_6358_SPI_MASK (1 << 0) 254 #define SOFTRESET_6358_ENET_MASK (1 << 2) 255 #define SOFTRESET_6358_MPI_MASK (1 << 3) 256 #define SOFTRESET_6358_EPHY_MASK (1 << 6) 257 #define SOFTRESET_6358_SAR_MASK (1 << 7) 258 #define SOFTRESET_6358_USBH_MASK (1 << 12) 259 #define SOFTRESET_6358_PCM_MASK (1 << 13) 260 #define SOFTRESET_6358_ADSL_MASK (1 << 14) 261 262 #define SOFTRESET_6368_SPI_MASK (1 << 0) 263 #define SOFTRESET_6368_MPI_MASK (1 << 3) 264 #define SOFTRESET_6368_EPHY_MASK (1 << 6) 265 #define SOFTRESET_6368_SAR_MASK (1 << 7) 266 #define SOFTRESET_6368_ENETSW_MASK (1 << 10) 267 #define SOFTRESET_6368_USBS_MASK (1 << 11) 268 #define SOFTRESET_6368_USBH_MASK (1 << 12) 269 #define SOFTRESET_6368_PCM_MASK (1 << 13) 270 271 /* MIPS PLL control register */ 272 #define PERF_MIPSPLLCTL_REG 0x34 273 #define MIPSPLLCTL_N1_SHIFT 20 274 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) 275 #define MIPSPLLCTL_N2_SHIFT 15 276 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) 277 #define MIPSPLLCTL_M1REF_SHIFT 12 278 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) 279 #define MIPSPLLCTL_M2REF_SHIFT 9 280 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) 281 #define MIPSPLLCTL_M1CPU_SHIFT 6 282 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) 283 #define MIPSPLLCTL_M1BUS_SHIFT 3 284 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) 285 #define MIPSPLLCTL_M2BUS_SHIFT 0 286 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) 287 288 /* ADSL PHY PLL Control register */ 289 #define PERF_ADSLPLLCTL_REG 0x38 290 #define ADSLPLLCTL_N1_SHIFT 20 291 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) 292 #define ADSLPLLCTL_N2_SHIFT 15 293 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) 294 #define ADSLPLLCTL_M1REF_SHIFT 12 295 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) 296 #define ADSLPLLCTL_M2REF_SHIFT 9 297 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) 298 #define ADSLPLLCTL_M1CPU_SHIFT 6 299 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) 300 #define ADSLPLLCTL_M1BUS_SHIFT 3 301 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) 302 #define ADSLPLLCTL_M2BUS_SHIFT 0 303 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) 304 305 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ 306 (((n1) << ADSLPLLCTL_N1_SHIFT) | \ 307 ((n2) << ADSLPLLCTL_N2_SHIFT) | \ 308 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ 309 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ 310 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ 311 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ 312 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) 313 314 315 /************************************************************************* 316 * _REG relative to RSET_TIMER 317 *************************************************************************/ 318 319 #define BCM63XX_TIMER_COUNT 4 320 #define TIMER_T0_ID 0 321 #define TIMER_T1_ID 1 322 #define TIMER_T2_ID 2 323 #define TIMER_WDT_ID 3 324 325 /* Timer irqstat register */ 326 #define TIMER_IRQSTAT_REG 0 327 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) 328 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) 329 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) 330 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) 331 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) 332 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) 333 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) 334 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) 335 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) 336 337 /* Timer control register */ 338 #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) 339 #define TIMER_CTL0_REG 0x4 340 #define TIMER_CTL1_REG 0x8 341 #define TIMER_CTL2_REG 0xC 342 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) 343 #define TIMER_CTL_MONOTONIC_MASK (1 << 30) 344 #define TIMER_CTL_ENABLE_MASK (1 << 31) 345 346 347 /************************************************************************* 348 * _REG relative to RSET_WDT 349 *************************************************************************/ 350 351 /* Watchdog default count register */ 352 #define WDT_DEFVAL_REG 0x0 353 354 /* Watchdog control register */ 355 #define WDT_CTL_REG 0x4 356 357 /* Watchdog control register constants */ 358 #define WDT_START_1 (0xff00) 359 #define WDT_START_2 (0x00ff) 360 #define WDT_STOP_1 (0xee00) 361 #define WDT_STOP_2 (0x00ee) 362 363 /* Watchdog reset length register */ 364 #define WDT_RSTLEN_REG 0x8 365 366 /* Watchdog soft reset register (BCM6328 only) */ 367 #define WDT_SOFTRESET_REG 0xc 368 369 /************************************************************************* 370 * _REG relative to RSET_UARTx 371 *************************************************************************/ 372 373 /* UART Control Register */ 374 #define UART_CTL_REG 0x0 375 #define UART_CTL_RXTMOUTCNT_SHIFT 0 376 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 377 #define UART_CTL_RSTTXDN_SHIFT 5 378 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 379 #define UART_CTL_RSTRXFIFO_SHIFT 6 380 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 381 #define UART_CTL_RSTTXFIFO_SHIFT 7 382 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 383 #define UART_CTL_STOPBITS_SHIFT 8 384 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 385 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 386 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 387 #define UART_CTL_BITSPERSYM_SHIFT 12 388 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 389 #define UART_CTL_XMITBRK_SHIFT 14 390 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 391 #define UART_CTL_RSVD_SHIFT 15 392 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 393 #define UART_CTL_RXPAREVEN_SHIFT 16 394 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 395 #define UART_CTL_RXPAREN_SHIFT 17 396 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 397 #define UART_CTL_TXPAREVEN_SHIFT 18 398 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 399 #define UART_CTL_TXPAREN_SHIFT 18 400 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 401 #define UART_CTL_LOOPBACK_SHIFT 20 402 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 403 #define UART_CTL_RXEN_SHIFT 21 404 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 405 #define UART_CTL_TXEN_SHIFT 22 406 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 407 #define UART_CTL_BRGEN_SHIFT 23 408 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 409 410 /* UART Baudword register */ 411 #define UART_BAUD_REG 0x4 412 413 /* UART Misc Control register */ 414 #define UART_MCTL_REG 0x8 415 #define UART_MCTL_DTR_SHIFT 0 416 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 417 #define UART_MCTL_RTS_SHIFT 1 418 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 419 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 420 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 421 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 422 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 423 #define UART_MCTL_RXFIFOFILL_SHIFT 16 424 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 425 #define UART_MCTL_TXFIFOFILL_SHIFT 24 426 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 427 428 /* UART External Input Configuration register */ 429 #define UART_EXTINP_REG 0xc 430 #define UART_EXTINP_RI_SHIFT 0 431 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 432 #define UART_EXTINP_CTS_SHIFT 1 433 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 434 #define UART_EXTINP_DCD_SHIFT 2 435 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 436 #define UART_EXTINP_DSR_SHIFT 3 437 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 438 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 439 #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 440 #define UART_EXTINP_IR_RI 0 441 #define UART_EXTINP_IR_CTS 1 442 #define UART_EXTINP_IR_DCD 2 443 #define UART_EXTINP_IR_DSR 3 444 #define UART_EXTINP_RI_NOSENSE_SHIFT 16 445 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 446 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 447 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 448 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 449 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 450 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 451 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 452 453 /* UART Interrupt register */ 454 #define UART_IR_REG 0x10 455 #define UART_IR_MASK(x) (1 << (x + 16)) 456 #define UART_IR_STAT(x) (1 << (x)) 457 #define UART_IR_EXTIP 0 458 #define UART_IR_TXUNDER 1 459 #define UART_IR_TXOVER 2 460 #define UART_IR_TXTRESH 3 461 #define UART_IR_TXRDLATCH 4 462 #define UART_IR_TXEMPTY 5 463 #define UART_IR_RXUNDER 6 464 #define UART_IR_RXOVER 7 465 #define UART_IR_RXTIMEOUT 8 466 #define UART_IR_RXFULL 9 467 #define UART_IR_RXTHRESH 10 468 #define UART_IR_RXNOTEMPTY 11 469 #define UART_IR_RXFRAMEERR 12 470 #define UART_IR_RXPARERR 13 471 #define UART_IR_RXBRK 14 472 #define UART_IR_TXDONE 15 473 474 /* UART Fifo register */ 475 #define UART_FIFO_REG 0x14 476 #define UART_FIFO_VALID_SHIFT 0 477 #define UART_FIFO_VALID_MASK 0xff 478 #define UART_FIFO_FRAMEERR_SHIFT 8 479 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 480 #define UART_FIFO_PARERR_SHIFT 9 481 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 482 #define UART_FIFO_BRKDET_SHIFT 10 483 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 484 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 485 UART_FIFO_PARERR_MASK | \ 486 UART_FIFO_BRKDET_MASK) 487 488 489 /************************************************************************* 490 * _REG relative to RSET_GPIO 491 *************************************************************************/ 492 493 /* GPIO registers */ 494 #define GPIO_CTL_HI_REG 0x0 495 #define GPIO_CTL_LO_REG 0x4 496 #define GPIO_DATA_HI_REG 0x8 497 #define GPIO_DATA_LO_REG 0xC 498 #define GPIO_DATA_LO_REG_6345 0x8 499 500 /* GPIO mux registers and constants */ 501 #define GPIO_MODE_REG 0x18 502 503 #define GPIO_MODE_6348_G4_DIAG 0x00090000 504 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000 505 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 506 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 507 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 508 #define GPIO_MODE_6348_G3_DIAG 0x00009000 509 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000 510 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000 511 #define GPIO_MODE_6348_G2_DIAG 0x00000900 512 #define GPIO_MODE_6348_G2_PCI 0x00000500 513 #define GPIO_MODE_6348_G1_DIAG 0x00000090 514 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080 515 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060 516 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 517 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 518 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 519 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 520 #define GPIO_MODE_6348_G0_DIAG 0x00000009 521 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007 522 523 #define GPIO_MODE_6358_EXTRACS (1 << 5) 524 #define GPIO_MODE_6358_UART1 (1 << 6) 525 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) 526 #define GPIO_MODE_6358_SERIAL_LED (1 << 10) 527 #define GPIO_MODE_6358_UTOPIA (1 << 12) 528 529 #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) 530 #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) 531 #define GPIO_MODE_6368_SYS_IRQ (1 << 2) 532 #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3) 533 #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4) 534 #define GPIO_MODE_6368_INET_LED (1 << 5) 535 #define GPIO_MODE_6368_EPHY0_LED (1 << 6) 536 #define GPIO_MODE_6368_EPHY1_LED (1 << 7) 537 #define GPIO_MODE_6368_EPHY2_LED (1 << 8) 538 #define GPIO_MODE_6368_EPHY3_LED (1 << 9) 539 #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10) 540 #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11) 541 #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12) 542 #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13) 543 #define GPIO_MODE_6368_USBD_LED (1 << 14) 544 #define GPIO_MODE_6368_NTR_PULSE (1 << 15) 545 #define GPIO_MODE_6368_PCI_REQ1 (1 << 16) 546 #define GPIO_MODE_6368_PCI_GNT1 (1 << 17) 547 #define GPIO_MODE_6368_PCI_INTB (1 << 18) 548 #define GPIO_MODE_6368_PCI_REQ0 (1 << 19) 549 #define GPIO_MODE_6368_PCI_GNT0 (1 << 20) 550 #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22) 551 #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23) 552 #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24) 553 #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25) 554 #define GPIO_MODE_6368_EBI_CS2 (1 << 26) 555 #define GPIO_MODE_6368_EBI_CS3 (1 << 27) 556 #define GPIO_MODE_6368_SPI_SSN2 (1 << 28) 557 #define GPIO_MODE_6368_SPI_SSN3 (1 << 29) 558 #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) 559 #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) 560 561 562 #define GPIO_PINMUX_OTHR_REG 0x24 563 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 564 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) 565 #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) 566 #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) 567 568 #define GPIO_BASEMODE_6368_REG 0x38 569 #define GPIO_BASEMODE_6368_UART2 0x1 570 #define GPIO_BASEMODE_6368_GPIO 0x0 571 #define GPIO_BASEMODE_6368_MASK 0x7 572 /* those bits must be kept as read in gpio basemode register*/ 573 574 #define GPIO_STRAPBUS_REG 0x40 575 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) 576 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) 577 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 578 #define STRAPBUS_6368_BOOT_SEL_NAND 0 579 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 580 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 581 582 583 /************************************************************************* 584 * _REG relative to RSET_ENET 585 *************************************************************************/ 586 587 /* Receiver Configuration register */ 588 #define ENET_RXCFG_REG 0x0 589 #define ENET_RXCFG_ALLMCAST_SHIFT 1 590 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) 591 #define ENET_RXCFG_PROMISC_SHIFT 3 592 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) 593 #define ENET_RXCFG_LOOPBACK_SHIFT 4 594 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) 595 #define ENET_RXCFG_ENFLOW_SHIFT 5 596 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) 597 598 /* Receive Maximum Length register */ 599 #define ENET_RXMAXLEN_REG 0x4 600 #define ENET_RXMAXLEN_SHIFT 0 601 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) 602 603 /* Transmit Maximum Length register */ 604 #define ENET_TXMAXLEN_REG 0x8 605 #define ENET_TXMAXLEN_SHIFT 0 606 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) 607 608 /* MII Status/Control register */ 609 #define ENET_MIISC_REG 0x10 610 #define ENET_MIISC_MDCFREQDIV_SHIFT 0 611 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) 612 #define ENET_MIISC_PREAMBLEEN_SHIFT 7 613 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) 614 615 /* MII Data register */ 616 #define ENET_MIIDATA_REG 0x14 617 #define ENET_MIIDATA_DATA_SHIFT 0 618 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) 619 #define ENET_MIIDATA_TA_SHIFT 16 620 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) 621 #define ENET_MIIDATA_REG_SHIFT 18 622 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) 623 #define ENET_MIIDATA_PHYID_SHIFT 23 624 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) 625 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) 626 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) 627 628 /* Ethernet Interrupt Mask register */ 629 #define ENET_IRMASK_REG 0x18 630 631 /* Ethernet Interrupt register */ 632 #define ENET_IR_REG 0x1c 633 #define ENET_IR_MII (1 << 0) 634 #define ENET_IR_MIB (1 << 1) 635 #define ENET_IR_FLOWC (1 << 2) 636 637 /* Ethernet Control register */ 638 #define ENET_CTL_REG 0x2c 639 #define ENET_CTL_ENABLE_SHIFT 0 640 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) 641 #define ENET_CTL_DISABLE_SHIFT 1 642 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) 643 #define ENET_CTL_SRESET_SHIFT 2 644 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) 645 #define ENET_CTL_EPHYSEL_SHIFT 3 646 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) 647 648 /* Transmit Control register */ 649 #define ENET_TXCTL_REG 0x30 650 #define ENET_TXCTL_FD_SHIFT 0 651 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) 652 653 /* Transmit Watermask register */ 654 #define ENET_TXWMARK_REG 0x34 655 #define ENET_TXWMARK_WM_SHIFT 0 656 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) 657 658 /* MIB Control register */ 659 #define ENET_MIBCTL_REG 0x38 660 #define ENET_MIBCTL_RDCLEAR_SHIFT 0 661 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) 662 663 /* Perfect Match Data Low register */ 664 #define ENET_PML_REG(x) (0x58 + (x) * 8) 665 #define ENET_PMH_REG(x) (0x5c + (x) * 8) 666 #define ENET_PMH_DATAVALID_SHIFT 16 667 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) 668 669 /* MIB register */ 670 #define ENET_MIB_REG(x) (0x200 + (x) * 4) 671 #define ENET_MIB_REG_COUNT 55 672 673 674 /************************************************************************* 675 * _REG relative to RSET_ENETDMA 676 *************************************************************************/ 677 678 /* Controller Configuration Register */ 679 #define ENETDMA_CFG_REG (0x0) 680 #define ENETDMA_CFG_EN_SHIFT 0 681 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) 682 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) 683 684 /* Flow Control Descriptor Low Threshold register */ 685 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) 686 687 /* Flow Control Descriptor High Threshold register */ 688 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) 689 690 /* Flow Control Descriptor Buffer Alloca Threshold register */ 691 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) 692 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 693 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) 694 695 /* Global interrupt status */ 696 #define ENETDMA_GLB_IRQSTAT_REG (0x40) 697 698 /* Global interrupt mask */ 699 #define ENETDMA_GLB_IRQMASK_REG (0x44) 700 701 /* Channel Configuration register */ 702 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) 703 #define ENETDMA_CHANCFG_EN_SHIFT 0 704 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) 705 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 706 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) 707 708 /* Interrupt Control/Status register */ 709 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) 710 #define ENETDMA_IR_BUFDONE_MASK (1 << 0) 711 #define ENETDMA_IR_PKTDONE_MASK (1 << 1) 712 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2) 713 714 /* Interrupt Mask register */ 715 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) 716 717 /* Maximum Burst Length */ 718 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) 719 720 /* Ring Start Address register */ 721 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) 722 723 /* State Ram Word 2 */ 724 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) 725 726 /* State Ram Word 3 */ 727 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) 728 729 /* State Ram Word 4 */ 730 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) 731 732 733 /************************************************************************* 734 * _REG relative to RSET_ENETDMAC 735 *************************************************************************/ 736 737 /* Channel Configuration register */ 738 #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) 739 #define ENETDMAC_CHANCFG_EN_SHIFT 0 740 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) 741 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 742 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) 743 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 744 #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) 745 746 /* Interrupt Control/Status register */ 747 #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) 748 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) 749 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) 750 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) 751 752 /* Interrupt Mask register */ 753 #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) 754 755 /* Maximum Burst Length */ 756 #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) 757 758 759 /************************************************************************* 760 * _REG relative to RSET_ENETDMAS 761 *************************************************************************/ 762 763 /* Ring Start Address register */ 764 #define ENETDMAS_RSTART_REG(x) ((x) * 0x10) 765 766 /* State Ram Word 2 */ 767 #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) 768 769 /* State Ram Word 3 */ 770 #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) 771 772 /* State Ram Word 4 */ 773 #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) 774 775 776 /************************************************************************* 777 * _REG relative to RSET_ENETSW 778 *************************************************************************/ 779 780 /* MIB register */ 781 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) 782 #define ENETSW_MIB_REG_COUNT 47 783 784 785 /************************************************************************* 786 * _REG relative to RSET_OHCI_PRIV 787 *************************************************************************/ 788 789 #define OHCI_PRIV_REG 0x0 790 #define OHCI_PRIV_PORT1_HOST_SHIFT 0 791 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) 792 #define OHCI_PRIV_REG_SWAP_SHIFT 3 793 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) 794 795 796 /************************************************************************* 797 * _REG relative to RSET_USBH_PRIV 798 *************************************************************************/ 799 800 #define USBH_PRIV_SWAP_6358_REG 0x0 801 #define USBH_PRIV_SWAP_6368_REG 0x1c 802 803 #define USBH_PRIV_SWAP_USBD_SHIFT 6 804 #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) 805 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 806 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 807 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 808 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) 809 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 810 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) 811 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 812 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 813 814 #define USBH_PRIV_UTMI_CTL_6368_REG 0x10 815 #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 816 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) 817 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 818 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) 819 820 #define USBH_PRIV_TEST_6358_REG 0x24 821 #define USBH_PRIV_TEST_6368_REG 0x14 822 823 #define USBH_PRIV_SETUP_6368_REG 0x28 824 #define USBH_PRIV_SETUP_IOC_SHIFT 4 825 #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) 826 827 828 /************************************************************************* 829 * _REG relative to RSET_USBD 830 *************************************************************************/ 831 832 /* General control */ 833 #define USBD_CONTROL_REG 0x00 834 #define USBD_CONTROL_TXZLENINS_SHIFT 14 835 #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) 836 #define USBD_CONTROL_AUTO_CSRS_SHIFT 13 837 #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) 838 #define USBD_CONTROL_RXZSCFG_SHIFT 12 839 #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) 840 #define USBD_CONTROL_INIT_SEL_SHIFT 8 841 #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) 842 #define USBD_CONTROL_FIFO_RESET_SHIFT 6 843 #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) 844 #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 845 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) 846 #define USBD_CONTROL_DONE_CSRS_SHIFT 0 847 #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) 848 849 /* Strap options */ 850 #define USBD_STRAPS_REG 0x04 851 #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 852 #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) 853 #define USBD_STRAPS_APP_DISCON_SHIFT 9 854 #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) 855 #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 856 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) 857 #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 858 #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) 859 #define USBD_STRAPS_APP_RAM_IF_SHIFT 7 860 #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) 861 #define USBD_STRAPS_APP_8BITPHY_SHIFT 2 862 #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) 863 #define USBD_STRAPS_SPEED_SHIFT 0 864 #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) 865 866 /* Stall control */ 867 #define USBD_STALL_REG 0x08 868 #define USBD_STALL_UPDATE_SHIFT 7 869 #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) 870 #define USBD_STALL_ENABLE_SHIFT 6 871 #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) 872 #define USBD_STALL_EPNUM_SHIFT 0 873 #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) 874 875 /* General status */ 876 #define USBD_STATUS_REG 0x0c 877 #define USBD_STATUS_SOF_SHIFT 16 878 #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) 879 #define USBD_STATUS_SPD_SHIFT 12 880 #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) 881 #define USBD_STATUS_ALTINTF_SHIFT 8 882 #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) 883 #define USBD_STATUS_INTF_SHIFT 4 884 #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) 885 #define USBD_STATUS_CFG_SHIFT 0 886 #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) 887 888 /* Other events */ 889 #define USBD_EVENTS_REG 0x10 890 #define USBD_EVENTS_USB_LINK_SHIFT 10 891 #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) 892 893 /* IRQ status */ 894 #define USBD_EVENT_IRQ_STATUS_REG 0x14 895 896 /* IRQ level (2 bits per IRQ event) */ 897 #define USBD_EVENT_IRQ_CFG_HI_REG 0x18 898 899 #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c 900 901 #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) 902 #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) 903 #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) 904 #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) 905 906 /* IRQ mask (1=unmasked) */ 907 #define USBD_EVENT_IRQ_MASK_REG 0x20 908 909 /* IRQ bits */ 910 #define USBD_EVENT_IRQ_USB_LINK 10 911 #define USBD_EVENT_IRQ_SETCFG 9 912 #define USBD_EVENT_IRQ_SETINTF 8 913 #define USBD_EVENT_IRQ_ERRATIC_ERR 7 914 #define USBD_EVENT_IRQ_SET_CSRS 6 915 #define USBD_EVENT_IRQ_SUSPEND 5 916 #define USBD_EVENT_IRQ_EARLY_SUSPEND 4 917 #define USBD_EVENT_IRQ_SOF 3 918 #define USBD_EVENT_IRQ_ENUM_ON 2 919 #define USBD_EVENT_IRQ_SETUP 1 920 #define USBD_EVENT_IRQ_USB_RESET 0 921 922 /* TX FIFO partitioning */ 923 #define USBD_TXFIFO_CONFIG_REG 0x40 924 #define USBD_TXFIFO_CONFIG_END_SHIFT 16 925 #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) 926 #define USBD_TXFIFO_CONFIG_START_SHIFT 0 927 #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) 928 929 /* RX FIFO partitioning */ 930 #define USBD_RXFIFO_CONFIG_REG 0x44 931 #define USBD_RXFIFO_CONFIG_END_SHIFT 16 932 #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) 933 #define USBD_RXFIFO_CONFIG_START_SHIFT 0 934 #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) 935 936 /* TX FIFO/endpoint configuration */ 937 #define USBD_TXFIFO_EPSIZE_REG 0x48 938 939 /* RX FIFO/endpoint configuration */ 940 #define USBD_RXFIFO_EPSIZE_REG 0x4c 941 942 /* Endpoint<->DMA mappings */ 943 #define USBD_EPNUM_TYPEMAP_REG 0x50 944 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 945 #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) 946 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 947 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) 948 949 /* Misc per-endpoint settings */ 950 #define USBD_CSR_SETUPADDR_REG 0x80 951 #define USBD_CSR_SETUPADDR_DEF 0xb550 952 953 #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) 954 #define USBD_CSR_EP_MAXPKT_SHIFT 19 955 #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) 956 #define USBD_CSR_EP_ALTIFACE_SHIFT 15 957 #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) 958 #define USBD_CSR_EP_IFACE_SHIFT 11 959 #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) 960 #define USBD_CSR_EP_CFG_SHIFT 7 961 #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) 962 #define USBD_CSR_EP_TYPE_SHIFT 5 963 #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) 964 #define USBD_CSR_EP_DIR_SHIFT 4 965 #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) 966 #define USBD_CSR_EP_LOG_SHIFT 0 967 #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) 968 969 970 /************************************************************************* 971 * _REG relative to RSET_MPI 972 *************************************************************************/ 973 974 /* well known (hard wired) chip select */ 975 #define MPI_CS_PCMCIA_COMMON 4 976 #define MPI_CS_PCMCIA_ATTR 5 977 #define MPI_CS_PCMCIA_IO 6 978 979 /* Chip select base register */ 980 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8) 981 #define MPI_CSBASE_BASE_SHIFT 13 982 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) 983 #define MPI_CSBASE_SIZE_SHIFT 0 984 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) 985 986 #define MPI_CSBASE_SIZE_8K 0 987 #define MPI_CSBASE_SIZE_16K 1 988 #define MPI_CSBASE_SIZE_32K 2 989 #define MPI_CSBASE_SIZE_64K 3 990 #define MPI_CSBASE_SIZE_128K 4 991 #define MPI_CSBASE_SIZE_256K 5 992 #define MPI_CSBASE_SIZE_512K 6 993 #define MPI_CSBASE_SIZE_1M 7 994 #define MPI_CSBASE_SIZE_2M 8 995 #define MPI_CSBASE_SIZE_4M 9 996 #define MPI_CSBASE_SIZE_8M 10 997 #define MPI_CSBASE_SIZE_16M 11 998 #define MPI_CSBASE_SIZE_32M 12 999 #define MPI_CSBASE_SIZE_64M 13 1000 #define MPI_CSBASE_SIZE_128M 14 1001 #define MPI_CSBASE_SIZE_256M 15 1002 1003 /* Chip select control register */ 1004 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8) 1005 #define MPI_CSCTL_ENABLE_MASK (1 << 0) 1006 #define MPI_CSCTL_WAIT_SHIFT 1 1007 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) 1008 #define MPI_CSCTL_DATA16_MASK (1 << 4) 1009 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7) 1010 #define MPI_CSCTL_TSIZE_MASK (1 << 8) 1011 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) 1012 #define MPI_CSCTL_SETUP_SHIFT 16 1013 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) 1014 #define MPI_CSCTL_HOLD_SHIFT 20 1015 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) 1016 1017 /* PCI registers */ 1018 #define MPI_SP0_RANGE_REG 0x100 1019 #define MPI_SP0_REMAP_REG 0x104 1020 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) 1021 #define MPI_SP1_RANGE_REG 0x10C 1022 #define MPI_SP1_REMAP_REG 0x110 1023 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) 1024 1025 #define MPI_L2PCFG_REG 0x11C 1026 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0 1027 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) 1028 #define MPI_L2PCFG_REG_SHIFT 2 1029 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) 1030 #define MPI_L2PCFG_FUNC_SHIFT 8 1031 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) 1032 #define MPI_L2PCFG_DEVNUM_SHIFT 11 1033 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) 1034 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) 1035 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) 1036 1037 #define MPI_L2PMEMRANGE1_REG 0x120 1038 #define MPI_L2PMEMBASE1_REG 0x124 1039 #define MPI_L2PMEMREMAP1_REG 0x128 1040 #define MPI_L2PMEMRANGE2_REG 0x12C 1041 #define MPI_L2PMEMBASE2_REG 0x130 1042 #define MPI_L2PMEMREMAP2_REG 0x134 1043 #define MPI_L2PIORANGE_REG 0x138 1044 #define MPI_L2PIOBASE_REG 0x13C 1045 #define MPI_L2PIOREMAP_REG 0x140 1046 #define MPI_L2P_BASE_MASK (0xffff8000) 1047 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0) 1048 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) 1049 1050 #define MPI_PCIMODESEL_REG 0x144 1051 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) 1052 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) 1053 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) 1054 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 1055 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) 1056 1057 #define MPI_LOCBUSCTL_REG 0x14C 1058 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) 1059 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) 1060 1061 #define MPI_LOCINT_REG 0x150 1062 #define MPI_LOCINT_MASK(x) (1 << (x + 16)) 1063 #define MPI_LOCINT_STAT(x) (1 << (x)) 1064 #define MPI_LOCINT_DIR_FAILED 6 1065 #define MPI_LOCINT_EXT_PCI_INT 7 1066 #define MPI_LOCINT_SERR 8 1067 #define MPI_LOCINT_CSERR 9 1068 1069 #define MPI_PCICFGCTL_REG 0x178 1070 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2 1071 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) 1072 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) 1073 1074 #define MPI_PCICFGDATA_REG 0x17C 1075 1076 /* PCI host bridge custom register */ 1077 #define BCMPCI_REG_TIMERS 0x40 1078 #define REG_TIMER_TRDY_SHIFT 0 1079 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) 1080 #define REG_TIMER_RETRY_SHIFT 8 1081 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) 1082 1083 1084 /************************************************************************* 1085 * _REG relative to RSET_PCMCIA 1086 *************************************************************************/ 1087 1088 #define PCMCIA_C1_REG 0x0 1089 #define PCMCIA_C1_CD1_MASK (1 << 0) 1090 #define PCMCIA_C1_CD2_MASK (1 << 1) 1091 #define PCMCIA_C1_VS1_MASK (1 << 2) 1092 #define PCMCIA_C1_VS2_MASK (1 << 3) 1093 #define PCMCIA_C1_VS1OE_MASK (1 << 6) 1094 #define PCMCIA_C1_VS2OE_MASK (1 << 7) 1095 #define PCMCIA_C1_CBIDSEL_SHIFT (8) 1096 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) 1097 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) 1098 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) 1099 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) 1100 #define PCMCIA_C1_RESET_MASK (1 << 18) 1101 1102 #define PCMCIA_C2_REG 0x8 1103 #define PCMCIA_C2_DATA16_MASK (1 << 0) 1104 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1) 1105 #define PCMCIA_C2_RWCOUNT_SHIFT 2 1106 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) 1107 #define PCMCIA_C2_INACTIVE_SHIFT 8 1108 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) 1109 #define PCMCIA_C2_SETUP_SHIFT 16 1110 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) 1111 #define PCMCIA_C2_HOLD_SHIFT 24 1112 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) 1113 1114 1115 /************************************************************************* 1116 * _REG relative to RSET_SDRAM 1117 *************************************************************************/ 1118 1119 #define SDRAM_CFG_REG 0x0 1120 #define SDRAM_CFG_ROW_SHIFT 4 1121 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) 1122 #define SDRAM_CFG_COL_SHIFT 6 1123 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) 1124 #define SDRAM_CFG_32B_SHIFT 10 1125 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) 1126 #define SDRAM_CFG_BANK_SHIFT 13 1127 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 1128 1129 #define SDRAM_MBASE_REG 0xc 1130 1131 #define SDRAM_PRIO_REG 0x2C 1132 #define SDRAM_PRIO_MIPS_SHIFT 29 1133 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 1134 #define SDRAM_PRIO_ADSL_SHIFT 30 1135 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) 1136 #define SDRAM_PRIO_EN_SHIFT 31 1137 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) 1138 1139 1140 /************************************************************************* 1141 * _REG relative to RSET_MEMC 1142 *************************************************************************/ 1143 1144 #define MEMC_CFG_REG 0x4 1145 #define MEMC_CFG_32B_SHIFT 1 1146 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) 1147 #define MEMC_CFG_COL_SHIFT 3 1148 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) 1149 #define MEMC_CFG_ROW_SHIFT 6 1150 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) 1151 1152 1153 /************************************************************************* 1154 * _REG relative to RSET_DDR 1155 *************************************************************************/ 1156 1157 #define DDR_CSEND_REG 0x8 1158 1159 #define DDR_DMIPSPLLCFG_REG 0x18 1160 #define DMIPSPLLCFG_M1_SHIFT 0 1161 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 1162 #define DMIPSPLLCFG_N1_SHIFT 23 1163 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) 1164 #define DMIPSPLLCFG_N2_SHIFT 29 1165 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 1166 1167 #define DDR_DMIPSPLLCFG_6368_REG 0x20 1168 #define DMIPSPLLCFG_6368_P1_SHIFT 0 1169 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) 1170 #define DMIPSPLLCFG_6368_P2_SHIFT 4 1171 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) 1172 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 1173 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) 1174 1175 #define DDR_DMIPSPLLDIV_6368_REG 0x24 1176 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 1177 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) 1178 1179 1180 /************************************************************************* 1181 * _REG relative to RSET_M2M 1182 *************************************************************************/ 1183 1184 #define M2M_RX 0 1185 #define M2M_TX 1 1186 1187 #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) 1188 #define M2M_DST_REG(x) ((x) * 0x40 + 0x04) 1189 #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) 1190 1191 #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) 1192 #define M2M_CTRL_ENABLE_MASK (1 << 0) 1193 #define M2M_CTRL_IRQEN_MASK (1 << 1) 1194 #define M2M_CTRL_ERROR_CLR_MASK (1 << 6) 1195 #define M2M_CTRL_DONE_CLR_MASK (1 << 7) 1196 #define M2M_CTRL_NOINC_MASK (1 << 8) 1197 #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) 1198 #define M2M_CTRL_SWAPBYTE_MASK (1 << 10) 1199 #define M2M_CTRL_ENDIAN_MASK (1 << 11) 1200 1201 #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) 1202 #define M2M_STAT_DONE (1 << 0) 1203 #define M2M_STAT_ERROR (1 << 1) 1204 1205 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) 1206 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) 1207 1208 /************************************************************************* 1209 * _REG relative to RSET_RNG 1210 *************************************************************************/ 1211 1212 #define RNG_CTRL 0x00 1213 #define RNG_EN (1 << 0) 1214 1215 #define RNG_STAT 0x04 1216 #define RNG_AVAIL_MASK (0xff000000) 1217 1218 #define RNG_DATA 0x08 1219 #define RNG_THRES 0x0c 1220 #define RNG_MASK 0x10 1221 1222 /************************************************************************* 1223 * _REG relative to RSET_SPI 1224 *************************************************************************/ 1225 1226 /* BCM 6338 SPI core */ 1227 #define SPI_6338_CMD 0x00 /* 16-bits register */ 1228 #define SPI_6338_INT_STATUS 0x02 1229 #define SPI_6338_INT_MASK_ST 0x03 1230 #define SPI_6338_INT_MASK 0x04 1231 #define SPI_6338_ST 0x05 1232 #define SPI_6338_CLK_CFG 0x06 1233 #define SPI_6338_FILL_BYTE 0x07 1234 #define SPI_6338_MSG_TAIL 0x09 1235 #define SPI_6338_RX_TAIL 0x0b 1236 #define SPI_6338_MSG_CTL 0x40 /* 8-bits register */ 1237 #define SPI_6338_MSG_CTL_WIDTH 8 1238 #define SPI_6338_MSG_DATA 0x41 1239 #define SPI_6338_MSG_DATA_SIZE 0x3f 1240 #define SPI_6338_RX_DATA 0x80 1241 #define SPI_6338_RX_DATA_SIZE 0x3f 1242 1243 /* BCM 6348 SPI core */ 1244 #define SPI_6348_CMD 0x00 /* 16-bits register */ 1245 #define SPI_6348_INT_STATUS 0x02 1246 #define SPI_6348_INT_MASK_ST 0x03 1247 #define SPI_6348_INT_MASK 0x04 1248 #define SPI_6348_ST 0x05 1249 #define SPI_6348_CLK_CFG 0x06 1250 #define SPI_6348_FILL_BYTE 0x07 1251 #define SPI_6348_MSG_TAIL 0x09 1252 #define SPI_6348_RX_TAIL 0x0b 1253 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ 1254 #define SPI_6348_MSG_CTL_WIDTH 8 1255 #define SPI_6348_MSG_DATA 0x41 1256 #define SPI_6348_MSG_DATA_SIZE 0x3f 1257 #define SPI_6348_RX_DATA 0x80 1258 #define SPI_6348_RX_DATA_SIZE 0x3f 1259 1260 /* BCM 6358 SPI core */ 1261 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 1262 #define SPI_6358_MSG_CTL_WIDTH 16 1263 #define SPI_6358_MSG_DATA 0x02 1264 #define SPI_6358_MSG_DATA_SIZE 0x21e 1265 #define SPI_6358_RX_DATA 0x400 1266 #define SPI_6358_RX_DATA_SIZE 0x220 1267 #define SPI_6358_CMD 0x700 /* 16-bits register */ 1268 #define SPI_6358_INT_STATUS 0x702 1269 #define SPI_6358_INT_MASK_ST 0x703 1270 #define SPI_6358_INT_MASK 0x704 1271 #define SPI_6358_ST 0x705 1272 #define SPI_6358_CLK_CFG 0x706 1273 #define SPI_6358_FILL_BYTE 0x707 1274 #define SPI_6358_MSG_TAIL 0x709 1275 #define SPI_6358_RX_TAIL 0x70B 1276 1277 /* BCM 6358 SPI core */ 1278 #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ 1279 #define SPI_6368_MSG_CTL_WIDTH 16 1280 #define SPI_6368_MSG_DATA 0x02 1281 #define SPI_6368_MSG_DATA_SIZE 0x21e 1282 #define SPI_6368_RX_DATA 0x400 1283 #define SPI_6368_RX_DATA_SIZE 0x220 1284 #define SPI_6368_CMD 0x700 /* 16-bits register */ 1285 #define SPI_6368_INT_STATUS 0x702 1286 #define SPI_6368_INT_MASK_ST 0x703 1287 #define SPI_6368_INT_MASK 0x704 1288 #define SPI_6368_ST 0x705 1289 #define SPI_6368_CLK_CFG 0x706 1290 #define SPI_6368_FILL_BYTE 0x707 1291 #define SPI_6368_MSG_TAIL 0x709 1292 #define SPI_6368_RX_TAIL 0x70B 1293 1294 /* Shared SPI definitions */ 1295 1296 /* Message configuration */ 1297 #define SPI_FD_RW 0x00 1298 #define SPI_HD_W 0x01 1299 #define SPI_HD_R 0x02 1300 #define SPI_BYTE_CNT_SHIFT 0 1301 #define SPI_6338_MSG_TYPE_SHIFT 6 1302 #define SPI_6348_MSG_TYPE_SHIFT 6 1303 #define SPI_6358_MSG_TYPE_SHIFT 14 1304 #define SPI_6368_MSG_TYPE_SHIFT 14 1305 1306 /* Command */ 1307 #define SPI_CMD_NOOP 0x00 1308 #define SPI_CMD_SOFT_RESET 0x01 1309 #define SPI_CMD_HARD_RESET 0x02 1310 #define SPI_CMD_START_IMMEDIATE 0x03 1311 #define SPI_CMD_COMMAND_SHIFT 0 1312 #define SPI_CMD_COMMAND_MASK 0x000f 1313 #define SPI_CMD_DEVICE_ID_SHIFT 4 1314 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 1315 #define SPI_CMD_ONE_BYTE_SHIFT 11 1316 #define SPI_CMD_ONE_WIRE_SHIFT 12 1317 #define SPI_DEV_ID_0 0 1318 #define SPI_DEV_ID_1 1 1319 #define SPI_DEV_ID_2 2 1320 #define SPI_DEV_ID_3 3 1321 1322 /* Interrupt mask */ 1323 #define SPI_INTR_CMD_DONE 0x01 1324 #define SPI_INTR_RX_OVERFLOW 0x02 1325 #define SPI_INTR_TX_UNDERFLOW 0x04 1326 #define SPI_INTR_TX_OVERFLOW 0x08 1327 #define SPI_INTR_RX_UNDERFLOW 0x10 1328 #define SPI_INTR_CLEAR_ALL 0x1f 1329 1330 /* Status */ 1331 #define SPI_RX_EMPTY 0x02 1332 #define SPI_CMD_BUSY 0x04 1333 #define SPI_SERIAL_BUSY 0x08 1334 1335 /* Clock configuration */ 1336 #define SPI_CLK_20MHZ 0x00 1337 #define SPI_CLK_0_391MHZ 0x01 1338 #define SPI_CLK_0_781MHZ 0x02 /* default */ 1339 #define SPI_CLK_1_563MHZ 0x03 1340 #define SPI_CLK_3_125MHZ 0x04 1341 #define SPI_CLK_6_250MHZ 0x05 1342 #define SPI_CLK_12_50MHZ 0x06 1343 #define SPI_CLK_MASK 0x07 1344 #define SPI_SSOFFTIME_MASK 0x38 1345 #define SPI_SSOFFTIME_SHIFT 3 1346 #define SPI_BYTE_SWAP 0x80 1347 1348 /************************************************************************* 1349 * _REG relative to RSET_MISC 1350 *************************************************************************/ 1351 #define MISC_SERDES_CTRL_REG 0x0 1352 #define SERDES_PCIE_EN (1 << 0) 1353 #define SERDES_PCIE_EXD_EN (1 << 15) 1354 1355 #define MISC_STRAPBUS_6328_REG 0x240 1356 #define STRAPBUS_6328_FCVO_SHIFT 7 1357 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 1358 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) 1359 #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) 1360 1361 /************************************************************************* 1362 * _REG relative to RSET_PCIE 1363 *************************************************************************/ 1364 1365 #define PCIE_CONFIG2_REG 0x408 1366 #define CONFIG2_BAR1_SIZE_EN 1 1367 #define CONFIG2_BAR1_SIZE_MASK 0xf 1368 1369 #define PCIE_IDVAL3_REG 0x43c 1370 #define IDVAL3_CLASS_CODE_MASK 0xffffff 1371 #define IDVAL3_SUBCLASS_SHIFT 8 1372 #define IDVAL3_CLASS_SHIFT 16 1373 1374 #define PCIE_DLSTATUS_REG 0x1048 1375 #define DLSTATUS_PHYLINKUP (1 << 13) 1376 1377 #define PCIE_BRIDGE_OPT1_REG 0x2820 1378 #define OPT1_RD_BE_OPT_EN (1 << 7) 1379 #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9) 1380 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11) 1381 #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12) 1382 1383 #define PCIE_BRIDGE_OPT2_REG 0x2824 1384 #define OPT2_UBUS_UR_DECODE_DIS (1 << 2) 1385 #define OPT2_TX_CREDIT_CHK_EN (1 << 4) 1386 #define OPT2_CFG_TYPE1_BD_SEL (1 << 7) 1387 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16 1388 #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT) 1389 1390 #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828 1391 #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830 1392 #define BASEMASK_REMAP_EN (1 << 0) 1393 #define BASEMASK_SWAP_EN (1 << 1) 1394 #define BASEMASK_MASK_SHIFT 4 1395 #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT) 1396 #define BASEMASK_BASE_SHIFT 20 1397 #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT) 1398 1399 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c 1400 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834 1401 #define REBASE_ADDR_BASE_SHIFT 20 1402 #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT) 1403 1404 #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854 1405 #define PCIE_RC_INT_A (1 << 0) 1406 #define PCIE_RC_INT_B (1 << 1) 1407 #define PCIE_RC_INT_C (1 << 2) 1408 #define PCIE_RC_INT_D (1 << 3) 1409 1410 #define PCIE_DEVICE_OFFSET 0x8000 1411 1412 #endif /* BCM63XX_REGS_H_ */ 1413