1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef BCM63XX_REGS_H_
3 #define BCM63XX_REGS_H_
4 
5 /*************************************************************************
6  * _REG relative to RSET_PERF
7  *************************************************************************/
8 
9 /* Chip Identifier / Revision register */
10 #define PERF_REV_REG			0x0
11 #define REV_CHIPID_SHIFT		16
12 #define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
13 #define REV_REVID_SHIFT			0
14 #define REV_REVID_MASK			(0xff << REV_REVID_SHIFT)
15 
16 /* Clock Control register */
17 #define PERF_CKCTL_REG			0x4
18 
19 #define CKCTL_3368_MAC_EN		(1 << 3)
20 #define CKCTL_3368_TC_EN		(1 << 5)
21 #define CKCTL_3368_US_TOP_EN		(1 << 6)
22 #define CKCTL_3368_DS_TOP_EN		(1 << 7)
23 #define CKCTL_3368_APM_EN		(1 << 8)
24 #define CKCTL_3368_SPI_EN		(1 << 9)
25 #define CKCTL_3368_USBS_EN		(1 << 10)
26 #define CKCTL_3368_BMU_EN		(1 << 11)
27 #define CKCTL_3368_PCM_EN		(1 << 12)
28 #define CKCTL_3368_NTP_EN		(1 << 13)
29 #define CKCTL_3368_ACP_B_EN		(1 << 14)
30 #define CKCTL_3368_ACP_A_EN		(1 << 15)
31 #define CKCTL_3368_EMUSB_EN		(1 << 17)
32 #define CKCTL_3368_ENET0_EN		(1 << 18)
33 #define CKCTL_3368_ENET1_EN		(1 << 19)
34 #define CKCTL_3368_USBU_EN		(1 << 20)
35 #define CKCTL_3368_EPHY_EN		(1 << 21)
36 
37 #define CKCTL_3368_ALL_SAFE_EN		(CKCTL_3368_MAC_EN | \
38 					 CKCTL_3368_TC_EN | \
39 					 CKCTL_3368_US_TOP_EN | \
40 					 CKCTL_3368_DS_TOP_EN | \
41 					 CKCTL_3368_APM_EN | \
42 					 CKCTL_3368_SPI_EN | \
43 					 CKCTL_3368_USBS_EN | \
44 					 CKCTL_3368_BMU_EN | \
45 					 CKCTL_3368_PCM_EN | \
46 					 CKCTL_3368_NTP_EN | \
47 					 CKCTL_3368_ACP_B_EN | \
48 					 CKCTL_3368_ACP_A_EN | \
49 					 CKCTL_3368_EMUSB_EN | \
50 					 CKCTL_3368_USBU_EN)
51 
52 #define CKCTL_6328_PHYMIPS_EN		(1 << 0)
53 #define CKCTL_6328_ADSL_QPROC_EN	(1 << 1)
54 #define CKCTL_6328_ADSL_AFE_EN		(1 << 2)
55 #define CKCTL_6328_ADSL_EN		(1 << 3)
56 #define CKCTL_6328_MIPS_EN		(1 << 4)
57 #define CKCTL_6328_SAR_EN		(1 << 5)
58 #define CKCTL_6328_PCM_EN		(1 << 6)
59 #define CKCTL_6328_USBD_EN		(1 << 7)
60 #define CKCTL_6328_USBH_EN		(1 << 8)
61 #define CKCTL_6328_HSSPI_EN		(1 << 9)
62 #define CKCTL_6328_PCIE_EN		(1 << 10)
63 #define CKCTL_6328_ROBOSW_EN		(1 << 11)
64 
65 #define CKCTL_6328_ALL_SAFE_EN		(CKCTL_6328_PHYMIPS_EN |	\
66 					CKCTL_6328_ADSL_QPROC_EN |	\
67 					CKCTL_6328_ADSL_AFE_EN |	\
68 					CKCTL_6328_ADSL_EN |		\
69 					CKCTL_6328_SAR_EN  |		\
70 					CKCTL_6328_PCM_EN  |		\
71 					CKCTL_6328_USBD_EN |		\
72 					CKCTL_6328_USBH_EN |		\
73 					CKCTL_6328_ROBOSW_EN |		\
74 					CKCTL_6328_PCIE_EN)
75 
76 #define CKCTL_6338_ADSLPHY_EN		(1 << 0)
77 #define CKCTL_6338_MPI_EN		(1 << 1)
78 #define CKCTL_6338_DRAM_EN		(1 << 2)
79 #define CKCTL_6338_ENET_EN		(1 << 4)
80 #define CKCTL_6338_USBS_EN		(1 << 4)
81 #define CKCTL_6338_SAR_EN		(1 << 5)
82 #define CKCTL_6338_SPI_EN		(1 << 9)
83 
84 #define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ADSLPHY_EN |	\
85 					CKCTL_6338_MPI_EN |		\
86 					CKCTL_6338_ENET_EN |		\
87 					CKCTL_6338_SAR_EN |		\
88 					CKCTL_6338_SPI_EN)
89 
90 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
91  * control register which is 16-bits wide. That way we do not have any
92  * specific BCM6345 code for handling clocks, and writing 0 to the test
93  * control register is fine.
94  */
95 #define CKCTL_6345_CPU_EN		(1 << 16)
96 #define CKCTL_6345_BUS_EN		(1 << 17)
97 #define CKCTL_6345_EBI_EN		(1 << 18)
98 #define CKCTL_6345_UART_EN		(1 << 19)
99 #define CKCTL_6345_ADSLPHY_EN		(1 << 20)
100 #define CKCTL_6345_ENET_EN		(1 << 23)
101 #define CKCTL_6345_USBH_EN		(1 << 24)
102 
103 #define CKCTL_6345_ALL_SAFE_EN		(CKCTL_6345_ENET_EN |	\
104 					CKCTL_6345_USBH_EN |	\
105 					CKCTL_6345_ADSLPHY_EN)
106 
107 #define CKCTL_6348_ADSLPHY_EN		(1 << 0)
108 #define CKCTL_6348_MPI_EN		(1 << 1)
109 #define CKCTL_6348_SDRAM_EN		(1 << 2)
110 #define CKCTL_6348_M2M_EN		(1 << 3)
111 #define CKCTL_6348_ENET_EN		(1 << 4)
112 #define CKCTL_6348_SAR_EN		(1 << 5)
113 #define CKCTL_6348_USBS_EN		(1 << 6)
114 #define CKCTL_6348_USBH_EN		(1 << 8)
115 #define CKCTL_6348_SPI_EN		(1 << 9)
116 
117 #define CKCTL_6348_ALL_SAFE_EN		(CKCTL_6348_ADSLPHY_EN |	\
118 					CKCTL_6348_M2M_EN |		\
119 					CKCTL_6348_ENET_EN |		\
120 					CKCTL_6348_SAR_EN |		\
121 					CKCTL_6348_USBS_EN |		\
122 					CKCTL_6348_USBH_EN |		\
123 					CKCTL_6348_SPI_EN)
124 
125 #define CKCTL_6358_ENET_EN		(1 << 4)
126 #define CKCTL_6358_ADSLPHY_EN		(1 << 5)
127 #define CKCTL_6358_PCM_EN		(1 << 8)
128 #define CKCTL_6358_SPI_EN		(1 << 9)
129 #define CKCTL_6358_USBS_EN		(1 << 10)
130 #define CKCTL_6358_SAR_EN		(1 << 11)
131 #define CKCTL_6358_EMUSB_EN		(1 << 17)
132 #define CKCTL_6358_ENET0_EN		(1 << 18)
133 #define CKCTL_6358_ENET1_EN		(1 << 19)
134 #define CKCTL_6358_USBSU_EN		(1 << 20)
135 #define CKCTL_6358_EPHY_EN		(1 << 21)
136 
137 #define CKCTL_6358_ALL_SAFE_EN		(CKCTL_6358_ENET_EN |		\
138 					CKCTL_6358_ADSLPHY_EN |		\
139 					CKCTL_6358_PCM_EN |		\
140 					CKCTL_6358_SPI_EN |		\
141 					CKCTL_6358_USBS_EN |		\
142 					CKCTL_6358_SAR_EN |		\
143 					CKCTL_6358_EMUSB_EN |		\
144 					CKCTL_6358_ENET0_EN |		\
145 					CKCTL_6358_ENET1_EN |		\
146 					CKCTL_6358_USBSU_EN |		\
147 					CKCTL_6358_EPHY_EN)
148 
149 #define CKCTL_6362_ADSL_QPROC_EN	(1 << 1)
150 #define CKCTL_6362_ADSL_AFE_EN		(1 << 2)
151 #define CKCTL_6362_ADSL_EN		(1 << 3)
152 #define CKCTL_6362_MIPS_EN		(1 << 4)
153 #define CKCTL_6362_WLAN_OCP_EN		(1 << 5)
154 #define CKCTL_6362_SWPKT_USB_EN		(1 << 7)
155 #define CKCTL_6362_SWPKT_SAR_EN		(1 << 8)
156 #define CKCTL_6362_SAR_EN		(1 << 9)
157 #define CKCTL_6362_ROBOSW_EN		(1 << 10)
158 #define CKCTL_6362_PCM_EN		(1 << 11)
159 #define CKCTL_6362_USBD_EN		(1 << 12)
160 #define CKCTL_6362_USBH_EN		(1 << 13)
161 #define CKCTL_6362_IPSEC_EN		(1 << 14)
162 #define CKCTL_6362_SPI_EN		(1 << 15)
163 #define CKCTL_6362_HSSPI_EN		(1 << 16)
164 #define CKCTL_6362_PCIE_EN		(1 << 17)
165 #define CKCTL_6362_FAP_EN		(1 << 18)
166 #define CKCTL_6362_PHYMIPS_EN		(1 << 19)
167 #define CKCTL_6362_NAND_EN		(1 << 20)
168 
169 #define CKCTL_6362_ALL_SAFE_EN		(CKCTL_6362_PHYMIPS_EN |	\
170 					CKCTL_6362_ADSL_QPROC_EN |	\
171 					CKCTL_6362_ADSL_AFE_EN |	\
172 					CKCTL_6362_ADSL_EN |		\
173 					CKCTL_6362_SAR_EN  |		\
174 					CKCTL_6362_PCM_EN  |		\
175 					CKCTL_6362_IPSEC_EN |		\
176 					CKCTL_6362_USBD_EN |		\
177 					CKCTL_6362_USBH_EN |		\
178 					CKCTL_6362_ROBOSW_EN |		\
179 					CKCTL_6362_PCIE_EN)
180 
181 
182 #define CKCTL_6368_VDSL_QPROC_EN	(1 << 2)
183 #define CKCTL_6368_VDSL_AFE_EN		(1 << 3)
184 #define CKCTL_6368_VDSL_BONDING_EN	(1 << 4)
185 #define CKCTL_6368_VDSL_EN		(1 << 5)
186 #define CKCTL_6368_PHYMIPS_EN		(1 << 6)
187 #define CKCTL_6368_SWPKT_USB_EN		(1 << 7)
188 #define CKCTL_6368_SWPKT_SAR_EN		(1 << 8)
189 #define CKCTL_6368_SPI_EN		(1 << 9)
190 #define CKCTL_6368_USBD_EN		(1 << 10)
191 #define CKCTL_6368_SAR_EN		(1 << 11)
192 #define CKCTL_6368_ROBOSW_EN		(1 << 12)
193 #define CKCTL_6368_UTOPIA_EN		(1 << 13)
194 #define CKCTL_6368_PCM_EN		(1 << 14)
195 #define CKCTL_6368_USBH_EN		(1 << 15)
196 #define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
197 #define CKCTL_6368_NAND_EN		(1 << 17)
198 #define CKCTL_6368_IPSEC_EN		(1 << 18)
199 
200 #define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
201 					CKCTL_6368_SWPKT_SAR_EN |	\
202 					CKCTL_6368_SPI_EN |		\
203 					CKCTL_6368_USBD_EN |		\
204 					CKCTL_6368_SAR_EN |		\
205 					CKCTL_6368_ROBOSW_EN |		\
206 					CKCTL_6368_UTOPIA_EN |		\
207 					CKCTL_6368_PCM_EN |		\
208 					CKCTL_6368_USBH_EN |		\
209 					CKCTL_6368_DISABLE_GLESS_EN |	\
210 					CKCTL_6368_NAND_EN |		\
211 					CKCTL_6368_IPSEC_EN)
212 
213 /* System PLL Control register	*/
214 #define PERF_SYS_PLL_CTL_REG		0x8
215 #define SYS_PLL_SOFT_RESET		0x1
216 
217 /* Interrupt Mask register */
218 #define PERF_IRQMASK_3368_REG		0xc
219 #define PERF_IRQMASK_6328_REG(x)	(0x20 + (x) * 0x10)
220 #define PERF_IRQMASK_6338_REG		0xc
221 #define PERF_IRQMASK_6345_REG		0xc
222 #define PERF_IRQMASK_6348_REG		0xc
223 #define PERF_IRQMASK_6358_REG(x)	(0xc + (x) * 0x2c)
224 #define PERF_IRQMASK_6362_REG(x)	(0x20 + (x) * 0x10)
225 #define PERF_IRQMASK_6368_REG(x)	(0x20 + (x) * 0x10)
226 
227 /* Interrupt Status register */
228 #define PERF_IRQSTAT_3368_REG		0x10
229 #define PERF_IRQSTAT_6328_REG(x)	(0x28 + (x) * 0x10)
230 #define PERF_IRQSTAT_6338_REG		0x10
231 #define PERF_IRQSTAT_6345_REG		0x10
232 #define PERF_IRQSTAT_6348_REG		0x10
233 #define PERF_IRQSTAT_6358_REG(x)	(0x10 + (x) * 0x2c)
234 #define PERF_IRQSTAT_6362_REG(x)	(0x28 + (x) * 0x10)
235 #define PERF_IRQSTAT_6368_REG(x)	(0x28 + (x) * 0x10)
236 
237 /* External Interrupt Configuration register */
238 #define PERF_EXTIRQ_CFG_REG_3368	0x14
239 #define PERF_EXTIRQ_CFG_REG_6328	0x18
240 #define PERF_EXTIRQ_CFG_REG_6338	0x14
241 #define PERF_EXTIRQ_CFG_REG_6345	0x14
242 #define PERF_EXTIRQ_CFG_REG_6348	0x14
243 #define PERF_EXTIRQ_CFG_REG_6358	0x14
244 #define PERF_EXTIRQ_CFG_REG_6362	0x18
245 #define PERF_EXTIRQ_CFG_REG_6368	0x18
246 
247 #define PERF_EXTIRQ_CFG_REG2_6368	0x1c
248 
249 /* for 6348 only */
250 #define EXTIRQ_CFG_SENSE_6348(x)	(1 << (x))
251 #define EXTIRQ_CFG_STAT_6348(x)		(1 << (x + 5))
252 #define EXTIRQ_CFG_CLEAR_6348(x)	(1 << (x + 10))
253 #define EXTIRQ_CFG_MASK_6348(x)		(1 << (x + 15))
254 #define EXTIRQ_CFG_BOTHEDGE_6348(x)	(1 << (x + 20))
255 #define EXTIRQ_CFG_LEVELSENSE_6348(x)	(1 << (x + 25))
256 #define EXTIRQ_CFG_CLEAR_ALL_6348	(0xf << 10)
257 #define EXTIRQ_CFG_MASK_ALL_6348	(0xf << 15)
258 
259 /* for all others */
260 #define EXTIRQ_CFG_SENSE(x)		(1 << (x))
261 #define EXTIRQ_CFG_STAT(x)		(1 << (x + 4))
262 #define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 8))
263 #define EXTIRQ_CFG_MASK(x)		(1 << (x + 12))
264 #define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 16))
265 #define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 20))
266 #define EXTIRQ_CFG_CLEAR_ALL		(0xf << 8)
267 #define EXTIRQ_CFG_MASK_ALL		(0xf << 12)
268 
269 /* Soft Reset register */
270 #define PERF_SOFTRESET_REG		0x28
271 #define PERF_SOFTRESET_6328_REG		0x10
272 #define PERF_SOFTRESET_6358_REG		0x34
273 #define PERF_SOFTRESET_6362_REG		0x10
274 #define PERF_SOFTRESET_6368_REG		0x10
275 
276 #define SOFTRESET_3368_SPI_MASK		(1 << 0)
277 #define SOFTRESET_3368_ENET_MASK	(1 << 2)
278 #define SOFTRESET_3368_MPI_MASK		(1 << 3)
279 #define SOFTRESET_3368_EPHY_MASK	(1 << 6)
280 #define SOFTRESET_3368_USBS_MASK	(1 << 11)
281 #define SOFTRESET_3368_PCM_MASK		(1 << 13)
282 
283 #define SOFTRESET_6328_SPI_MASK		(1 << 0)
284 #define SOFTRESET_6328_EPHY_MASK	(1 << 1)
285 #define SOFTRESET_6328_SAR_MASK		(1 << 2)
286 #define SOFTRESET_6328_ENETSW_MASK	(1 << 3)
287 #define SOFTRESET_6328_USBS_MASK	(1 << 4)
288 #define SOFTRESET_6328_USBH_MASK	(1 << 5)
289 #define SOFTRESET_6328_PCM_MASK		(1 << 6)
290 #define SOFTRESET_6328_PCIE_CORE_MASK	(1 << 7)
291 #define SOFTRESET_6328_PCIE_MASK	(1 << 8)
292 #define SOFTRESET_6328_PCIE_EXT_MASK	(1 << 9)
293 #define SOFTRESET_6328_PCIE_HARD_MASK	(1 << 10)
294 
295 #define SOFTRESET_6338_SPI_MASK		(1 << 0)
296 #define SOFTRESET_6338_ENET_MASK	(1 << 2)
297 #define SOFTRESET_6338_USBH_MASK	(1 << 3)
298 #define SOFTRESET_6338_USBS_MASK	(1 << 4)
299 #define SOFTRESET_6338_ADSL_MASK	(1 << 5)
300 #define SOFTRESET_6338_DMAMEM_MASK	(1 << 6)
301 #define SOFTRESET_6338_SAR_MASK		(1 << 7)
302 #define SOFTRESET_6338_ACLC_MASK	(1 << 8)
303 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
304 #define SOFTRESET_6338_ALL	 (SOFTRESET_6338_SPI_MASK |		\
305 				  SOFTRESET_6338_ENET_MASK |		\
306 				  SOFTRESET_6338_USBH_MASK |		\
307 				  SOFTRESET_6338_USBS_MASK |		\
308 				  SOFTRESET_6338_ADSL_MASK |		\
309 				  SOFTRESET_6338_DMAMEM_MASK |		\
310 				  SOFTRESET_6338_SAR_MASK |		\
311 				  SOFTRESET_6338_ACLC_MASK |		\
312 				  SOFTRESET_6338_ADSLMIPSPLL_MASK)
313 
314 #define SOFTRESET_6348_SPI_MASK		(1 << 0)
315 #define SOFTRESET_6348_ENET_MASK	(1 << 2)
316 #define SOFTRESET_6348_USBH_MASK	(1 << 3)
317 #define SOFTRESET_6348_USBS_MASK	(1 << 4)
318 #define SOFTRESET_6348_ADSL_MASK	(1 << 5)
319 #define SOFTRESET_6348_DMAMEM_MASK	(1 << 6)
320 #define SOFTRESET_6348_SAR_MASK		(1 << 7)
321 #define SOFTRESET_6348_ACLC_MASK	(1 << 8)
322 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
323 
324 #define SOFTRESET_6348_ALL	 (SOFTRESET_6348_SPI_MASK |		\
325 				  SOFTRESET_6348_ENET_MASK |		\
326 				  SOFTRESET_6348_USBH_MASK |		\
327 				  SOFTRESET_6348_USBS_MASK |		\
328 				  SOFTRESET_6348_ADSL_MASK |		\
329 				  SOFTRESET_6348_DMAMEM_MASK |		\
330 				  SOFTRESET_6348_SAR_MASK |		\
331 				  SOFTRESET_6348_ACLC_MASK |		\
332 				  SOFTRESET_6348_ADSLMIPSPLL_MASK)
333 
334 #define SOFTRESET_6358_SPI_MASK		(1 << 0)
335 #define SOFTRESET_6358_ENET_MASK	(1 << 2)
336 #define SOFTRESET_6358_MPI_MASK		(1 << 3)
337 #define SOFTRESET_6358_EPHY_MASK	(1 << 6)
338 #define SOFTRESET_6358_SAR_MASK		(1 << 7)
339 #define SOFTRESET_6358_USBH_MASK	(1 << 12)
340 #define SOFTRESET_6358_PCM_MASK		(1 << 13)
341 #define SOFTRESET_6358_ADSL_MASK	(1 << 14)
342 
343 #define SOFTRESET_6362_SPI_MASK		(1 << 0)
344 #define SOFTRESET_6362_IPSEC_MASK	(1 << 1)
345 #define SOFTRESET_6362_EPHY_MASK	(1 << 2)
346 #define SOFTRESET_6362_SAR_MASK		(1 << 3)
347 #define SOFTRESET_6362_ENETSW_MASK	(1 << 4)
348 #define SOFTRESET_6362_USBS_MASK	(1 << 5)
349 #define SOFTRESET_6362_USBH_MASK	(1 << 6)
350 #define SOFTRESET_6362_PCM_MASK		(1 << 7)
351 #define SOFTRESET_6362_PCIE_CORE_MASK	(1 << 8)
352 #define SOFTRESET_6362_PCIE_MASK	(1 << 9)
353 #define SOFTRESET_6362_PCIE_EXT_MASK	(1 << 10)
354 #define SOFTRESET_6362_WLAN_SHIM_MASK	(1 << 11)
355 #define SOFTRESET_6362_DDR_PHY_MASK	(1 << 12)
356 #define SOFTRESET_6362_FAP_MASK		(1 << 13)
357 #define SOFTRESET_6362_WLAN_UBUS_MASK	(1 << 14)
358 
359 #define SOFTRESET_6368_SPI_MASK		(1 << 0)
360 #define SOFTRESET_6368_MPI_MASK		(1 << 3)
361 #define SOFTRESET_6368_EPHY_MASK	(1 << 6)
362 #define SOFTRESET_6368_SAR_MASK		(1 << 7)
363 #define SOFTRESET_6368_ENETSW_MASK	(1 << 10)
364 #define SOFTRESET_6368_USBS_MASK	(1 << 11)
365 #define SOFTRESET_6368_USBH_MASK	(1 << 12)
366 #define SOFTRESET_6368_PCM_MASK		(1 << 13)
367 
368 /* MIPS PLL control register */
369 #define PERF_MIPSPLLCTL_REG		0x34
370 #define MIPSPLLCTL_N1_SHIFT		20
371 #define MIPSPLLCTL_N1_MASK		(0x7 << MIPSPLLCTL_N1_SHIFT)
372 #define MIPSPLLCTL_N2_SHIFT		15
373 #define MIPSPLLCTL_N2_MASK		(0x1f << MIPSPLLCTL_N2_SHIFT)
374 #define MIPSPLLCTL_M1REF_SHIFT		12
375 #define MIPSPLLCTL_M1REF_MASK		(0x7 << MIPSPLLCTL_M1REF_SHIFT)
376 #define MIPSPLLCTL_M2REF_SHIFT		9
377 #define MIPSPLLCTL_M2REF_MASK		(0x7 << MIPSPLLCTL_M2REF_SHIFT)
378 #define MIPSPLLCTL_M1CPU_SHIFT		6
379 #define MIPSPLLCTL_M1CPU_MASK		(0x7 << MIPSPLLCTL_M1CPU_SHIFT)
380 #define MIPSPLLCTL_M1BUS_SHIFT		3
381 #define MIPSPLLCTL_M1BUS_MASK		(0x7 << MIPSPLLCTL_M1BUS_SHIFT)
382 #define MIPSPLLCTL_M2BUS_SHIFT		0
383 #define MIPSPLLCTL_M2BUS_MASK		(0x7 << MIPSPLLCTL_M2BUS_SHIFT)
384 
385 /* ADSL PHY PLL Control register */
386 #define PERF_ADSLPLLCTL_REG		0x38
387 #define ADSLPLLCTL_N1_SHIFT		20
388 #define ADSLPLLCTL_N1_MASK		(0x7 << ADSLPLLCTL_N1_SHIFT)
389 #define ADSLPLLCTL_N2_SHIFT		15
390 #define ADSLPLLCTL_N2_MASK		(0x1f << ADSLPLLCTL_N2_SHIFT)
391 #define ADSLPLLCTL_M1REF_SHIFT		12
392 #define ADSLPLLCTL_M1REF_MASK		(0x7 << ADSLPLLCTL_M1REF_SHIFT)
393 #define ADSLPLLCTL_M2REF_SHIFT		9
394 #define ADSLPLLCTL_M2REF_MASK		(0x7 << ADSLPLLCTL_M2REF_SHIFT)
395 #define ADSLPLLCTL_M1CPU_SHIFT		6
396 #define ADSLPLLCTL_M1CPU_MASK		(0x7 << ADSLPLLCTL_M1CPU_SHIFT)
397 #define ADSLPLLCTL_M1BUS_SHIFT		3
398 #define ADSLPLLCTL_M1BUS_MASK		(0x7 << ADSLPLLCTL_M1BUS_SHIFT)
399 #define ADSLPLLCTL_M2BUS_SHIFT		0
400 #define ADSLPLLCTL_M2BUS_MASK		(0x7 << ADSLPLLCTL_M2BUS_SHIFT)
401 
402 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus)	\
403 				(((n1) << ADSLPLLCTL_N1_SHIFT) |	\
404 				((n2) << ADSLPLLCTL_N2_SHIFT) |		\
405 				((m1ref) << ADSLPLLCTL_M1REF_SHIFT) |	\
406 				((m2ref) << ADSLPLLCTL_M2REF_SHIFT) |	\
407 				((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) |	\
408 				((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) |	\
409 				((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
410 
411 
412 /*************************************************************************
413  * _REG relative to RSET_TIMER
414  *************************************************************************/
415 
416 #define BCM63XX_TIMER_COUNT		4
417 #define TIMER_T0_ID			0
418 #define TIMER_T1_ID			1
419 #define TIMER_T2_ID			2
420 #define TIMER_WDT_ID			3
421 
422 /* Timer irqstat register */
423 #define TIMER_IRQSTAT_REG		0
424 #define TIMER_IRQSTAT_TIMER_CAUSE(x)	(1 << (x))
425 #define TIMER_IRQSTAT_TIMER0_CAUSE	(1 << 0)
426 #define TIMER_IRQSTAT_TIMER1_CAUSE	(1 << 1)
427 #define TIMER_IRQSTAT_TIMER2_CAUSE	(1 << 2)
428 #define TIMER_IRQSTAT_WDT_CAUSE		(1 << 3)
429 #define TIMER_IRQSTAT_TIMER_IR_EN(x)	(1 << ((x) + 8))
430 #define TIMER_IRQSTAT_TIMER0_IR_EN	(1 << 8)
431 #define TIMER_IRQSTAT_TIMER1_IR_EN	(1 << 9)
432 #define TIMER_IRQSTAT_TIMER2_IR_EN	(1 << 10)
433 
434 /* Timer control register */
435 #define TIMER_CTLx_REG(x)		(0x4 + (x * 4))
436 #define TIMER_CTL0_REG			0x4
437 #define TIMER_CTL1_REG			0x8
438 #define TIMER_CTL2_REG			0xC
439 #define TIMER_CTL_COUNTDOWN_MASK	(0x3fffffff)
440 #define TIMER_CTL_MONOTONIC_MASK	(1 << 30)
441 #define TIMER_CTL_ENABLE_MASK		(1 << 31)
442 
443 
444 /*************************************************************************
445  * _REG relative to RSET_WDT
446  *************************************************************************/
447 
448 /* Watchdog default count register */
449 #define WDT_DEFVAL_REG			0x0
450 
451 /* Watchdog control register */
452 #define WDT_CTL_REG			0x4
453 
454 /* Watchdog control register constants */
455 #define WDT_START_1			(0xff00)
456 #define WDT_START_2			(0x00ff)
457 #define WDT_STOP_1			(0xee00)
458 #define WDT_STOP_2			(0x00ee)
459 
460 /* Watchdog reset length register */
461 #define WDT_RSTLEN_REG			0x8
462 
463 /* Watchdog soft reset register (BCM6328 only) */
464 #define WDT_SOFTRESET_REG		0xc
465 
466 /*************************************************************************
467  * _REG relative to RSET_GPIO
468  *************************************************************************/
469 
470 /* GPIO registers */
471 #define GPIO_CTL_HI_REG			0x0
472 #define GPIO_CTL_LO_REG			0x4
473 #define GPIO_DATA_HI_REG		0x8
474 #define GPIO_DATA_LO_REG		0xC
475 #define GPIO_DATA_LO_REG_6345		0x8
476 
477 /* GPIO mux registers and constants */
478 #define GPIO_MODE_REG			0x18
479 
480 #define GPIO_MODE_6348_G4_DIAG		0x00090000
481 #define GPIO_MODE_6348_G4_UTOPIA	0x00080000
482 #define GPIO_MODE_6348_G4_LEGACY_LED	0x00030000
483 #define GPIO_MODE_6348_G4_MII_SNOOP	0x00020000
484 #define GPIO_MODE_6348_G4_EXT_EPHY	0x00010000
485 #define GPIO_MODE_6348_G3_DIAG		0x00009000
486 #define GPIO_MODE_6348_G3_UTOPIA	0x00008000
487 #define GPIO_MODE_6348_G3_EXT_MII	0x00007000
488 #define GPIO_MODE_6348_G2_DIAG		0x00000900
489 #define GPIO_MODE_6348_G2_PCI		0x00000500
490 #define GPIO_MODE_6348_G1_DIAG		0x00000090
491 #define GPIO_MODE_6348_G1_UTOPIA	0x00000080
492 #define GPIO_MODE_6348_G1_SPI_UART	0x00000060
493 #define GPIO_MODE_6348_G1_SPI_MASTER	0x00000060
494 #define GPIO_MODE_6348_G1_MII_PCCARD	0x00000040
495 #define GPIO_MODE_6348_G1_MII_SNOOP	0x00000020
496 #define GPIO_MODE_6348_G1_EXT_EPHY	0x00000010
497 #define GPIO_MODE_6348_G0_DIAG		0x00000009
498 #define GPIO_MODE_6348_G0_EXT_MII	0x00000007
499 
500 #define GPIO_MODE_6358_EXTRACS		(1 << 5)
501 #define GPIO_MODE_6358_UART1		(1 << 6)
502 #define GPIO_MODE_6358_EXTRA_SPI_SS	(1 << 7)
503 #define GPIO_MODE_6358_SERIAL_LED	(1 << 10)
504 #define GPIO_MODE_6358_UTOPIA		(1 << 12)
505 
506 #define GPIO_MODE_6368_ANALOG_AFE_0	(1 << 0)
507 #define GPIO_MODE_6368_ANALOG_AFE_1	(1 << 1)
508 #define GPIO_MODE_6368_SYS_IRQ		(1 << 2)
509 #define GPIO_MODE_6368_SERIAL_LED_DATA	(1 << 3)
510 #define GPIO_MODE_6368_SERIAL_LED_CLK	(1 << 4)
511 #define GPIO_MODE_6368_INET_LED		(1 << 5)
512 #define GPIO_MODE_6368_EPHY0_LED	(1 << 6)
513 #define GPIO_MODE_6368_EPHY1_LED	(1 << 7)
514 #define GPIO_MODE_6368_EPHY2_LED	(1 << 8)
515 #define GPIO_MODE_6368_EPHY3_LED	(1 << 9)
516 #define GPIO_MODE_6368_ROBOSW_LED_DAT	(1 << 10)
517 #define GPIO_MODE_6368_ROBOSW_LED_CLK	(1 << 11)
518 #define GPIO_MODE_6368_ROBOSW_LED0	(1 << 12)
519 #define GPIO_MODE_6368_ROBOSW_LED1	(1 << 13)
520 #define GPIO_MODE_6368_USBD_LED		(1 << 14)
521 #define GPIO_MODE_6368_NTR_PULSE	(1 << 15)
522 #define GPIO_MODE_6368_PCI_REQ1		(1 << 16)
523 #define GPIO_MODE_6368_PCI_GNT1		(1 << 17)
524 #define GPIO_MODE_6368_PCI_INTB		(1 << 18)
525 #define GPIO_MODE_6368_PCI_REQ0		(1 << 19)
526 #define GPIO_MODE_6368_PCI_GNT0		(1 << 20)
527 #define GPIO_MODE_6368_PCMCIA_CD1	(1 << 22)
528 #define GPIO_MODE_6368_PCMCIA_CD2	(1 << 23)
529 #define GPIO_MODE_6368_PCMCIA_VS1	(1 << 24)
530 #define GPIO_MODE_6368_PCMCIA_VS2	(1 << 25)
531 #define GPIO_MODE_6368_EBI_CS2		(1 << 26)
532 #define GPIO_MODE_6368_EBI_CS3		(1 << 27)
533 #define GPIO_MODE_6368_SPI_SSN2		(1 << 28)
534 #define GPIO_MODE_6368_SPI_SSN3		(1 << 29)
535 #define GPIO_MODE_6368_SPI_SSN4		(1 << 30)
536 #define GPIO_MODE_6368_SPI_SSN5		(1 << 31)
537 
538 
539 #define GPIO_PINMUX_OTHR_REG		0x24
540 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
541 #define GPIO_PINMUX_OTHR_6328_USB_MASK	(3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
542 #define GPIO_PINMUX_OTHR_6328_USB_HOST	(1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
543 #define GPIO_PINMUX_OTHR_6328_USB_DEV	(2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
544 
545 #define GPIO_BASEMODE_6368_REG		0x38
546 #define GPIO_BASEMODE_6368_UART2	0x1
547 #define GPIO_BASEMODE_6368_GPIO		0x0
548 #define GPIO_BASEMODE_6368_MASK		0x7
549 /* those bits must be kept as read in gpio basemode register*/
550 
551 #define GPIO_STRAPBUS_REG		0x40
552 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
553 #define STRAPBUS_6358_BOOT_SEL_SERIAL	(0 << 1)
554 #define STRAPBUS_6368_BOOT_SEL_MASK	0x3
555 #define STRAPBUS_6368_BOOT_SEL_NAND	0
556 #define STRAPBUS_6368_BOOT_SEL_SERIAL	1
557 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
558 
559 
560 /*************************************************************************
561  * _REG relative to RSET_ENET
562  *************************************************************************/
563 
564 /* Receiver Configuration register */
565 #define ENET_RXCFG_REG			0x0
566 #define ENET_RXCFG_ALLMCAST_SHIFT	1
567 #define ENET_RXCFG_ALLMCAST_MASK	(1 << ENET_RXCFG_ALLMCAST_SHIFT)
568 #define ENET_RXCFG_PROMISC_SHIFT	3
569 #define ENET_RXCFG_PROMISC_MASK		(1 << ENET_RXCFG_PROMISC_SHIFT)
570 #define ENET_RXCFG_LOOPBACK_SHIFT	4
571 #define ENET_RXCFG_LOOPBACK_MASK	(1 << ENET_RXCFG_LOOPBACK_SHIFT)
572 #define ENET_RXCFG_ENFLOW_SHIFT		5
573 #define ENET_RXCFG_ENFLOW_MASK		(1 << ENET_RXCFG_ENFLOW_SHIFT)
574 
575 /* Receive Maximum Length register */
576 #define ENET_RXMAXLEN_REG		0x4
577 #define ENET_RXMAXLEN_SHIFT		0
578 #define ENET_RXMAXLEN_MASK		(0x7ff << ENET_RXMAXLEN_SHIFT)
579 
580 /* Transmit Maximum Length register */
581 #define ENET_TXMAXLEN_REG		0x8
582 #define ENET_TXMAXLEN_SHIFT		0
583 #define ENET_TXMAXLEN_MASK		(0x7ff << ENET_TXMAXLEN_SHIFT)
584 
585 /* MII Status/Control register */
586 #define ENET_MIISC_REG			0x10
587 #define ENET_MIISC_MDCFREQDIV_SHIFT	0
588 #define ENET_MIISC_MDCFREQDIV_MASK	(0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
589 #define ENET_MIISC_PREAMBLEEN_SHIFT	7
590 #define ENET_MIISC_PREAMBLEEN_MASK	(1 << ENET_MIISC_PREAMBLEEN_SHIFT)
591 
592 /* MII Data register */
593 #define ENET_MIIDATA_REG		0x14
594 #define ENET_MIIDATA_DATA_SHIFT		0
595 #define ENET_MIIDATA_DATA_MASK		(0xffff << ENET_MIIDATA_DATA_SHIFT)
596 #define ENET_MIIDATA_TA_SHIFT		16
597 #define ENET_MIIDATA_TA_MASK		(0x3 << ENET_MIIDATA_TA_SHIFT)
598 #define ENET_MIIDATA_REG_SHIFT		18
599 #define ENET_MIIDATA_REG_MASK		(0x1f << ENET_MIIDATA_REG_SHIFT)
600 #define ENET_MIIDATA_PHYID_SHIFT	23
601 #define ENET_MIIDATA_PHYID_MASK		(0x1f << ENET_MIIDATA_PHYID_SHIFT)
602 #define ENET_MIIDATA_OP_READ_MASK	(0x6 << 28)
603 #define ENET_MIIDATA_OP_WRITE_MASK	(0x5 << 28)
604 
605 /* Ethernet Interrupt Mask register */
606 #define ENET_IRMASK_REG			0x18
607 
608 /* Ethernet Interrupt register */
609 #define ENET_IR_REG			0x1c
610 #define ENET_IR_MII			(1 << 0)
611 #define ENET_IR_MIB			(1 << 1)
612 #define ENET_IR_FLOWC			(1 << 2)
613 
614 /* Ethernet Control register */
615 #define ENET_CTL_REG			0x2c
616 #define ENET_CTL_ENABLE_SHIFT		0
617 #define ENET_CTL_ENABLE_MASK		(1 << ENET_CTL_ENABLE_SHIFT)
618 #define ENET_CTL_DISABLE_SHIFT		1
619 #define ENET_CTL_DISABLE_MASK		(1 << ENET_CTL_DISABLE_SHIFT)
620 #define ENET_CTL_SRESET_SHIFT		2
621 #define ENET_CTL_SRESET_MASK		(1 << ENET_CTL_SRESET_SHIFT)
622 #define ENET_CTL_EPHYSEL_SHIFT		3
623 #define ENET_CTL_EPHYSEL_MASK		(1 << ENET_CTL_EPHYSEL_SHIFT)
624 
625 /* Transmit Control register */
626 #define ENET_TXCTL_REG			0x30
627 #define ENET_TXCTL_FD_SHIFT		0
628 #define ENET_TXCTL_FD_MASK		(1 << ENET_TXCTL_FD_SHIFT)
629 
630 /* Transmit Watermask register */
631 #define ENET_TXWMARK_REG		0x34
632 #define ENET_TXWMARK_WM_SHIFT		0
633 #define ENET_TXWMARK_WM_MASK		(0x3f << ENET_TXWMARK_WM_SHIFT)
634 
635 /* MIB Control register */
636 #define ENET_MIBCTL_REG			0x38
637 #define ENET_MIBCTL_RDCLEAR_SHIFT	0
638 #define ENET_MIBCTL_RDCLEAR_MASK	(1 << ENET_MIBCTL_RDCLEAR_SHIFT)
639 
640 /* Perfect Match Data Low register */
641 #define ENET_PML_REG(x)			(0x58 + (x) * 8)
642 #define ENET_PMH_REG(x)			(0x5c + (x) * 8)
643 #define ENET_PMH_DATAVALID_SHIFT	16
644 #define ENET_PMH_DATAVALID_MASK		(1 << ENET_PMH_DATAVALID_SHIFT)
645 
646 /* MIB register */
647 #define ENET_MIB_REG(x)			(0x200 + (x) * 4)
648 #define ENET_MIB_REG_COUNT		55
649 
650 
651 /*************************************************************************
652  * _REG relative to RSET_ENETDMA
653  *************************************************************************/
654 #define ENETDMA_CHAN_WIDTH		0x10
655 #define ENETDMA_6345_CHAN_WIDTH		0x40
656 
657 /* Controller Configuration Register */
658 #define ENETDMA_CFG_REG			(0x0)
659 #define ENETDMA_CFG_EN_SHIFT		0
660 #define ENETDMA_CFG_EN_MASK		(1 << ENETDMA_CFG_EN_SHIFT)
661 #define ENETDMA_CFG_FLOWCH_MASK(x)	(1 << ((x >> 1) + 1))
662 
663 /* Flow Control Descriptor Low Threshold register */
664 #define ENETDMA_FLOWCL_REG(x)		(0x4 + (x) * 6)
665 
666 /* Flow Control Descriptor High Threshold register */
667 #define ENETDMA_FLOWCH_REG(x)		(0x8 + (x) * 6)
668 
669 /* Flow Control Descriptor Buffer Alloca Threshold register */
670 #define ENETDMA_BUFALLOC_REG(x)		(0xc + (x) * 6)
671 #define ENETDMA_BUFALLOC_FORCE_SHIFT	31
672 #define ENETDMA_BUFALLOC_FORCE_MASK	(1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
673 
674 /* Global interrupt status */
675 #define ENETDMA_GLB_IRQSTAT_REG		(0x40)
676 
677 /* Global interrupt mask */
678 #define ENETDMA_GLB_IRQMASK_REG		(0x44)
679 
680 /* Channel Configuration register */
681 #define ENETDMA_CHANCFG_REG(x)		(0x100 + (x) * 0x10)
682 #define ENETDMA_CHANCFG_EN_SHIFT	0
683 #define ENETDMA_CHANCFG_EN_MASK		(1 << ENETDMA_CHANCFG_EN_SHIFT)
684 #define ENETDMA_CHANCFG_PKTHALT_SHIFT	1
685 #define ENETDMA_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
686 
687 /* Interrupt Control/Status register */
688 #define ENETDMA_IR_REG(x)		(0x104 + (x) * 0x10)
689 #define ENETDMA_IR_BUFDONE_MASK		(1 << 0)
690 #define ENETDMA_IR_PKTDONE_MASK		(1 << 1)
691 #define ENETDMA_IR_NOTOWNER_MASK	(1 << 2)
692 
693 /* Interrupt Mask register */
694 #define ENETDMA_IRMASK_REG(x)		(0x108 + (x) * 0x10)
695 
696 /* Maximum Burst Length */
697 #define ENETDMA_MAXBURST_REG(x)		(0x10C + (x) * 0x10)
698 
699 /* Ring Start Address register */
700 #define ENETDMA_RSTART_REG(x)		(0x200 + (x) * 0x10)
701 
702 /* State Ram Word 2 */
703 #define ENETDMA_SRAM2_REG(x)		(0x204 + (x) * 0x10)
704 
705 /* State Ram Word 3 */
706 #define ENETDMA_SRAM3_REG(x)		(0x208 + (x) * 0x10)
707 
708 /* State Ram Word 4 */
709 #define ENETDMA_SRAM4_REG(x)		(0x20c + (x) * 0x10)
710 
711 /* Broadcom 6345 ENET DMA definitions */
712 #define ENETDMA_6345_CHANCFG_REG	(0x00)
713 
714 #define ENETDMA_6345_MAXBURST_REG	(0x04)
715 
716 #define ENETDMA_6345_RSTART_REG		(0x08)
717 
718 #define ENETDMA_6345_LEN_REG		(0x0C)
719 
720 #define ENETDMA_6345_IR_REG		(0x14)
721 
722 #define ENETDMA_6345_IRMASK_REG		(0x18)
723 
724 #define ENETDMA_6345_FC_REG		(0x1C)
725 
726 #define ENETDMA_6345_BUFALLOC_REG	(0x20)
727 
728 /* Shift down for EOP, SOP and WRAP bits */
729 #define ENETDMA_6345_DESC_SHIFT		(3)
730 
731 /*************************************************************************
732  * _REG relative to RSET_ENETDMAC
733  *************************************************************************/
734 
735 /* Channel Configuration register */
736 #define ENETDMAC_CHANCFG_REG		(0x0)
737 #define ENETDMAC_CHANCFG_EN_SHIFT	0
738 #define ENETDMAC_CHANCFG_EN_MASK	(1 << ENETDMAC_CHANCFG_EN_SHIFT)
739 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT	1
740 #define ENETDMAC_CHANCFG_PKTHALT_MASK	(1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
741 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT	2
742 #define ENETDMAC_CHANCFG_BUFHALT_MASK	(1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
743 #define ENETDMAC_CHANCFG_CHAINING_SHIFT	2
744 #define ENETDMAC_CHANCFG_CHAINING_MASK	(1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
745 #define ENETDMAC_CHANCFG_WRAP_EN_SHIFT	3
746 #define ENETDMAC_CHANCFG_WRAP_EN_MASK	(1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
747 #define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT	4
748 #define ENETDMAC_CHANCFG_FLOWC_EN_MASK	(1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
749 
750 /* Interrupt Control/Status register */
751 #define ENETDMAC_IR_REG			(0x4)
752 #define ENETDMAC_IR_BUFDONE_MASK	(1 << 0)
753 #define ENETDMAC_IR_PKTDONE_MASK	(1 << 1)
754 #define ENETDMAC_IR_NOTOWNER_MASK	(1 << 2)
755 
756 /* Interrupt Mask register */
757 #define ENETDMAC_IRMASK_REG		(0x8)
758 
759 /* Maximum Burst Length */
760 #define ENETDMAC_MAXBURST_REG		(0xc)
761 
762 
763 /*************************************************************************
764  * _REG relative to RSET_ENETDMAS
765  *************************************************************************/
766 
767 /* Ring Start Address register */
768 #define ENETDMAS_RSTART_REG		(0x0)
769 
770 /* State Ram Word 2 */
771 #define ENETDMAS_SRAM2_REG		(0x4)
772 
773 /* State Ram Word 3 */
774 #define ENETDMAS_SRAM3_REG		(0x8)
775 
776 /* State Ram Word 4 */
777 #define ENETDMAS_SRAM4_REG		(0xc)
778 
779 
780 /*************************************************************************
781  * _REG relative to RSET_ENETSW
782  *************************************************************************/
783 
784 /* Port traffic control */
785 #define ENETSW_PTCTRL_REG(x)		(0x0 + (x))
786 #define ENETSW_PTCTRL_RXDIS_MASK	(1 << 0)
787 #define ENETSW_PTCTRL_TXDIS_MASK	(1 << 1)
788 
789 /* Switch mode register */
790 #define ENETSW_SWMODE_REG		(0xb)
791 #define ENETSW_SWMODE_FWD_EN_MASK	(1 << 1)
792 
793 /* IMP override Register */
794 #define ENETSW_IMPOV_REG		(0xe)
795 #define ENETSW_IMPOV_FORCE_MASK		(1 << 7)
796 #define ENETSW_IMPOV_TXFLOW_MASK	(1 << 5)
797 #define ENETSW_IMPOV_RXFLOW_MASK	(1 << 4)
798 #define ENETSW_IMPOV_1000_MASK		(1 << 3)
799 #define ENETSW_IMPOV_100_MASK		(1 << 2)
800 #define ENETSW_IMPOV_FDX_MASK		(1 << 1)
801 #define ENETSW_IMPOV_LINKUP_MASK	(1 << 0)
802 
803 /* Port override Register */
804 #define ENETSW_PORTOV_REG(x)		(0x58 + (x))
805 #define ENETSW_PORTOV_ENABLE_MASK	(1 << 6)
806 #define ENETSW_PORTOV_TXFLOW_MASK	(1 << 5)
807 #define ENETSW_PORTOV_RXFLOW_MASK	(1 << 4)
808 #define ENETSW_PORTOV_1000_MASK		(1 << 3)
809 #define ENETSW_PORTOV_100_MASK		(1 << 2)
810 #define ENETSW_PORTOV_FDX_MASK		(1 << 1)
811 #define ENETSW_PORTOV_LINKUP_MASK	(1 << 0)
812 
813 /* MDIO control register */
814 #define ENETSW_MDIOC_REG		(0xb0)
815 #define ENETSW_MDIOC_EXT_MASK		(1 << 16)
816 #define ENETSW_MDIOC_REG_SHIFT		20
817 #define ENETSW_MDIOC_PHYID_SHIFT	25
818 #define ENETSW_MDIOC_RD_MASK		(1 << 30)
819 #define ENETSW_MDIOC_WR_MASK		(1 << 31)
820 
821 /* MDIO data register */
822 #define ENETSW_MDIOD_REG		(0xb4)
823 
824 /* Global Management Configuration Register */
825 #define ENETSW_GMCR_REG			(0x200)
826 #define ENETSW_GMCR_RST_MIB_MASK	(1 << 0)
827 
828 /* MIB register */
829 #define ENETSW_MIB_REG(x)		(0x2800 + (x) * 4)
830 #define ENETSW_MIB_REG_COUNT		47
831 
832 /* Jumbo control register port mask register */
833 #define ENETSW_JMBCTL_PORT_REG		(0x4004)
834 
835 /* Jumbo control mib good frame register */
836 #define ENETSW_JMBCTL_MAXSIZE_REG	(0x4008)
837 
838 
839 /*************************************************************************
840  * _REG relative to RSET_OHCI_PRIV
841  *************************************************************************/
842 
843 #define OHCI_PRIV_REG			0x0
844 #define OHCI_PRIV_PORT1_HOST_SHIFT	0
845 #define OHCI_PRIV_PORT1_HOST_MASK	(1 << OHCI_PRIV_PORT1_HOST_SHIFT)
846 #define OHCI_PRIV_REG_SWAP_SHIFT	3
847 #define OHCI_PRIV_REG_SWAP_MASK		(1 << OHCI_PRIV_REG_SWAP_SHIFT)
848 
849 
850 /*************************************************************************
851  * _REG relative to RSET_USBH_PRIV
852  *************************************************************************/
853 
854 #define USBH_PRIV_SWAP_6358_REG		0x0
855 #define USBH_PRIV_SWAP_6368_REG		0x1c
856 
857 #define USBH_PRIV_SWAP_USBD_SHIFT	6
858 #define USBH_PRIV_SWAP_USBD_MASK	(1 << USBH_PRIV_SWAP_USBD_SHIFT)
859 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT	4
860 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
861 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT	3
862 #define USBH_PRIV_SWAP_EHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
863 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT	1
864 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
865 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT	0
866 #define USBH_PRIV_SWAP_OHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
867 
868 #define USBH_PRIV_UTMI_CTL_6368_REG	0x10
869 #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
870 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK	(0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
871 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT	0
872 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK	(0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
873 
874 #define USBH_PRIV_TEST_6358_REG		0x24
875 #define USBH_PRIV_TEST_6368_REG		0x14
876 
877 #define USBH_PRIV_SETUP_6368_REG	0x28
878 #define USBH_PRIV_SETUP_IOC_SHIFT	4
879 #define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
880 
881 
882 /*************************************************************************
883  * _REG relative to RSET_USBD
884  *************************************************************************/
885 
886 /* General control */
887 #define USBD_CONTROL_REG		0x00
888 #define USBD_CONTROL_TXZLENINS_SHIFT	14
889 #define USBD_CONTROL_TXZLENINS_MASK	(1 << USBD_CONTROL_TXZLENINS_SHIFT)
890 #define USBD_CONTROL_AUTO_CSRS_SHIFT	13
891 #define USBD_CONTROL_AUTO_CSRS_MASK	(1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
892 #define USBD_CONTROL_RXZSCFG_SHIFT	12
893 #define USBD_CONTROL_RXZSCFG_MASK	(1 << USBD_CONTROL_RXZSCFG_SHIFT)
894 #define USBD_CONTROL_INIT_SEL_SHIFT	8
895 #define USBD_CONTROL_INIT_SEL_MASK	(0xf << USBD_CONTROL_INIT_SEL_SHIFT)
896 #define USBD_CONTROL_FIFO_RESET_SHIFT	6
897 #define USBD_CONTROL_FIFO_RESET_MASK	(3 << USBD_CONTROL_FIFO_RESET_SHIFT)
898 #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
899 #define USBD_CONTROL_SETUPERRLOCK_MASK	(1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
900 #define USBD_CONTROL_DONE_CSRS_SHIFT	0
901 #define USBD_CONTROL_DONE_CSRS_MASK	(1 << USBD_CONTROL_DONE_CSRS_SHIFT)
902 
903 /* Strap options */
904 #define USBD_STRAPS_REG			0x04
905 #define USBD_STRAPS_APP_SELF_PWR_SHIFT	10
906 #define USBD_STRAPS_APP_SELF_PWR_MASK	(1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
907 #define USBD_STRAPS_APP_DISCON_SHIFT	9
908 #define USBD_STRAPS_APP_DISCON_MASK	(1 << USBD_STRAPS_APP_DISCON_SHIFT)
909 #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
910 #define USBD_STRAPS_APP_CSRPRGSUP_MASK	(1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
911 #define USBD_STRAPS_APP_RMTWKUP_SHIFT	6
912 #define USBD_STRAPS_APP_RMTWKUP_MASK	(1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
913 #define USBD_STRAPS_APP_RAM_IF_SHIFT	7
914 #define USBD_STRAPS_APP_RAM_IF_MASK	(1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
915 #define USBD_STRAPS_APP_8BITPHY_SHIFT	2
916 #define USBD_STRAPS_APP_8BITPHY_MASK	(1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
917 #define USBD_STRAPS_SPEED_SHIFT		0
918 #define USBD_STRAPS_SPEED_MASK		(3 << USBD_STRAPS_SPEED_SHIFT)
919 
920 /* Stall control */
921 #define USBD_STALL_REG			0x08
922 #define USBD_STALL_UPDATE_SHIFT		7
923 #define USBD_STALL_UPDATE_MASK		(1 << USBD_STALL_UPDATE_SHIFT)
924 #define USBD_STALL_ENABLE_SHIFT		6
925 #define USBD_STALL_ENABLE_MASK		(1 << USBD_STALL_ENABLE_SHIFT)
926 #define USBD_STALL_EPNUM_SHIFT		0
927 #define USBD_STALL_EPNUM_MASK		(0xf << USBD_STALL_EPNUM_SHIFT)
928 
929 /* General status */
930 #define USBD_STATUS_REG			0x0c
931 #define USBD_STATUS_SOF_SHIFT		16
932 #define USBD_STATUS_SOF_MASK		(0x7ff << USBD_STATUS_SOF_SHIFT)
933 #define USBD_STATUS_SPD_SHIFT		12
934 #define USBD_STATUS_SPD_MASK		(3 << USBD_STATUS_SPD_SHIFT)
935 #define USBD_STATUS_ALTINTF_SHIFT	8
936 #define USBD_STATUS_ALTINTF_MASK	(0xf << USBD_STATUS_ALTINTF_SHIFT)
937 #define USBD_STATUS_INTF_SHIFT		4
938 #define USBD_STATUS_INTF_MASK		(0xf << USBD_STATUS_INTF_SHIFT)
939 #define USBD_STATUS_CFG_SHIFT		0
940 #define USBD_STATUS_CFG_MASK		(0xf << USBD_STATUS_CFG_SHIFT)
941 
942 /* Other events */
943 #define USBD_EVENTS_REG			0x10
944 #define USBD_EVENTS_USB_LINK_SHIFT	10
945 #define USBD_EVENTS_USB_LINK_MASK	(1 << USBD_EVENTS_USB_LINK_SHIFT)
946 
947 /* IRQ status */
948 #define USBD_EVENT_IRQ_STATUS_REG	0x14
949 
950 /* IRQ level (2 bits per IRQ event) */
951 #define USBD_EVENT_IRQ_CFG_HI_REG	0x18
952 
953 #define USBD_EVENT_IRQ_CFG_LO_REG	0x1c
954 
955 #define USBD_EVENT_IRQ_CFG_SHIFT(x)	((x & 0xf) << 1)
956 #define USBD_EVENT_IRQ_CFG_MASK(x)	(3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
957 #define USBD_EVENT_IRQ_CFG_RISING(x)	(0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
958 #define USBD_EVENT_IRQ_CFG_FALLING(x)	(1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
959 
960 /* IRQ mask (1=unmasked) */
961 #define USBD_EVENT_IRQ_MASK_REG		0x20
962 
963 /* IRQ bits */
964 #define USBD_EVENT_IRQ_USB_LINK		10
965 #define USBD_EVENT_IRQ_SETCFG		9
966 #define USBD_EVENT_IRQ_SETINTF		8
967 #define USBD_EVENT_IRQ_ERRATIC_ERR	7
968 #define USBD_EVENT_IRQ_SET_CSRS		6
969 #define USBD_EVENT_IRQ_SUSPEND		5
970 #define USBD_EVENT_IRQ_EARLY_SUSPEND	4
971 #define USBD_EVENT_IRQ_SOF		3
972 #define USBD_EVENT_IRQ_ENUM_ON		2
973 #define USBD_EVENT_IRQ_SETUP		1
974 #define USBD_EVENT_IRQ_USB_RESET	0
975 
976 /* TX FIFO partitioning */
977 #define USBD_TXFIFO_CONFIG_REG		0x40
978 #define USBD_TXFIFO_CONFIG_END_SHIFT	16
979 #define USBD_TXFIFO_CONFIG_END_MASK	(0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
980 #define USBD_TXFIFO_CONFIG_START_SHIFT	0
981 #define USBD_TXFIFO_CONFIG_START_MASK	(0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
982 
983 /* RX FIFO partitioning */
984 #define USBD_RXFIFO_CONFIG_REG		0x44
985 #define USBD_RXFIFO_CONFIG_END_SHIFT	16
986 #define USBD_RXFIFO_CONFIG_END_MASK	(0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
987 #define USBD_RXFIFO_CONFIG_START_SHIFT	0
988 #define USBD_RXFIFO_CONFIG_START_MASK	(0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
989 
990 /* TX FIFO/endpoint configuration */
991 #define USBD_TXFIFO_EPSIZE_REG		0x48
992 
993 /* RX FIFO/endpoint configuration */
994 #define USBD_RXFIFO_EPSIZE_REG		0x4c
995 
996 /* Endpoint<->DMA mappings */
997 #define USBD_EPNUM_TYPEMAP_REG		0x50
998 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT	8
999 #define USBD_EPNUM_TYPEMAP_TYPE_MASK	(0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
1000 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
1001 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK	(0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
1002 
1003 /* Misc per-endpoint settings */
1004 #define USBD_CSR_SETUPADDR_REG		0x80
1005 #define USBD_CSR_SETUPADDR_DEF		0xb550
1006 
1007 #define USBD_CSR_EP_REG(x)		(0x84 + (x) * 4)
1008 #define USBD_CSR_EP_MAXPKT_SHIFT	19
1009 #define USBD_CSR_EP_MAXPKT_MASK		(0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
1010 #define USBD_CSR_EP_ALTIFACE_SHIFT	15
1011 #define USBD_CSR_EP_ALTIFACE_MASK	(0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
1012 #define USBD_CSR_EP_IFACE_SHIFT		11
1013 #define USBD_CSR_EP_IFACE_MASK		(0xf << USBD_CSR_EP_IFACE_SHIFT)
1014 #define USBD_CSR_EP_CFG_SHIFT		7
1015 #define USBD_CSR_EP_CFG_MASK		(0xf << USBD_CSR_EP_CFG_SHIFT)
1016 #define USBD_CSR_EP_TYPE_SHIFT		5
1017 #define USBD_CSR_EP_TYPE_MASK		(3 << USBD_CSR_EP_TYPE_SHIFT)
1018 #define USBD_CSR_EP_DIR_SHIFT		4
1019 #define USBD_CSR_EP_DIR_MASK		(1 << USBD_CSR_EP_DIR_SHIFT)
1020 #define USBD_CSR_EP_LOG_SHIFT		0
1021 #define USBD_CSR_EP_LOG_MASK		(0xf << USBD_CSR_EP_LOG_SHIFT)
1022 
1023 
1024 /*************************************************************************
1025  * _REG relative to RSET_MPI
1026  *************************************************************************/
1027 
1028 /* well known (hard wired) chip select */
1029 #define MPI_CS_PCMCIA_COMMON		4
1030 #define MPI_CS_PCMCIA_ATTR		5
1031 #define MPI_CS_PCMCIA_IO		6
1032 
1033 /* Chip select base register */
1034 #define MPI_CSBASE_REG(x)		(0x0 + (x) * 8)
1035 #define MPI_CSBASE_BASE_SHIFT		13
1036 #define MPI_CSBASE_BASE_MASK		(0x1ffff << MPI_CSBASE_BASE_SHIFT)
1037 #define MPI_CSBASE_SIZE_SHIFT		0
1038 #define MPI_CSBASE_SIZE_MASK		(0xf << MPI_CSBASE_SIZE_SHIFT)
1039 
1040 #define MPI_CSBASE_SIZE_8K		0
1041 #define MPI_CSBASE_SIZE_16K		1
1042 #define MPI_CSBASE_SIZE_32K		2
1043 #define MPI_CSBASE_SIZE_64K		3
1044 #define MPI_CSBASE_SIZE_128K		4
1045 #define MPI_CSBASE_SIZE_256K		5
1046 #define MPI_CSBASE_SIZE_512K		6
1047 #define MPI_CSBASE_SIZE_1M		7
1048 #define MPI_CSBASE_SIZE_2M		8
1049 #define MPI_CSBASE_SIZE_4M		9
1050 #define MPI_CSBASE_SIZE_8M		10
1051 #define MPI_CSBASE_SIZE_16M		11
1052 #define MPI_CSBASE_SIZE_32M		12
1053 #define MPI_CSBASE_SIZE_64M		13
1054 #define MPI_CSBASE_SIZE_128M		14
1055 #define MPI_CSBASE_SIZE_256M		15
1056 
1057 /* Chip select control register */
1058 #define MPI_CSCTL_REG(x)		(0x4 + (x) * 8)
1059 #define MPI_CSCTL_ENABLE_MASK		(1 << 0)
1060 #define MPI_CSCTL_WAIT_SHIFT		1
1061 #define MPI_CSCTL_WAIT_MASK		(0x7 << MPI_CSCTL_WAIT_SHIFT)
1062 #define MPI_CSCTL_DATA16_MASK		(1 << 4)
1063 #define MPI_CSCTL_SYNCMODE_MASK		(1 << 7)
1064 #define MPI_CSCTL_TSIZE_MASK		(1 << 8)
1065 #define MPI_CSCTL_ENDIANSWAP_MASK	(1 << 10)
1066 #define MPI_CSCTL_SETUP_SHIFT		16
1067 #define MPI_CSCTL_SETUP_MASK		(0xf << MPI_CSCTL_SETUP_SHIFT)
1068 #define MPI_CSCTL_HOLD_SHIFT		20
1069 #define MPI_CSCTL_HOLD_MASK		(0xf << MPI_CSCTL_HOLD_SHIFT)
1070 
1071 /* PCI registers */
1072 #define MPI_SP0_RANGE_REG		0x100
1073 #define MPI_SP0_REMAP_REG		0x104
1074 #define MPI_SP0_REMAP_ENABLE_MASK	(1 << 0)
1075 #define MPI_SP1_RANGE_REG		0x10C
1076 #define MPI_SP1_REMAP_REG		0x110
1077 #define MPI_SP1_REMAP_ENABLE_MASK	(1 << 0)
1078 
1079 #define MPI_L2PCFG_REG			0x11C
1080 #define MPI_L2PCFG_CFG_TYPE_SHIFT	0
1081 #define MPI_L2PCFG_CFG_TYPE_MASK	(0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
1082 #define MPI_L2PCFG_REG_SHIFT		2
1083 #define MPI_L2PCFG_REG_MASK		(0x3f << MPI_L2PCFG_REG_SHIFT)
1084 #define MPI_L2PCFG_FUNC_SHIFT		8
1085 #define MPI_L2PCFG_FUNC_MASK		(0x7 << MPI_L2PCFG_FUNC_SHIFT)
1086 #define MPI_L2PCFG_DEVNUM_SHIFT		11
1087 #define MPI_L2PCFG_DEVNUM_MASK		(0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
1088 #define MPI_L2PCFG_CFG_USEREG_MASK	(1 << 30)
1089 #define MPI_L2PCFG_CFG_SEL_MASK		(1 << 31)
1090 
1091 #define MPI_L2PMEMRANGE1_REG		0x120
1092 #define MPI_L2PMEMBASE1_REG		0x124
1093 #define MPI_L2PMEMREMAP1_REG		0x128
1094 #define MPI_L2PMEMRANGE2_REG		0x12C
1095 #define MPI_L2PMEMBASE2_REG		0x130
1096 #define MPI_L2PMEMREMAP2_REG		0x134
1097 #define MPI_L2PIORANGE_REG		0x138
1098 #define MPI_L2PIOBASE_REG		0x13C
1099 #define MPI_L2PIOREMAP_REG		0x140
1100 #define MPI_L2P_BASE_MASK		(0xffff8000)
1101 #define MPI_L2PREMAP_ENABLED_MASK	(1 << 0)
1102 #define MPI_L2PREMAP_IS_CARDBUS_MASK	(1 << 2)
1103 
1104 #define MPI_PCIMODESEL_REG		0x144
1105 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
1106 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
1107 #define MPI_PCIMODESEL_EXT_ARB_MASK	(1 << 2)
1108 #define MPI_PCIMODESEL_PREFETCH_SHIFT	4
1109 #define MPI_PCIMODESEL_PREFETCH_MASK	(0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
1110 
1111 #define MPI_LOCBUSCTL_REG		0x14C
1112 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK	(1 << 0)
1113 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK	(1 << 1)
1114 
1115 #define MPI_LOCINT_REG			0x150
1116 #define MPI_LOCINT_MASK(x)		(1 << (x + 16))
1117 #define MPI_LOCINT_STAT(x)		(1 << (x))
1118 #define MPI_LOCINT_DIR_FAILED		6
1119 #define MPI_LOCINT_EXT_PCI_INT		7
1120 #define MPI_LOCINT_SERR			8
1121 #define MPI_LOCINT_CSERR		9
1122 
1123 #define MPI_PCICFGCTL_REG		0x178
1124 #define MPI_PCICFGCTL_CFGADDR_SHIFT	2
1125 #define MPI_PCICFGCTL_CFGADDR_MASK	(0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
1126 #define MPI_PCICFGCTL_WRITEEN_MASK	(1 << 7)
1127 
1128 #define MPI_PCICFGDATA_REG		0x17C
1129 
1130 /* PCI host bridge custom register */
1131 #define BCMPCI_REG_TIMERS		0x40
1132 #define REG_TIMER_TRDY_SHIFT		0
1133 #define REG_TIMER_TRDY_MASK		(0xff << REG_TIMER_TRDY_SHIFT)
1134 #define REG_TIMER_RETRY_SHIFT		8
1135 #define REG_TIMER_RETRY_MASK		(0xff << REG_TIMER_RETRY_SHIFT)
1136 
1137 
1138 /*************************************************************************
1139  * _REG relative to RSET_PCMCIA
1140  *************************************************************************/
1141 
1142 #define PCMCIA_C1_REG			0x0
1143 #define PCMCIA_C1_CD1_MASK		(1 << 0)
1144 #define PCMCIA_C1_CD2_MASK		(1 << 1)
1145 #define PCMCIA_C1_VS1_MASK		(1 << 2)
1146 #define PCMCIA_C1_VS2_MASK		(1 << 3)
1147 #define PCMCIA_C1_VS1OE_MASK		(1 << 6)
1148 #define PCMCIA_C1_VS2OE_MASK		(1 << 7)
1149 #define PCMCIA_C1_CBIDSEL_SHIFT		(8)
1150 #define PCMCIA_C1_CBIDSEL_MASK		(0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
1151 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK	(1 << 13)
1152 #define PCMCIA_C1_EN_PCMCIA_MASK	(1 << 14)
1153 #define PCMCIA_C1_EN_CARDBUS_MASK	(1 << 15)
1154 #define PCMCIA_C1_RESET_MASK		(1 << 18)
1155 
1156 #define PCMCIA_C2_REG			0x8
1157 #define PCMCIA_C2_DATA16_MASK		(1 << 0)
1158 #define PCMCIA_C2_BYTESWAP_MASK		(1 << 1)
1159 #define PCMCIA_C2_RWCOUNT_SHIFT		2
1160 #define PCMCIA_C2_RWCOUNT_MASK		(0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
1161 #define PCMCIA_C2_INACTIVE_SHIFT	8
1162 #define PCMCIA_C2_INACTIVE_MASK		(0x3f << PCMCIA_C2_INACTIVE_SHIFT)
1163 #define PCMCIA_C2_SETUP_SHIFT		16
1164 #define PCMCIA_C2_SETUP_MASK		(0x3f << PCMCIA_C2_SETUP_SHIFT)
1165 #define PCMCIA_C2_HOLD_SHIFT		24
1166 #define PCMCIA_C2_HOLD_MASK		(0x3f << PCMCIA_C2_HOLD_SHIFT)
1167 
1168 
1169 /*************************************************************************
1170  * _REG relative to RSET_SDRAM
1171  *************************************************************************/
1172 
1173 #define SDRAM_CFG_REG			0x0
1174 #define SDRAM_CFG_ROW_SHIFT		4
1175 #define SDRAM_CFG_ROW_MASK		(0x3 << SDRAM_CFG_ROW_SHIFT)
1176 #define SDRAM_CFG_COL_SHIFT		6
1177 #define SDRAM_CFG_COL_MASK		(0x3 << SDRAM_CFG_COL_SHIFT)
1178 #define SDRAM_CFG_32B_SHIFT		10
1179 #define SDRAM_CFG_32B_MASK		(1 << SDRAM_CFG_32B_SHIFT)
1180 #define SDRAM_CFG_BANK_SHIFT		13
1181 #define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
1182 
1183 #define SDRAM_MBASE_REG			0xc
1184 
1185 #define SDRAM_PRIO_REG			0x2C
1186 #define SDRAM_PRIO_MIPS_SHIFT		29
1187 #define SDRAM_PRIO_MIPS_MASK		(1 << SDRAM_PRIO_MIPS_SHIFT)
1188 #define SDRAM_PRIO_ADSL_SHIFT		30
1189 #define SDRAM_PRIO_ADSL_MASK		(1 << SDRAM_PRIO_ADSL_SHIFT)
1190 #define SDRAM_PRIO_EN_SHIFT		31
1191 #define SDRAM_PRIO_EN_MASK		(1 << SDRAM_PRIO_EN_SHIFT)
1192 
1193 
1194 /*************************************************************************
1195  * _REG relative to RSET_MEMC
1196  *************************************************************************/
1197 
1198 #define MEMC_CFG_REG			0x4
1199 #define MEMC_CFG_32B_SHIFT		1
1200 #define MEMC_CFG_32B_MASK		(1 << MEMC_CFG_32B_SHIFT)
1201 #define MEMC_CFG_COL_SHIFT		3
1202 #define MEMC_CFG_COL_MASK		(0x3 << MEMC_CFG_COL_SHIFT)
1203 #define MEMC_CFG_ROW_SHIFT		6
1204 #define MEMC_CFG_ROW_MASK		(0x3 << MEMC_CFG_ROW_SHIFT)
1205 
1206 
1207 /*************************************************************************
1208  * _REG relative to RSET_DDR
1209  *************************************************************************/
1210 
1211 #define DDR_CSEND_REG			0x8
1212 
1213 #define DDR_DMIPSPLLCFG_REG		0x18
1214 #define DMIPSPLLCFG_M1_SHIFT		0
1215 #define DMIPSPLLCFG_M1_MASK		(0xff << DMIPSPLLCFG_M1_SHIFT)
1216 #define DMIPSPLLCFG_N1_SHIFT		23
1217 #define DMIPSPLLCFG_N1_MASK		(0x3f << DMIPSPLLCFG_N1_SHIFT)
1218 #define DMIPSPLLCFG_N2_SHIFT		29
1219 #define DMIPSPLLCFG_N2_MASK		(0x7 << DMIPSPLLCFG_N2_SHIFT)
1220 
1221 #define DDR_DMIPSPLLCFG_6368_REG	0x20
1222 #define DMIPSPLLCFG_6368_P1_SHIFT	0
1223 #define DMIPSPLLCFG_6368_P1_MASK	(0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1224 #define DMIPSPLLCFG_6368_P2_SHIFT	4
1225 #define DMIPSPLLCFG_6368_P2_MASK	(0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1226 #define DMIPSPLLCFG_6368_NDIV_SHIFT	16
1227 #define DMIPSPLLCFG_6368_NDIV_MASK	(0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1228 
1229 #define DDR_DMIPSPLLDIV_6368_REG	0x24
1230 #define DMIPSPLLDIV_6368_MDIV_SHIFT	0
1231 #define DMIPSPLLDIV_6368_MDIV_MASK	(0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1232 
1233 
1234 /*************************************************************************
1235  * _REG relative to RSET_M2M
1236  *************************************************************************/
1237 
1238 #define M2M_RX				0
1239 #define M2M_TX				1
1240 
1241 #define M2M_SRC_REG(x)			((x) * 0x40 + 0x00)
1242 #define M2M_DST_REG(x)			((x) * 0x40 + 0x04)
1243 #define M2M_SIZE_REG(x)			((x) * 0x40 + 0x08)
1244 
1245 #define M2M_CTRL_REG(x)			((x) * 0x40 + 0x0c)
1246 #define M2M_CTRL_ENABLE_MASK		(1 << 0)
1247 #define M2M_CTRL_IRQEN_MASK		(1 << 1)
1248 #define M2M_CTRL_ERROR_CLR_MASK		(1 << 6)
1249 #define M2M_CTRL_DONE_CLR_MASK		(1 << 7)
1250 #define M2M_CTRL_NOINC_MASK		(1 << 8)
1251 #define M2M_CTRL_PCMCIASWAP_MASK	(1 << 9)
1252 #define M2M_CTRL_SWAPBYTE_MASK		(1 << 10)
1253 #define M2M_CTRL_ENDIAN_MASK		(1 << 11)
1254 
1255 #define M2M_STAT_REG(x)			((x) * 0x40 + 0x10)
1256 #define M2M_STAT_DONE			(1 << 0)
1257 #define M2M_STAT_ERROR			(1 << 1)
1258 
1259 #define M2M_SRCID_REG(x)		((x) * 0x40 + 0x14)
1260 #define M2M_DSTID_REG(x)		((x) * 0x40 + 0x18)
1261 
1262 /*************************************************************************
1263  * _REG relative to RSET_SPI
1264  *************************************************************************/
1265 
1266 /* BCM 6338/6348 SPI core */
1267 #define SPI_6348_CMD			0x00	/* 16-bits register */
1268 #define SPI_6348_INT_STATUS		0x02
1269 #define SPI_6348_INT_MASK_ST		0x03
1270 #define SPI_6348_INT_MASK		0x04
1271 #define SPI_6348_ST			0x05
1272 #define SPI_6348_CLK_CFG		0x06
1273 #define SPI_6348_FILL_BYTE		0x07
1274 #define SPI_6348_MSG_TAIL		0x09
1275 #define SPI_6348_RX_TAIL		0x0b
1276 #define SPI_6348_MSG_CTL		0x40	/* 8-bits register */
1277 #define SPI_6348_MSG_CTL_WIDTH		8
1278 #define SPI_6348_MSG_DATA		0x41
1279 #define SPI_6348_MSG_DATA_SIZE		0x3f
1280 #define SPI_6348_RX_DATA		0x80
1281 #define SPI_6348_RX_DATA_SIZE		0x3f
1282 
1283 /* BCM 3368/6358/6262/6368 SPI core */
1284 #define SPI_6358_MSG_CTL		0x00	/* 16-bits register */
1285 #define SPI_6358_MSG_CTL_WIDTH		16
1286 #define SPI_6358_MSG_DATA		0x02
1287 #define SPI_6358_MSG_DATA_SIZE		0x21e
1288 #define SPI_6358_RX_DATA		0x400
1289 #define SPI_6358_RX_DATA_SIZE		0x220
1290 #define SPI_6358_CMD			0x700	/* 16-bits register */
1291 #define SPI_6358_INT_STATUS		0x702
1292 #define SPI_6358_INT_MASK_ST		0x703
1293 #define SPI_6358_INT_MASK		0x704
1294 #define SPI_6358_ST			0x705
1295 #define SPI_6358_CLK_CFG		0x706
1296 #define SPI_6358_FILL_BYTE		0x707
1297 #define SPI_6358_MSG_TAIL		0x709
1298 #define SPI_6358_RX_TAIL		0x70B
1299 
1300 /* Shared SPI definitions */
1301 
1302 /* Message configuration */
1303 #define SPI_FD_RW			0x00
1304 #define SPI_HD_W			0x01
1305 #define SPI_HD_R			0x02
1306 #define SPI_BYTE_CNT_SHIFT		0
1307 #define SPI_6348_MSG_TYPE_SHIFT		6
1308 #define SPI_6358_MSG_TYPE_SHIFT		14
1309 
1310 /* Command */
1311 #define SPI_CMD_NOOP			0x00
1312 #define SPI_CMD_SOFT_RESET		0x01
1313 #define SPI_CMD_HARD_RESET		0x02
1314 #define SPI_CMD_START_IMMEDIATE		0x03
1315 #define SPI_CMD_COMMAND_SHIFT		0
1316 #define SPI_CMD_COMMAND_MASK		0x000f
1317 #define SPI_CMD_DEVICE_ID_SHIFT		4
1318 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT	8
1319 #define SPI_CMD_ONE_BYTE_SHIFT		11
1320 #define SPI_CMD_ONE_WIRE_SHIFT		12
1321 #define SPI_DEV_ID_0			0
1322 #define SPI_DEV_ID_1			1
1323 #define SPI_DEV_ID_2			2
1324 #define SPI_DEV_ID_3			3
1325 
1326 /* Interrupt mask */
1327 #define SPI_INTR_CMD_DONE		0x01
1328 #define SPI_INTR_RX_OVERFLOW		0x02
1329 #define SPI_INTR_TX_UNDERFLOW		0x04
1330 #define SPI_INTR_TX_OVERFLOW		0x08
1331 #define SPI_INTR_RX_UNDERFLOW		0x10
1332 #define SPI_INTR_CLEAR_ALL		0x1f
1333 
1334 /* Status */
1335 #define SPI_RX_EMPTY			0x02
1336 #define SPI_CMD_BUSY			0x04
1337 #define SPI_SERIAL_BUSY			0x08
1338 
1339 /* Clock configuration */
1340 #define SPI_CLK_20MHZ			0x00
1341 #define SPI_CLK_0_391MHZ		0x01
1342 #define SPI_CLK_0_781MHZ		0x02 /* default */
1343 #define SPI_CLK_1_563MHZ		0x03
1344 #define SPI_CLK_3_125MHZ		0x04
1345 #define SPI_CLK_6_250MHZ		0x05
1346 #define SPI_CLK_12_50MHZ		0x06
1347 #define SPI_CLK_MASK			0x07
1348 #define SPI_SSOFFTIME_MASK		0x38
1349 #define SPI_SSOFFTIME_SHIFT		3
1350 #define SPI_BYTE_SWAP			0x80
1351 
1352 /*************************************************************************
1353  * _REG relative to RSET_MISC
1354  *************************************************************************/
1355 #define MISC_SERDES_CTRL_6328_REG	0x0
1356 #define MISC_SERDES_CTRL_6362_REG	0x4
1357 #define SERDES_PCIE_EN			(1 << 0)
1358 #define SERDES_PCIE_EXD_EN		(1 << 15)
1359 
1360 #define MISC_STRAPBUS_6362_REG		0x14
1361 #define STRAPBUS_6362_FCVO_SHIFT	1
1362 #define STRAPBUS_6362_HSSPI_CLK_FAST	(1 << 13)
1363 #define STRAPBUS_6362_FCVO_MASK		(0x1f << STRAPBUS_6362_FCVO_SHIFT)
1364 #define STRAPBUS_6362_BOOT_SEL_SERIAL	(1 << 15)
1365 #define STRAPBUS_6362_BOOT_SEL_NAND	(0 << 15)
1366 
1367 #define MISC_STRAPBUS_6328_REG		0x240
1368 #define STRAPBUS_6328_FCVO_SHIFT	7
1369 #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
1370 #define STRAPBUS_6328_BOOT_SEL_SERIAL	(1 << 18)
1371 #define STRAPBUS_6328_BOOT_SEL_NAND	(0 << 18)
1372 
1373 /*************************************************************************
1374  * _REG relative to RSET_PCIE
1375  *************************************************************************/
1376 
1377 #define PCIE_CONFIG2_REG		0x408
1378 #define CONFIG2_BAR1_SIZE_EN		1
1379 #define CONFIG2_BAR1_SIZE_MASK		0xf
1380 
1381 #define PCIE_IDVAL3_REG			0x43c
1382 #define IDVAL3_CLASS_CODE_MASK		0xffffff
1383 #define IDVAL3_SUBCLASS_SHIFT		8
1384 #define IDVAL3_CLASS_SHIFT		16
1385 
1386 #define PCIE_DLSTATUS_REG		0x1048
1387 #define DLSTATUS_PHYLINKUP		(1 << 13)
1388 
1389 #define PCIE_BRIDGE_OPT1_REG		0x2820
1390 #define OPT1_RD_BE_OPT_EN		(1 << 7)
1391 #define OPT1_RD_REPLY_BE_FIX_EN		(1 << 9)
1392 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN	(1 << 11)
1393 #define OPT1_L1_INT_STATUS_MASK_POL	(1 << 12)
1394 
1395 #define PCIE_BRIDGE_OPT2_REG		0x2824
1396 #define OPT2_UBUS_UR_DECODE_DIS		(1 << 2)
1397 #define OPT2_TX_CREDIT_CHK_EN		(1 << 4)
1398 #define OPT2_CFG_TYPE1_BD_SEL		(1 << 7)
1399 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT	16
1400 #define OPT2_CFG_TYPE1_BUS_NO_MASK	(0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1401 
1402 #define PCIE_BRIDGE_BAR0_BASEMASK_REG	0x2828
1403 #define PCIE_BRIDGE_BAR1_BASEMASK_REG	0x2830
1404 #define BASEMASK_REMAP_EN		(1 << 0)
1405 #define BASEMASK_SWAP_EN		(1 << 1)
1406 #define BASEMASK_MASK_SHIFT		4
1407 #define BASEMASK_MASK_MASK		(0xfff << BASEMASK_MASK_SHIFT)
1408 #define BASEMASK_BASE_SHIFT		20
1409 #define BASEMASK_BASE_MASK		(0xfff << BASEMASK_BASE_SHIFT)
1410 
1411 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1412 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1413 #define REBASE_ADDR_BASE_SHIFT		20
1414 #define REBASE_ADDR_BASE_MASK		(0xfff << REBASE_ADDR_BASE_SHIFT)
1415 
1416 #define PCIE_BRIDGE_RC_INT_MASK_REG	0x2854
1417 #define PCIE_RC_INT_A			(1 << 0)
1418 #define PCIE_RC_INT_B			(1 << 1)
1419 #define PCIE_RC_INT_C			(1 << 2)
1420 #define PCIE_RC_INT_D			(1 << 3)
1421 
1422 #define PCIE_DEVICE_OFFSET		0x8000
1423 
1424 /*************************************************************************
1425  * _REG relative to RSET_OTP
1426  *************************************************************************/
1427 
1428 #define OTP_USER_BITS_6328_REG(i)	(0x20 + (i) * 4)
1429 #define   OTP_6328_REG3_TP1_DISABLED	BIT(9)
1430 
1431 #endif /* BCM63XX_REGS_H_ */
1432