1e7300d04SMaxime Bizon #ifndef BCM63XX_REGS_H_ 2e7300d04SMaxime Bizon #define BCM63XX_REGS_H_ 3e7300d04SMaxime Bizon 4e7300d04SMaxime Bizon /************************************************************************* 5e7300d04SMaxime Bizon * _REG relative to RSET_PERF 6e7300d04SMaxime Bizon *************************************************************************/ 7e7300d04SMaxime Bizon 8e7300d04SMaxime Bizon /* Chip Identifier / Revision register */ 9e7300d04SMaxime Bizon #define PERF_REV_REG 0x0 10e7300d04SMaxime Bizon #define REV_CHIPID_SHIFT 16 11e7300d04SMaxime Bizon #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 12e7300d04SMaxime Bizon #define REV_REVID_SHIFT 0 13e7300d04SMaxime Bizon #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) 14e7300d04SMaxime Bizon 15e7300d04SMaxime Bizon /* Clock Control register */ 16e7300d04SMaxime Bizon #define PERF_CKCTL_REG 0x4 17e7300d04SMaxime Bizon 18e7300d04SMaxime Bizon #define CKCTL_6338_ADSLPHY_EN (1 << 0) 19e7300d04SMaxime Bizon #define CKCTL_6338_MPI_EN (1 << 1) 20e7300d04SMaxime Bizon #define CKCTL_6338_DRAM_EN (1 << 2) 21e7300d04SMaxime Bizon #define CKCTL_6338_ENET_EN (1 << 4) 22e7300d04SMaxime Bizon #define CKCTL_6338_USBS_EN (1 << 4) 23e7300d04SMaxime Bizon #define CKCTL_6338_SAR_EN (1 << 5) 24e7300d04SMaxime Bizon #define CKCTL_6338_SPI_EN (1 << 9) 25e7300d04SMaxime Bizon 26e7300d04SMaxime Bizon #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ 27e7300d04SMaxime Bizon CKCTL_6338_MPI_EN | \ 28e7300d04SMaxime Bizon CKCTL_6338_ENET_EN | \ 29e7300d04SMaxime Bizon CKCTL_6338_SAR_EN | \ 30e7300d04SMaxime Bizon CKCTL_6338_SPI_EN) 31e7300d04SMaxime Bizon 32e7300d04SMaxime Bizon #define CKCTL_6345_CPU_EN (1 << 0) 33e7300d04SMaxime Bizon #define CKCTL_6345_BUS_EN (1 << 1) 34e7300d04SMaxime Bizon #define CKCTL_6345_EBI_EN (1 << 2) 35e7300d04SMaxime Bizon #define CKCTL_6345_UART_EN (1 << 3) 36e7300d04SMaxime Bizon #define CKCTL_6345_ADSLPHY_EN (1 << 4) 37e7300d04SMaxime Bizon #define CKCTL_6345_ENET_EN (1 << 7) 38e7300d04SMaxime Bizon #define CKCTL_6345_USBH_EN (1 << 8) 39e7300d04SMaxime Bizon 40e7300d04SMaxime Bizon #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 41e7300d04SMaxime Bizon CKCTL_6345_USBH_EN | \ 42e7300d04SMaxime Bizon CKCTL_6345_ADSLPHY_EN) 43e7300d04SMaxime Bizon 44e7300d04SMaxime Bizon #define CKCTL_6348_ADSLPHY_EN (1 << 0) 45e7300d04SMaxime Bizon #define CKCTL_6348_MPI_EN (1 << 1) 46e7300d04SMaxime Bizon #define CKCTL_6348_SDRAM_EN (1 << 2) 47e7300d04SMaxime Bizon #define CKCTL_6348_M2M_EN (1 << 3) 48e7300d04SMaxime Bizon #define CKCTL_6348_ENET_EN (1 << 4) 49e7300d04SMaxime Bizon #define CKCTL_6348_SAR_EN (1 << 5) 50e7300d04SMaxime Bizon #define CKCTL_6348_USBS_EN (1 << 6) 51e7300d04SMaxime Bizon #define CKCTL_6348_USBH_EN (1 << 8) 52e7300d04SMaxime Bizon #define CKCTL_6348_SPI_EN (1 << 9) 53e7300d04SMaxime Bizon 54e7300d04SMaxime Bizon #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ 55e7300d04SMaxime Bizon CKCTL_6348_M2M_EN | \ 56e7300d04SMaxime Bizon CKCTL_6348_ENET_EN | \ 57e7300d04SMaxime Bizon CKCTL_6348_SAR_EN | \ 58e7300d04SMaxime Bizon CKCTL_6348_USBS_EN | \ 59e7300d04SMaxime Bizon CKCTL_6348_USBH_EN | \ 60e7300d04SMaxime Bizon CKCTL_6348_SPI_EN) 61e7300d04SMaxime Bizon 62e7300d04SMaxime Bizon #define CKCTL_6358_ENET_EN (1 << 4) 63e7300d04SMaxime Bizon #define CKCTL_6358_ADSLPHY_EN (1 << 5) 64e7300d04SMaxime Bizon #define CKCTL_6358_PCM_EN (1 << 8) 65e7300d04SMaxime Bizon #define CKCTL_6358_SPI_EN (1 << 9) 66e7300d04SMaxime Bizon #define CKCTL_6358_USBS_EN (1 << 10) 67e7300d04SMaxime Bizon #define CKCTL_6358_SAR_EN (1 << 11) 68e7300d04SMaxime Bizon #define CKCTL_6358_EMUSB_EN (1 << 17) 69e7300d04SMaxime Bizon #define CKCTL_6358_ENET0_EN (1 << 18) 70e7300d04SMaxime Bizon #define CKCTL_6358_ENET1_EN (1 << 19) 71e7300d04SMaxime Bizon #define CKCTL_6358_USBSU_EN (1 << 20) 72e7300d04SMaxime Bizon #define CKCTL_6358_EPHY_EN (1 << 21) 73e7300d04SMaxime Bizon 74e7300d04SMaxime Bizon #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ 75e7300d04SMaxime Bizon CKCTL_6358_ADSLPHY_EN | \ 76e7300d04SMaxime Bizon CKCTL_6358_PCM_EN | \ 77e7300d04SMaxime Bizon CKCTL_6358_SPI_EN | \ 78e7300d04SMaxime Bizon CKCTL_6358_USBS_EN | \ 79e7300d04SMaxime Bizon CKCTL_6358_SAR_EN | \ 80e7300d04SMaxime Bizon CKCTL_6358_EMUSB_EN | \ 81e7300d04SMaxime Bizon CKCTL_6358_ENET0_EN | \ 82e7300d04SMaxime Bizon CKCTL_6358_ENET1_EN | \ 83e7300d04SMaxime Bizon CKCTL_6358_USBSU_EN | \ 84e7300d04SMaxime Bizon CKCTL_6358_EPHY_EN) 85e7300d04SMaxime Bizon 8604712f3fSMaxime Bizon #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) 8704712f3fSMaxime Bizon #define CKCTL_6368_VDSL_AFE_EN (1 << 3) 8804712f3fSMaxime Bizon #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) 8904712f3fSMaxime Bizon #define CKCTL_6368_VDSL_EN (1 << 5) 9004712f3fSMaxime Bizon #define CKCTL_6368_PHYMIPS_EN (1 << 6) 9104712f3fSMaxime Bizon #define CKCTL_6368_SWPKT_USB_EN (1 << 7) 9204712f3fSMaxime Bizon #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) 93d9831a41SFlorian Fainelli #define CKCTL_6368_SPI_EN (1 << 9) 94d9831a41SFlorian Fainelli #define CKCTL_6368_USBD_EN (1 << 10) 95d9831a41SFlorian Fainelli #define CKCTL_6368_SAR_EN (1 << 11) 96d9831a41SFlorian Fainelli #define CKCTL_6368_ROBOSW_EN (1 << 12) 97d9831a41SFlorian Fainelli #define CKCTL_6368_UTOPIA_EN (1 << 13) 98d9831a41SFlorian Fainelli #define CKCTL_6368_PCM_EN (1 << 14) 99d9831a41SFlorian Fainelli #define CKCTL_6368_USBH_EN (1 << 15) 10004712f3fSMaxime Bizon #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) 101d9831a41SFlorian Fainelli #define CKCTL_6368_NAND_EN (1 << 17) 102d9831a41SFlorian Fainelli #define CKCTL_6368_IPSEC_EN (1 << 18) 10304712f3fSMaxime Bizon 10404712f3fSMaxime Bizon #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ 10504712f3fSMaxime Bizon CKCTL_6368_SWPKT_SAR_EN | \ 106d9831a41SFlorian Fainelli CKCTL_6368_SPI_EN | \ 107d9831a41SFlorian Fainelli CKCTL_6368_USBD_EN | \ 108d9831a41SFlorian Fainelli CKCTL_6368_SAR_EN | \ 109d9831a41SFlorian Fainelli CKCTL_6368_ROBOSW_EN | \ 110d9831a41SFlorian Fainelli CKCTL_6368_UTOPIA_EN | \ 111d9831a41SFlorian Fainelli CKCTL_6368_PCM_EN | \ 112d9831a41SFlorian Fainelli CKCTL_6368_USBH_EN | \ 11304712f3fSMaxime Bizon CKCTL_6368_DISABLE_GLESS_EN | \ 114d9831a41SFlorian Fainelli CKCTL_6368_NAND_EN | \ 115d9831a41SFlorian Fainelli CKCTL_6368_IPSEC_EN) 11604712f3fSMaxime Bizon 117e7300d04SMaxime Bizon /* System PLL Control register */ 118e7300d04SMaxime Bizon #define PERF_SYS_PLL_CTL_REG 0x8 119e7300d04SMaxime Bizon #define SYS_PLL_SOFT_RESET 0x1 120e7300d04SMaxime Bizon 121e7300d04SMaxime Bizon /* Interrupt Mask register */ 122f61cced9SMaxime Bizon #define PERF_IRQMASK_6338_REG 0xc 123f61cced9SMaxime Bizon #define PERF_IRQMASK_6345_REG 0xc 124f61cced9SMaxime Bizon #define PERF_IRQMASK_6348_REG 0xc 125f61cced9SMaxime Bizon #define PERF_IRQMASK_6358_REG 0xc 12604712f3fSMaxime Bizon #define PERF_IRQMASK_6368_REG 0x20 127e7300d04SMaxime Bizon 128e7300d04SMaxime Bizon /* Interrupt Status register */ 129f61cced9SMaxime Bizon #define PERF_IRQSTAT_6338_REG 0x10 130f61cced9SMaxime Bizon #define PERF_IRQSTAT_6345_REG 0x10 131f61cced9SMaxime Bizon #define PERF_IRQSTAT_6348_REG 0x10 132f61cced9SMaxime Bizon #define PERF_IRQSTAT_6358_REG 0x10 13304712f3fSMaxime Bizon #define PERF_IRQSTAT_6368_REG 0x28 134e7300d04SMaxime Bizon 135e7300d04SMaxime Bizon /* External Interrupt Configuration register */ 1366224892cSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6338 0x14 1376224892cSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6348 0x14 1386224892cSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6358 0x14 13904712f3fSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6368 0x18 14004712f3fSMaxime Bizon 14104712f3fSMaxime Bizon #define PERF_EXTIRQ_CFG_REG2_6368 0x1c 142e7300d04SMaxime Bizon 1436224892cSMaxime Bizon /* for 6348 only */ 1446224892cSMaxime Bizon #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) 1456224892cSMaxime Bizon #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5)) 1466224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10)) 1476224892cSMaxime Bizon #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15)) 1486224892cSMaxime Bizon #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20)) 1496224892cSMaxime Bizon #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25)) 1506224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10) 1516224892cSMaxime Bizon #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15) 1526224892cSMaxime Bizon 1536224892cSMaxime Bizon /* for all others */ 1546224892cSMaxime Bizon #define EXTIRQ_CFG_SENSE(x) (1 << (x)) 1556224892cSMaxime Bizon #define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) 1566224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) 1576224892cSMaxime Bizon #define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) 1586224892cSMaxime Bizon #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) 1596224892cSMaxime Bizon #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) 1606224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) 1616224892cSMaxime Bizon #define EXTIRQ_CFG_MASK_ALL (0xf << 12) 162e7300d04SMaxime Bizon 163e7300d04SMaxime Bizon /* Soft Reset register */ 164e7300d04SMaxime Bizon #define PERF_SOFTRESET_REG 0x28 16504712f3fSMaxime Bizon #define PERF_SOFTRESET_6368_REG 0x10 166e7300d04SMaxime Bizon 167e7300d04SMaxime Bizon #define SOFTRESET_6338_SPI_MASK (1 << 0) 168e7300d04SMaxime Bizon #define SOFTRESET_6338_ENET_MASK (1 << 2) 169e7300d04SMaxime Bizon #define SOFTRESET_6338_USBH_MASK (1 << 3) 170e7300d04SMaxime Bizon #define SOFTRESET_6338_USBS_MASK (1 << 4) 171e7300d04SMaxime Bizon #define SOFTRESET_6338_ADSL_MASK (1 << 5) 172e7300d04SMaxime Bizon #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) 173e7300d04SMaxime Bizon #define SOFTRESET_6338_SAR_MASK (1 << 7) 174e7300d04SMaxime Bizon #define SOFTRESET_6338_ACLC_MASK (1 << 8) 175e7300d04SMaxime Bizon #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) 176e7300d04SMaxime Bizon #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ 177e7300d04SMaxime Bizon SOFTRESET_6338_ENET_MASK | \ 178e7300d04SMaxime Bizon SOFTRESET_6338_USBH_MASK | \ 179e7300d04SMaxime Bizon SOFTRESET_6338_USBS_MASK | \ 180e7300d04SMaxime Bizon SOFTRESET_6338_ADSL_MASK | \ 181e7300d04SMaxime Bizon SOFTRESET_6338_DMAMEM_MASK | \ 182e7300d04SMaxime Bizon SOFTRESET_6338_SAR_MASK | \ 183e7300d04SMaxime Bizon SOFTRESET_6338_ACLC_MASK | \ 184e7300d04SMaxime Bizon SOFTRESET_6338_ADSLMIPSPLL_MASK) 185e7300d04SMaxime Bizon 186e7300d04SMaxime Bizon #define SOFTRESET_6348_SPI_MASK (1 << 0) 187e7300d04SMaxime Bizon #define SOFTRESET_6348_ENET_MASK (1 << 2) 188e7300d04SMaxime Bizon #define SOFTRESET_6348_USBH_MASK (1 << 3) 189e7300d04SMaxime Bizon #define SOFTRESET_6348_USBS_MASK (1 << 4) 190e7300d04SMaxime Bizon #define SOFTRESET_6348_ADSL_MASK (1 << 5) 191e7300d04SMaxime Bizon #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) 192e7300d04SMaxime Bizon #define SOFTRESET_6348_SAR_MASK (1 << 7) 193e7300d04SMaxime Bizon #define SOFTRESET_6348_ACLC_MASK (1 << 8) 194e7300d04SMaxime Bizon #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) 195e7300d04SMaxime Bizon 196e7300d04SMaxime Bizon #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ 197e7300d04SMaxime Bizon SOFTRESET_6348_ENET_MASK | \ 198e7300d04SMaxime Bizon SOFTRESET_6348_USBH_MASK | \ 199e7300d04SMaxime Bizon SOFTRESET_6348_USBS_MASK | \ 200e7300d04SMaxime Bizon SOFTRESET_6348_ADSL_MASK | \ 201e7300d04SMaxime Bizon SOFTRESET_6348_DMAMEM_MASK | \ 202e7300d04SMaxime Bizon SOFTRESET_6348_SAR_MASK | \ 203e7300d04SMaxime Bizon SOFTRESET_6348_ACLC_MASK | \ 204e7300d04SMaxime Bizon SOFTRESET_6348_ADSLMIPSPLL_MASK) 205e7300d04SMaxime Bizon 20604712f3fSMaxime Bizon #define SOFTRESET_6368_SPI_MASK (1 << 0) 20704712f3fSMaxime Bizon #define SOFTRESET_6368_MPI_MASK (1 << 3) 20804712f3fSMaxime Bizon #define SOFTRESET_6368_EPHY_MASK (1 << 6) 20904712f3fSMaxime Bizon #define SOFTRESET_6368_SAR_MASK (1 << 7) 21004712f3fSMaxime Bizon #define SOFTRESET_6368_ENETSW_MASK (1 << 10) 21104712f3fSMaxime Bizon #define SOFTRESET_6368_USBS_MASK (1 << 11) 21204712f3fSMaxime Bizon #define SOFTRESET_6368_USBH_MASK (1 << 12) 21304712f3fSMaxime Bizon #define SOFTRESET_6368_PCM_MASK (1 << 13) 21404712f3fSMaxime Bizon 215e7300d04SMaxime Bizon /* MIPS PLL control register */ 216e7300d04SMaxime Bizon #define PERF_MIPSPLLCTL_REG 0x34 217e7300d04SMaxime Bizon #define MIPSPLLCTL_N1_SHIFT 20 218e7300d04SMaxime Bizon #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) 219e7300d04SMaxime Bizon #define MIPSPLLCTL_N2_SHIFT 15 220e7300d04SMaxime Bizon #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) 221e7300d04SMaxime Bizon #define MIPSPLLCTL_M1REF_SHIFT 12 222e7300d04SMaxime Bizon #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) 223e7300d04SMaxime Bizon #define MIPSPLLCTL_M2REF_SHIFT 9 224e7300d04SMaxime Bizon #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) 225e7300d04SMaxime Bizon #define MIPSPLLCTL_M1CPU_SHIFT 6 226e7300d04SMaxime Bizon #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) 227e7300d04SMaxime Bizon #define MIPSPLLCTL_M1BUS_SHIFT 3 228e7300d04SMaxime Bizon #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) 229e7300d04SMaxime Bizon #define MIPSPLLCTL_M2BUS_SHIFT 0 230e7300d04SMaxime Bizon #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) 231e7300d04SMaxime Bizon 232e7300d04SMaxime Bizon /* ADSL PHY PLL Control register */ 233e7300d04SMaxime Bizon #define PERF_ADSLPLLCTL_REG 0x38 234e7300d04SMaxime Bizon #define ADSLPLLCTL_N1_SHIFT 20 235e7300d04SMaxime Bizon #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) 236e7300d04SMaxime Bizon #define ADSLPLLCTL_N2_SHIFT 15 237e7300d04SMaxime Bizon #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) 238e7300d04SMaxime Bizon #define ADSLPLLCTL_M1REF_SHIFT 12 239e7300d04SMaxime Bizon #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) 240e7300d04SMaxime Bizon #define ADSLPLLCTL_M2REF_SHIFT 9 241e7300d04SMaxime Bizon #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) 242e7300d04SMaxime Bizon #define ADSLPLLCTL_M1CPU_SHIFT 6 243e7300d04SMaxime Bizon #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) 244e7300d04SMaxime Bizon #define ADSLPLLCTL_M1BUS_SHIFT 3 245e7300d04SMaxime Bizon #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) 246e7300d04SMaxime Bizon #define ADSLPLLCTL_M2BUS_SHIFT 0 247e7300d04SMaxime Bizon #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) 248e7300d04SMaxime Bizon 249e7300d04SMaxime Bizon #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ 250e7300d04SMaxime Bizon (((n1) << ADSLPLLCTL_N1_SHIFT) | \ 251e7300d04SMaxime Bizon ((n2) << ADSLPLLCTL_N2_SHIFT) | \ 252e7300d04SMaxime Bizon ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ 253e7300d04SMaxime Bizon ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ 254e7300d04SMaxime Bizon ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ 255e7300d04SMaxime Bizon ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ 256e7300d04SMaxime Bizon ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) 257e7300d04SMaxime Bizon 258e7300d04SMaxime Bizon 259e7300d04SMaxime Bizon /************************************************************************* 260e7300d04SMaxime Bizon * _REG relative to RSET_TIMER 261e7300d04SMaxime Bizon *************************************************************************/ 262e7300d04SMaxime Bizon 263e7300d04SMaxime Bizon #define BCM63XX_TIMER_COUNT 4 264e7300d04SMaxime Bizon #define TIMER_T0_ID 0 265e7300d04SMaxime Bizon #define TIMER_T1_ID 1 266e7300d04SMaxime Bizon #define TIMER_T2_ID 2 267e7300d04SMaxime Bizon #define TIMER_WDT_ID 3 268e7300d04SMaxime Bizon 269e7300d04SMaxime Bizon /* Timer irqstat register */ 270e7300d04SMaxime Bizon #define TIMER_IRQSTAT_REG 0 271e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) 272e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) 273e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) 274e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) 275e7300d04SMaxime Bizon #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) 276e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) 277e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) 278e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) 279e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) 280e7300d04SMaxime Bizon 281e7300d04SMaxime Bizon /* Timer control register */ 282e7300d04SMaxime Bizon #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) 283e7300d04SMaxime Bizon #define TIMER_CTL0_REG 0x4 284e7300d04SMaxime Bizon #define TIMER_CTL1_REG 0x8 285e7300d04SMaxime Bizon #define TIMER_CTL2_REG 0xC 286e7300d04SMaxime Bizon #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) 287e7300d04SMaxime Bizon #define TIMER_CTL_MONOTONIC_MASK (1 << 30) 288e7300d04SMaxime Bizon #define TIMER_CTL_ENABLE_MASK (1 << 31) 289e7300d04SMaxime Bizon 290e7300d04SMaxime Bizon 291e7300d04SMaxime Bizon /************************************************************************* 292e7300d04SMaxime Bizon * _REG relative to RSET_WDT 293e7300d04SMaxime Bizon *************************************************************************/ 294e7300d04SMaxime Bizon 295e7300d04SMaxime Bizon /* Watchdog default count register */ 296e7300d04SMaxime Bizon #define WDT_DEFVAL_REG 0x0 297e7300d04SMaxime Bizon 298e7300d04SMaxime Bizon /* Watchdog control register */ 299e7300d04SMaxime Bizon #define WDT_CTL_REG 0x4 300e7300d04SMaxime Bizon 301e7300d04SMaxime Bizon /* Watchdog control register constants */ 302e7300d04SMaxime Bizon #define WDT_START_1 (0xff00) 303e7300d04SMaxime Bizon #define WDT_START_2 (0x00ff) 304e7300d04SMaxime Bizon #define WDT_STOP_1 (0xee00) 305e7300d04SMaxime Bizon #define WDT_STOP_2 (0x00ee) 306e7300d04SMaxime Bizon 307e7300d04SMaxime Bizon /* Watchdog reset length register */ 308e7300d04SMaxime Bizon #define WDT_RSTLEN_REG 0x8 309e7300d04SMaxime Bizon 310e7300d04SMaxime Bizon 311e7300d04SMaxime Bizon /************************************************************************* 312e7300d04SMaxime Bizon * _REG relative to RSET_UARTx 313e7300d04SMaxime Bizon *************************************************************************/ 314e7300d04SMaxime Bizon 315e7300d04SMaxime Bizon /* UART Control Register */ 316e7300d04SMaxime Bizon #define UART_CTL_REG 0x0 317e7300d04SMaxime Bizon #define UART_CTL_RXTMOUTCNT_SHIFT 0 318e7300d04SMaxime Bizon #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 319e7300d04SMaxime Bizon #define UART_CTL_RSTTXDN_SHIFT 5 320e7300d04SMaxime Bizon #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 321e7300d04SMaxime Bizon #define UART_CTL_RSTRXFIFO_SHIFT 6 322e7300d04SMaxime Bizon #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 323e7300d04SMaxime Bizon #define UART_CTL_RSTTXFIFO_SHIFT 7 324e7300d04SMaxime Bizon #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 325e7300d04SMaxime Bizon #define UART_CTL_STOPBITS_SHIFT 8 326e7300d04SMaxime Bizon #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 327e7300d04SMaxime Bizon #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 328e7300d04SMaxime Bizon #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 329e7300d04SMaxime Bizon #define UART_CTL_BITSPERSYM_SHIFT 12 330e7300d04SMaxime Bizon #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 331e7300d04SMaxime Bizon #define UART_CTL_XMITBRK_SHIFT 14 332e7300d04SMaxime Bizon #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 333e7300d04SMaxime Bizon #define UART_CTL_RSVD_SHIFT 15 334e7300d04SMaxime Bizon #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 335e7300d04SMaxime Bizon #define UART_CTL_RXPAREVEN_SHIFT 16 336e7300d04SMaxime Bizon #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 337e7300d04SMaxime Bizon #define UART_CTL_RXPAREN_SHIFT 17 338e7300d04SMaxime Bizon #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 339e7300d04SMaxime Bizon #define UART_CTL_TXPAREVEN_SHIFT 18 340e7300d04SMaxime Bizon #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 341e7300d04SMaxime Bizon #define UART_CTL_TXPAREN_SHIFT 18 342e7300d04SMaxime Bizon #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 343e7300d04SMaxime Bizon #define UART_CTL_LOOPBACK_SHIFT 20 344e7300d04SMaxime Bizon #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 345e7300d04SMaxime Bizon #define UART_CTL_RXEN_SHIFT 21 346e7300d04SMaxime Bizon #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 347e7300d04SMaxime Bizon #define UART_CTL_TXEN_SHIFT 22 348e7300d04SMaxime Bizon #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 349e7300d04SMaxime Bizon #define UART_CTL_BRGEN_SHIFT 23 350e7300d04SMaxime Bizon #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 351e7300d04SMaxime Bizon 352e7300d04SMaxime Bizon /* UART Baudword register */ 353e7300d04SMaxime Bizon #define UART_BAUD_REG 0x4 354e7300d04SMaxime Bizon 355e7300d04SMaxime Bizon /* UART Misc Control register */ 356e7300d04SMaxime Bizon #define UART_MCTL_REG 0x8 357e7300d04SMaxime Bizon #define UART_MCTL_DTR_SHIFT 0 358e7300d04SMaxime Bizon #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 359e7300d04SMaxime Bizon #define UART_MCTL_RTS_SHIFT 1 360e7300d04SMaxime Bizon #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 361e7300d04SMaxime Bizon #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 362e7300d04SMaxime Bizon #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 363e7300d04SMaxime Bizon #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 364e7300d04SMaxime Bizon #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 365e7300d04SMaxime Bizon #define UART_MCTL_RXFIFOFILL_SHIFT 16 366e7300d04SMaxime Bizon #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 367e7300d04SMaxime Bizon #define UART_MCTL_TXFIFOFILL_SHIFT 24 368e7300d04SMaxime Bizon #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 369e7300d04SMaxime Bizon 370e7300d04SMaxime Bizon /* UART External Input Configuration register */ 371e7300d04SMaxime Bizon #define UART_EXTINP_REG 0xc 372e7300d04SMaxime Bizon #define UART_EXTINP_RI_SHIFT 0 373e7300d04SMaxime Bizon #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 374e7300d04SMaxime Bizon #define UART_EXTINP_CTS_SHIFT 1 375e7300d04SMaxime Bizon #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 376e7300d04SMaxime Bizon #define UART_EXTINP_DCD_SHIFT 2 377e7300d04SMaxime Bizon #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 378e7300d04SMaxime Bizon #define UART_EXTINP_DSR_SHIFT 3 379e7300d04SMaxime Bizon #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 380e7300d04SMaxime Bizon #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 381e7300d04SMaxime Bizon #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 382e7300d04SMaxime Bizon #define UART_EXTINP_IR_RI 0 383e7300d04SMaxime Bizon #define UART_EXTINP_IR_CTS 1 384e7300d04SMaxime Bizon #define UART_EXTINP_IR_DCD 2 385e7300d04SMaxime Bizon #define UART_EXTINP_IR_DSR 3 386e7300d04SMaxime Bizon #define UART_EXTINP_RI_NOSENSE_SHIFT 16 387e7300d04SMaxime Bizon #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 388e7300d04SMaxime Bizon #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 389e7300d04SMaxime Bizon #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 390e7300d04SMaxime Bizon #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 391e7300d04SMaxime Bizon #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 392e7300d04SMaxime Bizon #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 393e7300d04SMaxime Bizon #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 394e7300d04SMaxime Bizon 395e7300d04SMaxime Bizon /* UART Interrupt register */ 396e7300d04SMaxime Bizon #define UART_IR_REG 0x10 397e7300d04SMaxime Bizon #define UART_IR_MASK(x) (1 << (x + 16)) 398e7300d04SMaxime Bizon #define UART_IR_STAT(x) (1 << (x)) 399e7300d04SMaxime Bizon #define UART_IR_EXTIP 0 400e7300d04SMaxime Bizon #define UART_IR_TXUNDER 1 401e7300d04SMaxime Bizon #define UART_IR_TXOVER 2 402e7300d04SMaxime Bizon #define UART_IR_TXTRESH 3 403e7300d04SMaxime Bizon #define UART_IR_TXRDLATCH 4 404e7300d04SMaxime Bizon #define UART_IR_TXEMPTY 5 405e7300d04SMaxime Bizon #define UART_IR_RXUNDER 6 406e7300d04SMaxime Bizon #define UART_IR_RXOVER 7 407e7300d04SMaxime Bizon #define UART_IR_RXTIMEOUT 8 408e7300d04SMaxime Bizon #define UART_IR_RXFULL 9 409e7300d04SMaxime Bizon #define UART_IR_RXTHRESH 10 410e7300d04SMaxime Bizon #define UART_IR_RXNOTEMPTY 11 411e7300d04SMaxime Bizon #define UART_IR_RXFRAMEERR 12 412e7300d04SMaxime Bizon #define UART_IR_RXPARERR 13 413e7300d04SMaxime Bizon #define UART_IR_RXBRK 14 414e7300d04SMaxime Bizon #define UART_IR_TXDONE 15 415e7300d04SMaxime Bizon 416e7300d04SMaxime Bizon /* UART Fifo register */ 417e7300d04SMaxime Bizon #define UART_FIFO_REG 0x14 418e7300d04SMaxime Bizon #define UART_FIFO_VALID_SHIFT 0 419e7300d04SMaxime Bizon #define UART_FIFO_VALID_MASK 0xff 420e7300d04SMaxime Bizon #define UART_FIFO_FRAMEERR_SHIFT 8 421e7300d04SMaxime Bizon #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 422e7300d04SMaxime Bizon #define UART_FIFO_PARERR_SHIFT 9 423e7300d04SMaxime Bizon #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 424e7300d04SMaxime Bizon #define UART_FIFO_BRKDET_SHIFT 10 425e7300d04SMaxime Bizon #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 426e7300d04SMaxime Bizon #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 427e7300d04SMaxime Bizon UART_FIFO_PARERR_MASK | \ 428e7300d04SMaxime Bizon UART_FIFO_BRKDET_MASK) 429e7300d04SMaxime Bizon 430e7300d04SMaxime Bizon 431e7300d04SMaxime Bizon /************************************************************************* 432e7300d04SMaxime Bizon * _REG relative to RSET_GPIO 433e7300d04SMaxime Bizon *************************************************************************/ 434e7300d04SMaxime Bizon 435e7300d04SMaxime Bizon /* GPIO registers */ 436e7300d04SMaxime Bizon #define GPIO_CTL_HI_REG 0x0 437e7300d04SMaxime Bizon #define GPIO_CTL_LO_REG 0x4 438e7300d04SMaxime Bizon #define GPIO_DATA_HI_REG 0x8 439e7300d04SMaxime Bizon #define GPIO_DATA_LO_REG 0xC 44092d9ae20SFlorian Fainelli #define GPIO_DATA_LO_REG_6345 0x8 441e7300d04SMaxime Bizon 442e7300d04SMaxime Bizon /* GPIO mux registers and constants */ 443e7300d04SMaxime Bizon #define GPIO_MODE_REG 0x18 444e7300d04SMaxime Bizon 445e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_DIAG 0x00090000 446e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_UTOPIA 0x00080000 447e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 448e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 449e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 450e7300d04SMaxime Bizon #define GPIO_MODE_6348_G3_DIAG 0x00009000 451e7300d04SMaxime Bizon #define GPIO_MODE_6348_G3_UTOPIA 0x00008000 452e7300d04SMaxime Bizon #define GPIO_MODE_6348_G3_EXT_MII 0x00007000 453e7300d04SMaxime Bizon #define GPIO_MODE_6348_G2_DIAG 0x00000900 454e7300d04SMaxime Bizon #define GPIO_MODE_6348_G2_PCI 0x00000500 455e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_DIAG 0x00000090 456e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_UTOPIA 0x00000080 457e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_SPI_UART 0x00000060 458e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 459e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 460e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 461e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 462e7300d04SMaxime Bizon #define GPIO_MODE_6348_G0_DIAG 0x00000009 463e7300d04SMaxime Bizon #define GPIO_MODE_6348_G0_EXT_MII 0x00000007 464e7300d04SMaxime Bizon 465e7300d04SMaxime Bizon #define GPIO_MODE_6358_EXTRACS (1 << 5) 466e7300d04SMaxime Bizon #define GPIO_MODE_6358_UART1 (1 << 6) 467e7300d04SMaxime Bizon #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) 468e7300d04SMaxime Bizon #define GPIO_MODE_6358_SERIAL_LED (1 << 10) 469e7300d04SMaxime Bizon #define GPIO_MODE_6358_UTOPIA (1 << 12) 470e7300d04SMaxime Bizon 47104712f3fSMaxime Bizon #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) 47204712f3fSMaxime Bizon #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) 47304712f3fSMaxime Bizon #define GPIO_MODE_6368_SYS_IRQ (1 << 2) 47404712f3fSMaxime Bizon #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3) 47504712f3fSMaxime Bizon #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4) 47604712f3fSMaxime Bizon #define GPIO_MODE_6368_INET_LED (1 << 5) 47704712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY0_LED (1 << 6) 47804712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY1_LED (1 << 7) 47904712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY2_LED (1 << 8) 48004712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY3_LED (1 << 9) 48104712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10) 48204712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11) 48304712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12) 48404712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13) 48504712f3fSMaxime Bizon #define GPIO_MODE_6368_USBD_LED (1 << 14) 48604712f3fSMaxime Bizon #define GPIO_MODE_6368_NTR_PULSE (1 << 15) 48704712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_REQ1 (1 << 16) 48804712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_GNT1 (1 << 17) 48904712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_INTB (1 << 18) 49004712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_REQ0 (1 << 19) 49104712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_GNT0 (1 << 20) 49204712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22) 49304712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23) 49404712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24) 49504712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25) 49604712f3fSMaxime Bizon #define GPIO_MODE_6368_EBI_CS2 (1 << 26) 49704712f3fSMaxime Bizon #define GPIO_MODE_6368_EBI_CS3 (1 << 27) 49804712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN2 (1 << 28) 49904712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN3 (1 << 29) 50004712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) 50104712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) 50204712f3fSMaxime Bizon 50304712f3fSMaxime Bizon 50404712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_REG 0x38 50504712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_UART2 0x1 50604712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_GPIO 0x0 50704712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_MASK 0x7 50804712f3fSMaxime Bizon /* those bits must be kept as read in gpio basemode register*/ 509e7300d04SMaxime Bizon 510e7300d04SMaxime Bizon /************************************************************************* 511e7300d04SMaxime Bizon * _REG relative to RSET_ENET 512e7300d04SMaxime Bizon *************************************************************************/ 513e7300d04SMaxime Bizon 514e7300d04SMaxime Bizon /* Receiver Configuration register */ 515e7300d04SMaxime Bizon #define ENET_RXCFG_REG 0x0 516e7300d04SMaxime Bizon #define ENET_RXCFG_ALLMCAST_SHIFT 1 517e7300d04SMaxime Bizon #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) 518e7300d04SMaxime Bizon #define ENET_RXCFG_PROMISC_SHIFT 3 519e7300d04SMaxime Bizon #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) 520e7300d04SMaxime Bizon #define ENET_RXCFG_LOOPBACK_SHIFT 4 521e7300d04SMaxime Bizon #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) 522e7300d04SMaxime Bizon #define ENET_RXCFG_ENFLOW_SHIFT 5 523e7300d04SMaxime Bizon #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) 524e7300d04SMaxime Bizon 525e7300d04SMaxime Bizon /* Receive Maximum Length register */ 526e7300d04SMaxime Bizon #define ENET_RXMAXLEN_REG 0x4 527e7300d04SMaxime Bizon #define ENET_RXMAXLEN_SHIFT 0 528e7300d04SMaxime Bizon #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) 529e7300d04SMaxime Bizon 530e7300d04SMaxime Bizon /* Transmit Maximum Length register */ 531e7300d04SMaxime Bizon #define ENET_TXMAXLEN_REG 0x8 532e7300d04SMaxime Bizon #define ENET_TXMAXLEN_SHIFT 0 533e7300d04SMaxime Bizon #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) 534e7300d04SMaxime Bizon 535e7300d04SMaxime Bizon /* MII Status/Control register */ 536e7300d04SMaxime Bizon #define ENET_MIISC_REG 0x10 537e7300d04SMaxime Bizon #define ENET_MIISC_MDCFREQDIV_SHIFT 0 538e7300d04SMaxime Bizon #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) 539e7300d04SMaxime Bizon #define ENET_MIISC_PREAMBLEEN_SHIFT 7 540e7300d04SMaxime Bizon #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) 541e7300d04SMaxime Bizon 542e7300d04SMaxime Bizon /* MII Data register */ 543e7300d04SMaxime Bizon #define ENET_MIIDATA_REG 0x14 544e7300d04SMaxime Bizon #define ENET_MIIDATA_DATA_SHIFT 0 545e7300d04SMaxime Bizon #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) 546e7300d04SMaxime Bizon #define ENET_MIIDATA_TA_SHIFT 16 547e7300d04SMaxime Bizon #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) 548e7300d04SMaxime Bizon #define ENET_MIIDATA_REG_SHIFT 18 549e7300d04SMaxime Bizon #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) 550e7300d04SMaxime Bizon #define ENET_MIIDATA_PHYID_SHIFT 23 551e7300d04SMaxime Bizon #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) 552e7300d04SMaxime Bizon #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) 553e7300d04SMaxime Bizon #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) 554e7300d04SMaxime Bizon 555e7300d04SMaxime Bizon /* Ethernet Interrupt Mask register */ 556e7300d04SMaxime Bizon #define ENET_IRMASK_REG 0x18 557e7300d04SMaxime Bizon 558e7300d04SMaxime Bizon /* Ethernet Interrupt register */ 559e7300d04SMaxime Bizon #define ENET_IR_REG 0x1c 560e7300d04SMaxime Bizon #define ENET_IR_MII (1 << 0) 561e7300d04SMaxime Bizon #define ENET_IR_MIB (1 << 1) 562e7300d04SMaxime Bizon #define ENET_IR_FLOWC (1 << 2) 563e7300d04SMaxime Bizon 564e7300d04SMaxime Bizon /* Ethernet Control register */ 565e7300d04SMaxime Bizon #define ENET_CTL_REG 0x2c 566e7300d04SMaxime Bizon #define ENET_CTL_ENABLE_SHIFT 0 567e7300d04SMaxime Bizon #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) 568e7300d04SMaxime Bizon #define ENET_CTL_DISABLE_SHIFT 1 569e7300d04SMaxime Bizon #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) 570e7300d04SMaxime Bizon #define ENET_CTL_SRESET_SHIFT 2 571e7300d04SMaxime Bizon #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) 572e7300d04SMaxime Bizon #define ENET_CTL_EPHYSEL_SHIFT 3 573e7300d04SMaxime Bizon #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) 574e7300d04SMaxime Bizon 575e7300d04SMaxime Bizon /* Transmit Control register */ 576e7300d04SMaxime Bizon #define ENET_TXCTL_REG 0x30 577e7300d04SMaxime Bizon #define ENET_TXCTL_FD_SHIFT 0 578e7300d04SMaxime Bizon #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) 579e7300d04SMaxime Bizon 580e7300d04SMaxime Bizon /* Transmit Watermask register */ 581e7300d04SMaxime Bizon #define ENET_TXWMARK_REG 0x34 582e7300d04SMaxime Bizon #define ENET_TXWMARK_WM_SHIFT 0 583e7300d04SMaxime Bizon #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) 584e7300d04SMaxime Bizon 585e7300d04SMaxime Bizon /* MIB Control register */ 586e7300d04SMaxime Bizon #define ENET_MIBCTL_REG 0x38 587e7300d04SMaxime Bizon #define ENET_MIBCTL_RDCLEAR_SHIFT 0 588e7300d04SMaxime Bizon #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) 589e7300d04SMaxime Bizon 590e7300d04SMaxime Bizon /* Perfect Match Data Low register */ 591e7300d04SMaxime Bizon #define ENET_PML_REG(x) (0x58 + (x) * 8) 592e7300d04SMaxime Bizon #define ENET_PMH_REG(x) (0x5c + (x) * 8) 593e7300d04SMaxime Bizon #define ENET_PMH_DATAVALID_SHIFT 16 594e7300d04SMaxime Bizon #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) 595e7300d04SMaxime Bizon 596e7300d04SMaxime Bizon /* MIB register */ 597e7300d04SMaxime Bizon #define ENET_MIB_REG(x) (0x200 + (x) * 4) 598e7300d04SMaxime Bizon #define ENET_MIB_REG_COUNT 55 599e7300d04SMaxime Bizon 600e7300d04SMaxime Bizon 601e7300d04SMaxime Bizon /************************************************************************* 602e7300d04SMaxime Bizon * _REG relative to RSET_ENETDMA 603e7300d04SMaxime Bizon *************************************************************************/ 604e7300d04SMaxime Bizon 605e7300d04SMaxime Bizon /* Controller Configuration Register */ 606e7300d04SMaxime Bizon #define ENETDMA_CFG_REG (0x0) 607e7300d04SMaxime Bizon #define ENETDMA_CFG_EN_SHIFT 0 608e7300d04SMaxime Bizon #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) 609e7300d04SMaxime Bizon #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) 610e7300d04SMaxime Bizon 611e7300d04SMaxime Bizon /* Flow Control Descriptor Low Threshold register */ 612e7300d04SMaxime Bizon #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) 613e7300d04SMaxime Bizon 614e7300d04SMaxime Bizon /* Flow Control Descriptor High Threshold register */ 615e7300d04SMaxime Bizon #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) 616e7300d04SMaxime Bizon 617e7300d04SMaxime Bizon /* Flow Control Descriptor Buffer Alloca Threshold register */ 618e7300d04SMaxime Bizon #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) 619e7300d04SMaxime Bizon #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 620e7300d04SMaxime Bizon #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) 621e7300d04SMaxime Bizon 622e7300d04SMaxime Bizon /* Channel Configuration register */ 623e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) 624e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_EN_SHIFT 0 625e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) 626e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 627e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) 628e7300d04SMaxime Bizon 629e7300d04SMaxime Bizon /* Interrupt Control/Status register */ 630e7300d04SMaxime Bizon #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) 631e7300d04SMaxime Bizon #define ENETDMA_IR_BUFDONE_MASK (1 << 0) 632e7300d04SMaxime Bizon #define ENETDMA_IR_PKTDONE_MASK (1 << 1) 633e7300d04SMaxime Bizon #define ENETDMA_IR_NOTOWNER_MASK (1 << 2) 634e7300d04SMaxime Bizon 635e7300d04SMaxime Bizon /* Interrupt Mask register */ 636e7300d04SMaxime Bizon #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) 637e7300d04SMaxime Bizon 638e7300d04SMaxime Bizon /* Maximum Burst Length */ 639e7300d04SMaxime Bizon #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) 640e7300d04SMaxime Bizon 641e7300d04SMaxime Bizon /* Ring Start Address register */ 642e7300d04SMaxime Bizon #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) 643e7300d04SMaxime Bizon 644e7300d04SMaxime Bizon /* State Ram Word 2 */ 645e7300d04SMaxime Bizon #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) 646e7300d04SMaxime Bizon 647e7300d04SMaxime Bizon /* State Ram Word 3 */ 648e7300d04SMaxime Bizon #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) 649e7300d04SMaxime Bizon 650e7300d04SMaxime Bizon /* State Ram Word 4 */ 651e7300d04SMaxime Bizon #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) 652e7300d04SMaxime Bizon 653e7300d04SMaxime Bizon 654e7300d04SMaxime Bizon /************************************************************************* 655d430b6c5SMaxime Bizon * _REG relative to RSET_ENETDMAC 656d430b6c5SMaxime Bizon *************************************************************************/ 657d430b6c5SMaxime Bizon 658d430b6c5SMaxime Bizon /* Channel Configuration register */ 659d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) 660d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_EN_SHIFT 0 661d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) 662d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 663d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) 664d430b6c5SMaxime Bizon 665d430b6c5SMaxime Bizon /* Interrupt Control/Status register */ 666d430b6c5SMaxime Bizon #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) 667d430b6c5SMaxime Bizon #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) 668d430b6c5SMaxime Bizon #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) 669d430b6c5SMaxime Bizon #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) 670d430b6c5SMaxime Bizon 671d430b6c5SMaxime Bizon /* Interrupt Mask register */ 672d430b6c5SMaxime Bizon #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) 673d430b6c5SMaxime Bizon 674d430b6c5SMaxime Bizon /* Maximum Burst Length */ 675d430b6c5SMaxime Bizon #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) 676d430b6c5SMaxime Bizon 677d430b6c5SMaxime Bizon 678d430b6c5SMaxime Bizon /************************************************************************* 679d430b6c5SMaxime Bizon * _REG relative to RSET_ENETDMAS 680d430b6c5SMaxime Bizon *************************************************************************/ 681d430b6c5SMaxime Bizon 682d430b6c5SMaxime Bizon /* Ring Start Address register */ 683d430b6c5SMaxime Bizon #define ENETDMAS_RSTART_REG(x) ((x) * 0x10) 684d430b6c5SMaxime Bizon 685d430b6c5SMaxime Bizon /* State Ram Word 2 */ 686d430b6c5SMaxime Bizon #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) 687d430b6c5SMaxime Bizon 688d430b6c5SMaxime Bizon /* State Ram Word 3 */ 689d430b6c5SMaxime Bizon #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) 690d430b6c5SMaxime Bizon 691d430b6c5SMaxime Bizon /* State Ram Word 4 */ 692d430b6c5SMaxime Bizon #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) 693d430b6c5SMaxime Bizon 694d430b6c5SMaxime Bizon 695d430b6c5SMaxime Bizon /************************************************************************* 696d430b6c5SMaxime Bizon * _REG relative to RSET_ENETSW 697d430b6c5SMaxime Bizon *************************************************************************/ 698d430b6c5SMaxime Bizon 699d430b6c5SMaxime Bizon /* MIB register */ 700d430b6c5SMaxime Bizon #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) 701d430b6c5SMaxime Bizon #define ENETSW_MIB_REG_COUNT 47 702d430b6c5SMaxime Bizon 703d430b6c5SMaxime Bizon 704d430b6c5SMaxime Bizon /************************************************************************* 705e7300d04SMaxime Bizon * _REG relative to RSET_OHCI_PRIV 706e7300d04SMaxime Bizon *************************************************************************/ 707e7300d04SMaxime Bizon 708e7300d04SMaxime Bizon #define OHCI_PRIV_REG 0x0 709e7300d04SMaxime Bizon #define OHCI_PRIV_PORT1_HOST_SHIFT 0 710e7300d04SMaxime Bizon #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) 711e7300d04SMaxime Bizon #define OHCI_PRIV_REG_SWAP_SHIFT 3 712e7300d04SMaxime Bizon #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) 713e7300d04SMaxime Bizon 714e7300d04SMaxime Bizon 715e7300d04SMaxime Bizon /************************************************************************* 716e7300d04SMaxime Bizon * _REG relative to RSET_USBH_PRIV 717e7300d04SMaxime Bizon *************************************************************************/ 718e7300d04SMaxime Bizon 71904712f3fSMaxime Bizon #define USBH_PRIV_SWAP_6358_REG 0x0 72004712f3fSMaxime Bizon #define USBH_PRIV_SWAP_6368_REG 0x1c 72104712f3fSMaxime Bizon 722e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 723e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 724e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 725e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) 726e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 727e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) 728e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 729e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 730e7300d04SMaxime Bizon 73104712f3fSMaxime Bizon #define USBH_PRIV_TEST_6358_REG 0x24 73204712f3fSMaxime Bizon #define USBH_PRIV_TEST_6368_REG 0x14 73304712f3fSMaxime Bizon 73404712f3fSMaxime Bizon #define USBH_PRIV_SETUP_6368_REG 0x28 73504712f3fSMaxime Bizon #define USBH_PRIV_SETUP_IOC_SHIFT 4 73604712f3fSMaxime Bizon #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) 73704712f3fSMaxime Bizon 738e7300d04SMaxime Bizon 739e7300d04SMaxime Bizon 740e7300d04SMaxime Bizon /************************************************************************* 741e7300d04SMaxime Bizon * _REG relative to RSET_MPI 742e7300d04SMaxime Bizon *************************************************************************/ 743e7300d04SMaxime Bizon 744e7300d04SMaxime Bizon /* well known (hard wired) chip select */ 745e7300d04SMaxime Bizon #define MPI_CS_PCMCIA_COMMON 4 746e7300d04SMaxime Bizon #define MPI_CS_PCMCIA_ATTR 5 747e7300d04SMaxime Bizon #define MPI_CS_PCMCIA_IO 6 748e7300d04SMaxime Bizon 749e7300d04SMaxime Bizon /* Chip select base register */ 750e7300d04SMaxime Bizon #define MPI_CSBASE_REG(x) (0x0 + (x) * 8) 751e7300d04SMaxime Bizon #define MPI_CSBASE_BASE_SHIFT 13 752e7300d04SMaxime Bizon #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) 753e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_SHIFT 0 754e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) 755e7300d04SMaxime Bizon 756e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_8K 0 757e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_16K 1 758e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_32K 2 759e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_64K 3 760e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_128K 4 761e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_256K 5 762e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_512K 6 763e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_1M 7 764e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_2M 8 765e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_4M 9 766e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_8M 10 767e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_16M 11 768e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_32M 12 769e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_64M 13 770e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_128M 14 771e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_256M 15 772e7300d04SMaxime Bizon 773e7300d04SMaxime Bizon /* Chip select control register */ 774e7300d04SMaxime Bizon #define MPI_CSCTL_REG(x) (0x4 + (x) * 8) 775e7300d04SMaxime Bizon #define MPI_CSCTL_ENABLE_MASK (1 << 0) 776e7300d04SMaxime Bizon #define MPI_CSCTL_WAIT_SHIFT 1 777e7300d04SMaxime Bizon #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) 778e7300d04SMaxime Bizon #define MPI_CSCTL_DATA16_MASK (1 << 4) 779e7300d04SMaxime Bizon #define MPI_CSCTL_SYNCMODE_MASK (1 << 7) 780e7300d04SMaxime Bizon #define MPI_CSCTL_TSIZE_MASK (1 << 8) 781e7300d04SMaxime Bizon #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) 782e7300d04SMaxime Bizon #define MPI_CSCTL_SETUP_SHIFT 16 783e7300d04SMaxime Bizon #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) 784e7300d04SMaxime Bizon #define MPI_CSCTL_HOLD_SHIFT 20 785e7300d04SMaxime Bizon #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) 786e7300d04SMaxime Bizon 787e7300d04SMaxime Bizon /* PCI registers */ 788e7300d04SMaxime Bizon #define MPI_SP0_RANGE_REG 0x100 789e7300d04SMaxime Bizon #define MPI_SP0_REMAP_REG 0x104 790e7300d04SMaxime Bizon #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) 791e7300d04SMaxime Bizon #define MPI_SP1_RANGE_REG 0x10C 792e7300d04SMaxime Bizon #define MPI_SP1_REMAP_REG 0x110 793e7300d04SMaxime Bizon #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) 794e7300d04SMaxime Bizon 795e7300d04SMaxime Bizon #define MPI_L2PCFG_REG 0x11C 796e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_TYPE_SHIFT 0 797e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) 798e7300d04SMaxime Bizon #define MPI_L2PCFG_REG_SHIFT 2 799e7300d04SMaxime Bizon #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) 800e7300d04SMaxime Bizon #define MPI_L2PCFG_FUNC_SHIFT 8 801e7300d04SMaxime Bizon #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) 802e7300d04SMaxime Bizon #define MPI_L2PCFG_DEVNUM_SHIFT 11 803e7300d04SMaxime Bizon #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) 804e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) 805e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) 806e7300d04SMaxime Bizon 807e7300d04SMaxime Bizon #define MPI_L2PMEMRANGE1_REG 0x120 808e7300d04SMaxime Bizon #define MPI_L2PMEMBASE1_REG 0x124 809e7300d04SMaxime Bizon #define MPI_L2PMEMREMAP1_REG 0x128 810e7300d04SMaxime Bizon #define MPI_L2PMEMRANGE2_REG 0x12C 811e7300d04SMaxime Bizon #define MPI_L2PMEMBASE2_REG 0x130 812e7300d04SMaxime Bizon #define MPI_L2PMEMREMAP2_REG 0x134 813e7300d04SMaxime Bizon #define MPI_L2PIORANGE_REG 0x138 814e7300d04SMaxime Bizon #define MPI_L2PIOBASE_REG 0x13C 815e7300d04SMaxime Bizon #define MPI_L2PIOREMAP_REG 0x140 816e7300d04SMaxime Bizon #define MPI_L2P_BASE_MASK (0xffff8000) 817e7300d04SMaxime Bizon #define MPI_L2PREMAP_ENABLED_MASK (1 << 0) 818e7300d04SMaxime Bizon #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) 819e7300d04SMaxime Bizon 820e7300d04SMaxime Bizon #define MPI_PCIMODESEL_REG 0x144 821e7300d04SMaxime Bizon #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) 822e7300d04SMaxime Bizon #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) 823e7300d04SMaxime Bizon #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) 824e7300d04SMaxime Bizon #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 825e7300d04SMaxime Bizon #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) 826e7300d04SMaxime Bizon 827e7300d04SMaxime Bizon #define MPI_LOCBUSCTL_REG 0x14C 828e7300d04SMaxime Bizon #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) 829e7300d04SMaxime Bizon #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) 830e7300d04SMaxime Bizon 831e7300d04SMaxime Bizon #define MPI_LOCINT_REG 0x150 832e7300d04SMaxime Bizon #define MPI_LOCINT_MASK(x) (1 << (x + 16)) 833e7300d04SMaxime Bizon #define MPI_LOCINT_STAT(x) (1 << (x)) 834e7300d04SMaxime Bizon #define MPI_LOCINT_DIR_FAILED 6 835e7300d04SMaxime Bizon #define MPI_LOCINT_EXT_PCI_INT 7 836e7300d04SMaxime Bizon #define MPI_LOCINT_SERR 8 837e7300d04SMaxime Bizon #define MPI_LOCINT_CSERR 9 838e7300d04SMaxime Bizon 839e7300d04SMaxime Bizon #define MPI_PCICFGCTL_REG 0x178 840e7300d04SMaxime Bizon #define MPI_PCICFGCTL_CFGADDR_SHIFT 2 841e7300d04SMaxime Bizon #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) 842e7300d04SMaxime Bizon #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) 843e7300d04SMaxime Bizon 844e7300d04SMaxime Bizon #define MPI_PCICFGDATA_REG 0x17C 845e7300d04SMaxime Bizon 846e7300d04SMaxime Bizon /* PCI host bridge custom register */ 847e7300d04SMaxime Bizon #define BCMPCI_REG_TIMERS 0x40 848e7300d04SMaxime Bizon #define REG_TIMER_TRDY_SHIFT 0 849e7300d04SMaxime Bizon #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) 850e7300d04SMaxime Bizon #define REG_TIMER_RETRY_SHIFT 8 851e7300d04SMaxime Bizon #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) 852e7300d04SMaxime Bizon 853e7300d04SMaxime Bizon 854e7300d04SMaxime Bizon /************************************************************************* 855e7300d04SMaxime Bizon * _REG relative to RSET_PCMCIA 856e7300d04SMaxime Bizon *************************************************************************/ 857e7300d04SMaxime Bizon 858e7300d04SMaxime Bizon #define PCMCIA_C1_REG 0x0 859e7300d04SMaxime Bizon #define PCMCIA_C1_CD1_MASK (1 << 0) 860e7300d04SMaxime Bizon #define PCMCIA_C1_CD2_MASK (1 << 1) 861e7300d04SMaxime Bizon #define PCMCIA_C1_VS1_MASK (1 << 2) 862e7300d04SMaxime Bizon #define PCMCIA_C1_VS2_MASK (1 << 3) 863e7300d04SMaxime Bizon #define PCMCIA_C1_VS1OE_MASK (1 << 6) 864e7300d04SMaxime Bizon #define PCMCIA_C1_VS2OE_MASK (1 << 7) 865e7300d04SMaxime Bizon #define PCMCIA_C1_CBIDSEL_SHIFT (8) 866e7300d04SMaxime Bizon #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) 867e7300d04SMaxime Bizon #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) 868e7300d04SMaxime Bizon #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) 869e7300d04SMaxime Bizon #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) 870e7300d04SMaxime Bizon #define PCMCIA_C1_RESET_MASK (1 << 18) 871e7300d04SMaxime Bizon 872e7300d04SMaxime Bizon #define PCMCIA_C2_REG 0x8 873e7300d04SMaxime Bizon #define PCMCIA_C2_DATA16_MASK (1 << 0) 874e7300d04SMaxime Bizon #define PCMCIA_C2_BYTESWAP_MASK (1 << 1) 875e7300d04SMaxime Bizon #define PCMCIA_C2_RWCOUNT_SHIFT 2 876e7300d04SMaxime Bizon #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) 877e7300d04SMaxime Bizon #define PCMCIA_C2_INACTIVE_SHIFT 8 878e7300d04SMaxime Bizon #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) 879e7300d04SMaxime Bizon #define PCMCIA_C2_SETUP_SHIFT 16 880e7300d04SMaxime Bizon #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) 881e7300d04SMaxime Bizon #define PCMCIA_C2_HOLD_SHIFT 24 882e7300d04SMaxime Bizon #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) 883e7300d04SMaxime Bizon 884e7300d04SMaxime Bizon 885e7300d04SMaxime Bizon /************************************************************************* 886e7300d04SMaxime Bizon * _REG relative to RSET_SDRAM 887e7300d04SMaxime Bizon *************************************************************************/ 888e7300d04SMaxime Bizon 889e7300d04SMaxime Bizon #define SDRAM_CFG_REG 0x0 890e7300d04SMaxime Bizon #define SDRAM_CFG_ROW_SHIFT 4 891e7300d04SMaxime Bizon #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) 892e7300d04SMaxime Bizon #define SDRAM_CFG_COL_SHIFT 6 893e7300d04SMaxime Bizon #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) 894e7300d04SMaxime Bizon #define SDRAM_CFG_32B_SHIFT 10 895e7300d04SMaxime Bizon #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) 896e7300d04SMaxime Bizon #define SDRAM_CFG_BANK_SHIFT 13 897e7300d04SMaxime Bizon #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 898e7300d04SMaxime Bizon 899d61fcfe2SFlorian Fainelli #define SDRAM_MBASE_REG 0xc 900d61fcfe2SFlorian Fainelli 901e7300d04SMaxime Bizon #define SDRAM_PRIO_REG 0x2C 902e7300d04SMaxime Bizon #define SDRAM_PRIO_MIPS_SHIFT 29 903e7300d04SMaxime Bizon #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 904e7300d04SMaxime Bizon #define SDRAM_PRIO_ADSL_SHIFT 30 905e7300d04SMaxime Bizon #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) 906e7300d04SMaxime Bizon #define SDRAM_PRIO_EN_SHIFT 31 907e7300d04SMaxime Bizon #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) 908e7300d04SMaxime Bizon 909e7300d04SMaxime Bizon 910e7300d04SMaxime Bizon /************************************************************************* 911e7300d04SMaxime Bizon * _REG relative to RSET_MEMC 912e7300d04SMaxime Bizon *************************************************************************/ 913e7300d04SMaxime Bizon 914e7300d04SMaxime Bizon #define MEMC_CFG_REG 0x4 915e7300d04SMaxime Bizon #define MEMC_CFG_32B_SHIFT 1 916e7300d04SMaxime Bizon #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) 917e7300d04SMaxime Bizon #define MEMC_CFG_COL_SHIFT 3 918e7300d04SMaxime Bizon #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) 919e7300d04SMaxime Bizon #define MEMC_CFG_ROW_SHIFT 6 920e7300d04SMaxime Bizon #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) 921e7300d04SMaxime Bizon 922e7300d04SMaxime Bizon 923e7300d04SMaxime Bizon /************************************************************************* 924e7300d04SMaxime Bizon * _REG relative to RSET_DDR 925e7300d04SMaxime Bizon *************************************************************************/ 926e7300d04SMaxime Bizon 927e7300d04SMaxime Bizon #define DDR_DMIPSPLLCFG_REG 0x18 928e7300d04SMaxime Bizon #define DMIPSPLLCFG_M1_SHIFT 0 929e7300d04SMaxime Bizon #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 930e7300d04SMaxime Bizon #define DMIPSPLLCFG_N1_SHIFT 23 931e7300d04SMaxime Bizon #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) 932e7300d04SMaxime Bizon #define DMIPSPLLCFG_N2_SHIFT 29 933e7300d04SMaxime Bizon #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 934e7300d04SMaxime Bizon 93504712f3fSMaxime Bizon #define DDR_DMIPSPLLCFG_6368_REG 0x20 93604712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P1_SHIFT 0 93704712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) 93804712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P2_SHIFT 4 93904712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) 94004712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 94104712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) 94204712f3fSMaxime Bizon 94304712f3fSMaxime Bizon #define DDR_DMIPSPLLDIV_6368_REG 0x24 94404712f3fSMaxime Bizon #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 94504712f3fSMaxime Bizon #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) 94604712f3fSMaxime Bizon 94704712f3fSMaxime Bizon 948d430b6c5SMaxime Bizon /************************************************************************* 949d430b6c5SMaxime Bizon * _REG relative to RSET_M2M 950d430b6c5SMaxime Bizon *************************************************************************/ 951d430b6c5SMaxime Bizon 952d430b6c5SMaxime Bizon #define M2M_RX 0 953d430b6c5SMaxime Bizon #define M2M_TX 1 954d430b6c5SMaxime Bizon 955d430b6c5SMaxime Bizon #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) 956d430b6c5SMaxime Bizon #define M2M_DST_REG(x) ((x) * 0x40 + 0x04) 957d430b6c5SMaxime Bizon #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) 958d430b6c5SMaxime Bizon 959d430b6c5SMaxime Bizon #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) 960d430b6c5SMaxime Bizon #define M2M_CTRL_ENABLE_MASK (1 << 0) 961d430b6c5SMaxime Bizon #define M2M_CTRL_IRQEN_MASK (1 << 1) 962d430b6c5SMaxime Bizon #define M2M_CTRL_ERROR_CLR_MASK (1 << 6) 963d430b6c5SMaxime Bizon #define M2M_CTRL_DONE_CLR_MASK (1 << 7) 964d430b6c5SMaxime Bizon #define M2M_CTRL_NOINC_MASK (1 << 8) 965d430b6c5SMaxime Bizon #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) 966d430b6c5SMaxime Bizon #define M2M_CTRL_SWAPBYTE_MASK (1 << 10) 967d430b6c5SMaxime Bizon #define M2M_CTRL_ENDIAN_MASK (1 << 11) 968d430b6c5SMaxime Bizon 969d430b6c5SMaxime Bizon #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) 970d430b6c5SMaxime Bizon #define M2M_STAT_DONE (1 << 0) 971d430b6c5SMaxime Bizon #define M2M_STAT_ERROR (1 << 1) 972d430b6c5SMaxime Bizon 973d430b6c5SMaxime Bizon #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) 974d430b6c5SMaxime Bizon #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) 975d430b6c5SMaxime Bizon 976e7300d04SMaxime Bizon #endif /* BCM63XX_REGS_H_ */ 977