1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2e7300d04SMaxime Bizon #ifndef BCM63XX_REGS_H_ 3e7300d04SMaxime Bizon #define BCM63XX_REGS_H_ 4e7300d04SMaxime Bizon 5e7300d04SMaxime Bizon /************************************************************************* 6e7300d04SMaxime Bizon * _REG relative to RSET_PERF 7e7300d04SMaxime Bizon *************************************************************************/ 8e7300d04SMaxime Bizon 9e7300d04SMaxime Bizon /* Chip Identifier / Revision register */ 10e7300d04SMaxime Bizon #define PERF_REV_REG 0x0 11e7300d04SMaxime Bizon #define REV_CHIPID_SHIFT 16 12e7300d04SMaxime Bizon #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 13e7300d04SMaxime Bizon #define REV_REVID_SHIFT 0 146605428cSJonas Gorski #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) 15e7300d04SMaxime Bizon 16e7300d04SMaxime Bizon /* Clock Control register */ 17e7300d04SMaxime Bizon #define PERF_CKCTL_REG 0x4 18e7300d04SMaxime Bizon 197b933421SFlorian Fainelli #define CKCTL_3368_MAC_EN (1 << 3) 207b933421SFlorian Fainelli #define CKCTL_3368_TC_EN (1 << 5) 217b933421SFlorian Fainelli #define CKCTL_3368_US_TOP_EN (1 << 6) 227b933421SFlorian Fainelli #define CKCTL_3368_DS_TOP_EN (1 << 7) 237b933421SFlorian Fainelli #define CKCTL_3368_APM_EN (1 << 8) 247b933421SFlorian Fainelli #define CKCTL_3368_SPI_EN (1 << 9) 257b933421SFlorian Fainelli #define CKCTL_3368_USBS_EN (1 << 10) 267b933421SFlorian Fainelli #define CKCTL_3368_BMU_EN (1 << 11) 277b933421SFlorian Fainelli #define CKCTL_3368_PCM_EN (1 << 12) 287b933421SFlorian Fainelli #define CKCTL_3368_NTP_EN (1 << 13) 297b933421SFlorian Fainelli #define CKCTL_3368_ACP_B_EN (1 << 14) 307b933421SFlorian Fainelli #define CKCTL_3368_ACP_A_EN (1 << 15) 317b933421SFlorian Fainelli #define CKCTL_3368_EMUSB_EN (1 << 17) 327b933421SFlorian Fainelli #define CKCTL_3368_ENET0_EN (1 << 18) 337b933421SFlorian Fainelli #define CKCTL_3368_ENET1_EN (1 << 19) 347b933421SFlorian Fainelli #define CKCTL_3368_USBU_EN (1 << 20) 357b933421SFlorian Fainelli #define CKCTL_3368_EPHY_EN (1 << 21) 367b933421SFlorian Fainelli 377b933421SFlorian Fainelli #define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \ 387b933421SFlorian Fainelli CKCTL_3368_TC_EN | \ 397b933421SFlorian Fainelli CKCTL_3368_US_TOP_EN | \ 407b933421SFlorian Fainelli CKCTL_3368_DS_TOP_EN | \ 417b933421SFlorian Fainelli CKCTL_3368_APM_EN | \ 427b933421SFlorian Fainelli CKCTL_3368_SPI_EN | \ 437b933421SFlorian Fainelli CKCTL_3368_USBS_EN | \ 447b933421SFlorian Fainelli CKCTL_3368_BMU_EN | \ 457b933421SFlorian Fainelli CKCTL_3368_PCM_EN | \ 467b933421SFlorian Fainelli CKCTL_3368_NTP_EN | \ 477b933421SFlorian Fainelli CKCTL_3368_ACP_B_EN | \ 487b933421SFlorian Fainelli CKCTL_3368_ACP_A_EN | \ 497b933421SFlorian Fainelli CKCTL_3368_EMUSB_EN | \ 507b933421SFlorian Fainelli CKCTL_3368_USBU_EN) 517b933421SFlorian Fainelli 52e5766aeaSJonas Gorski #define CKCTL_6328_PHYMIPS_EN (1 << 0) 53e5766aeaSJonas Gorski #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) 54e5766aeaSJonas Gorski #define CKCTL_6328_ADSL_AFE_EN (1 << 2) 55e5766aeaSJonas Gorski #define CKCTL_6328_ADSL_EN (1 << 3) 56e5766aeaSJonas Gorski #define CKCTL_6328_MIPS_EN (1 << 4) 57e5766aeaSJonas Gorski #define CKCTL_6328_SAR_EN (1 << 5) 58e5766aeaSJonas Gorski #define CKCTL_6328_PCM_EN (1 << 6) 59e5766aeaSJonas Gorski #define CKCTL_6328_USBD_EN (1 << 7) 60e5766aeaSJonas Gorski #define CKCTL_6328_USBH_EN (1 << 8) 61e5766aeaSJonas Gorski #define CKCTL_6328_HSSPI_EN (1 << 9) 62e5766aeaSJonas Gorski #define CKCTL_6328_PCIE_EN (1 << 10) 63e5766aeaSJonas Gorski #define CKCTL_6328_ROBOSW_EN (1 << 11) 64e5766aeaSJonas Gorski 65e5766aeaSJonas Gorski #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \ 66e5766aeaSJonas Gorski CKCTL_6328_ADSL_QPROC_EN | \ 67e5766aeaSJonas Gorski CKCTL_6328_ADSL_AFE_EN | \ 68e5766aeaSJonas Gorski CKCTL_6328_ADSL_EN | \ 69e5766aeaSJonas Gorski CKCTL_6328_SAR_EN | \ 70e5766aeaSJonas Gorski CKCTL_6328_PCM_EN | \ 71e5766aeaSJonas Gorski CKCTL_6328_USBD_EN | \ 72e5766aeaSJonas Gorski CKCTL_6328_USBH_EN | \ 73e5766aeaSJonas Gorski CKCTL_6328_ROBOSW_EN | \ 74e5766aeaSJonas Gorski CKCTL_6328_PCIE_EN) 75e5766aeaSJonas Gorski 76e7300d04SMaxime Bizon #define CKCTL_6338_ADSLPHY_EN (1 << 0) 77e7300d04SMaxime Bizon #define CKCTL_6338_MPI_EN (1 << 1) 78e7300d04SMaxime Bizon #define CKCTL_6338_DRAM_EN (1 << 2) 79e7300d04SMaxime Bizon #define CKCTL_6338_ENET_EN (1 << 4) 80e7300d04SMaxime Bizon #define CKCTL_6338_USBS_EN (1 << 4) 81e7300d04SMaxime Bizon #define CKCTL_6338_SAR_EN (1 << 5) 82e7300d04SMaxime Bizon #define CKCTL_6338_SPI_EN (1 << 9) 83e7300d04SMaxime Bizon 84e7300d04SMaxime Bizon #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ 85e7300d04SMaxime Bizon CKCTL_6338_MPI_EN | \ 86e7300d04SMaxime Bizon CKCTL_6338_ENET_EN | \ 87e7300d04SMaxime Bizon CKCTL_6338_SAR_EN | \ 88e7300d04SMaxime Bizon CKCTL_6338_SPI_EN) 89e7300d04SMaxime Bizon 90e59b008eSFlorian Fainelli /* BCM6345 clock bits are shifted by 16 on the left, because of the test 91e59b008eSFlorian Fainelli * control register which is 16-bits wide. That way we do not have any 92e59b008eSFlorian Fainelli * specific BCM6345 code for handling clocks, and writing 0 to the test 93e59b008eSFlorian Fainelli * control register is fine. 94e59b008eSFlorian Fainelli */ 95e59b008eSFlorian Fainelli #define CKCTL_6345_CPU_EN (1 << 16) 96e59b008eSFlorian Fainelli #define CKCTL_6345_BUS_EN (1 << 17) 97e59b008eSFlorian Fainelli #define CKCTL_6345_EBI_EN (1 << 18) 98e59b008eSFlorian Fainelli #define CKCTL_6345_UART_EN (1 << 19) 99e59b008eSFlorian Fainelli #define CKCTL_6345_ADSLPHY_EN (1 << 20) 100e59b008eSFlorian Fainelli #define CKCTL_6345_ENET_EN (1 << 23) 101e59b008eSFlorian Fainelli #define CKCTL_6345_USBH_EN (1 << 24) 102e7300d04SMaxime Bizon 103e7300d04SMaxime Bizon #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 104e7300d04SMaxime Bizon CKCTL_6345_USBH_EN | \ 105e7300d04SMaxime Bizon CKCTL_6345_ADSLPHY_EN) 106e7300d04SMaxime Bizon 107e7300d04SMaxime Bizon #define CKCTL_6348_ADSLPHY_EN (1 << 0) 108e7300d04SMaxime Bizon #define CKCTL_6348_MPI_EN (1 << 1) 109e7300d04SMaxime Bizon #define CKCTL_6348_SDRAM_EN (1 << 2) 110e7300d04SMaxime Bizon #define CKCTL_6348_M2M_EN (1 << 3) 111e7300d04SMaxime Bizon #define CKCTL_6348_ENET_EN (1 << 4) 112e7300d04SMaxime Bizon #define CKCTL_6348_SAR_EN (1 << 5) 113e7300d04SMaxime Bizon #define CKCTL_6348_USBS_EN (1 << 6) 114e7300d04SMaxime Bizon #define CKCTL_6348_USBH_EN (1 << 8) 115e7300d04SMaxime Bizon #define CKCTL_6348_SPI_EN (1 << 9) 116e7300d04SMaxime Bizon 117e7300d04SMaxime Bizon #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ 118e7300d04SMaxime Bizon CKCTL_6348_M2M_EN | \ 119e7300d04SMaxime Bizon CKCTL_6348_ENET_EN | \ 120e7300d04SMaxime Bizon CKCTL_6348_SAR_EN | \ 121e7300d04SMaxime Bizon CKCTL_6348_USBS_EN | \ 122e7300d04SMaxime Bizon CKCTL_6348_USBH_EN | \ 123e7300d04SMaxime Bizon CKCTL_6348_SPI_EN) 124e7300d04SMaxime Bizon 125e7300d04SMaxime Bizon #define CKCTL_6358_ENET_EN (1 << 4) 126e7300d04SMaxime Bizon #define CKCTL_6358_ADSLPHY_EN (1 << 5) 127e7300d04SMaxime Bizon #define CKCTL_6358_PCM_EN (1 << 8) 128e7300d04SMaxime Bizon #define CKCTL_6358_SPI_EN (1 << 9) 129e7300d04SMaxime Bizon #define CKCTL_6358_USBS_EN (1 << 10) 130e7300d04SMaxime Bizon #define CKCTL_6358_SAR_EN (1 << 11) 131e7300d04SMaxime Bizon #define CKCTL_6358_EMUSB_EN (1 << 17) 132e7300d04SMaxime Bizon #define CKCTL_6358_ENET0_EN (1 << 18) 133e7300d04SMaxime Bizon #define CKCTL_6358_ENET1_EN (1 << 19) 134e7300d04SMaxime Bizon #define CKCTL_6358_USBSU_EN (1 << 20) 135e7300d04SMaxime Bizon #define CKCTL_6358_EPHY_EN (1 << 21) 136e7300d04SMaxime Bizon 137e7300d04SMaxime Bizon #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ 138e7300d04SMaxime Bizon CKCTL_6358_ADSLPHY_EN | \ 139e7300d04SMaxime Bizon CKCTL_6358_PCM_EN | \ 140e7300d04SMaxime Bizon CKCTL_6358_SPI_EN | \ 141e7300d04SMaxime Bizon CKCTL_6358_USBS_EN | \ 142e7300d04SMaxime Bizon CKCTL_6358_SAR_EN | \ 143e7300d04SMaxime Bizon CKCTL_6358_EMUSB_EN | \ 144e7300d04SMaxime Bizon CKCTL_6358_ENET0_EN | \ 145e7300d04SMaxime Bizon CKCTL_6358_ENET1_EN | \ 146e7300d04SMaxime Bizon CKCTL_6358_USBSU_EN | \ 147e7300d04SMaxime Bizon CKCTL_6358_EPHY_EN) 148e7300d04SMaxime Bizon 1492c8aaf71SJonas Gorski #define CKCTL_6362_ADSL_QPROC_EN (1 << 1) 1502c8aaf71SJonas Gorski #define CKCTL_6362_ADSL_AFE_EN (1 << 2) 1512c8aaf71SJonas Gorski #define CKCTL_6362_ADSL_EN (1 << 3) 1522c8aaf71SJonas Gorski #define CKCTL_6362_MIPS_EN (1 << 4) 1532c8aaf71SJonas Gorski #define CKCTL_6362_WLAN_OCP_EN (1 << 5) 1542c8aaf71SJonas Gorski #define CKCTL_6362_SWPKT_USB_EN (1 << 7) 1552c8aaf71SJonas Gorski #define CKCTL_6362_SWPKT_SAR_EN (1 << 8) 1562c8aaf71SJonas Gorski #define CKCTL_6362_SAR_EN (1 << 9) 1572c8aaf71SJonas Gorski #define CKCTL_6362_ROBOSW_EN (1 << 10) 1582c8aaf71SJonas Gorski #define CKCTL_6362_PCM_EN (1 << 11) 1592c8aaf71SJonas Gorski #define CKCTL_6362_USBD_EN (1 << 12) 1602c8aaf71SJonas Gorski #define CKCTL_6362_USBH_EN (1 << 13) 1612c8aaf71SJonas Gorski #define CKCTL_6362_IPSEC_EN (1 << 14) 1622c8aaf71SJonas Gorski #define CKCTL_6362_SPI_EN (1 << 15) 1632c8aaf71SJonas Gorski #define CKCTL_6362_HSSPI_EN (1 << 16) 1642c8aaf71SJonas Gorski #define CKCTL_6362_PCIE_EN (1 << 17) 1652c8aaf71SJonas Gorski #define CKCTL_6362_FAP_EN (1 << 18) 1662c8aaf71SJonas Gorski #define CKCTL_6362_PHYMIPS_EN (1 << 19) 1672c8aaf71SJonas Gorski #define CKCTL_6362_NAND_EN (1 << 20) 1682c8aaf71SJonas Gorski 1692c8aaf71SJonas Gorski #define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \ 1702c8aaf71SJonas Gorski CKCTL_6362_ADSL_QPROC_EN | \ 1712c8aaf71SJonas Gorski CKCTL_6362_ADSL_AFE_EN | \ 1722c8aaf71SJonas Gorski CKCTL_6362_ADSL_EN | \ 1732c8aaf71SJonas Gorski CKCTL_6362_SAR_EN | \ 1742c8aaf71SJonas Gorski CKCTL_6362_PCM_EN | \ 1752c8aaf71SJonas Gorski CKCTL_6362_IPSEC_EN | \ 1762c8aaf71SJonas Gorski CKCTL_6362_USBD_EN | \ 1772c8aaf71SJonas Gorski CKCTL_6362_USBH_EN | \ 1782c8aaf71SJonas Gorski CKCTL_6362_ROBOSW_EN | \ 1792c8aaf71SJonas Gorski CKCTL_6362_PCIE_EN) 1802c8aaf71SJonas Gorski 1812c8aaf71SJonas Gorski 18204712f3fSMaxime Bizon #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) 18304712f3fSMaxime Bizon #define CKCTL_6368_VDSL_AFE_EN (1 << 3) 18404712f3fSMaxime Bizon #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) 18504712f3fSMaxime Bizon #define CKCTL_6368_VDSL_EN (1 << 5) 18604712f3fSMaxime Bizon #define CKCTL_6368_PHYMIPS_EN (1 << 6) 18704712f3fSMaxime Bizon #define CKCTL_6368_SWPKT_USB_EN (1 << 7) 18804712f3fSMaxime Bizon #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) 189d9831a41SFlorian Fainelli #define CKCTL_6368_SPI_EN (1 << 9) 190d9831a41SFlorian Fainelli #define CKCTL_6368_USBD_EN (1 << 10) 191d9831a41SFlorian Fainelli #define CKCTL_6368_SAR_EN (1 << 11) 192d9831a41SFlorian Fainelli #define CKCTL_6368_ROBOSW_EN (1 << 12) 193d9831a41SFlorian Fainelli #define CKCTL_6368_UTOPIA_EN (1 << 13) 194d9831a41SFlorian Fainelli #define CKCTL_6368_PCM_EN (1 << 14) 195d9831a41SFlorian Fainelli #define CKCTL_6368_USBH_EN (1 << 15) 19604712f3fSMaxime Bizon #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) 197d9831a41SFlorian Fainelli #define CKCTL_6368_NAND_EN (1 << 17) 198d9831a41SFlorian Fainelli #define CKCTL_6368_IPSEC_EN (1 << 18) 19904712f3fSMaxime Bizon 20004712f3fSMaxime Bizon #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ 20104712f3fSMaxime Bizon CKCTL_6368_SWPKT_SAR_EN | \ 202d9831a41SFlorian Fainelli CKCTL_6368_SPI_EN | \ 203d9831a41SFlorian Fainelli CKCTL_6368_USBD_EN | \ 204d9831a41SFlorian Fainelli CKCTL_6368_SAR_EN | \ 205d9831a41SFlorian Fainelli CKCTL_6368_ROBOSW_EN | \ 206d9831a41SFlorian Fainelli CKCTL_6368_UTOPIA_EN | \ 207d9831a41SFlorian Fainelli CKCTL_6368_PCM_EN | \ 208d9831a41SFlorian Fainelli CKCTL_6368_USBH_EN | \ 20904712f3fSMaxime Bizon CKCTL_6368_DISABLE_GLESS_EN | \ 210d9831a41SFlorian Fainelli CKCTL_6368_NAND_EN | \ 211d9831a41SFlorian Fainelli CKCTL_6368_IPSEC_EN) 21204712f3fSMaxime Bizon 213e7300d04SMaxime Bizon /* System PLL Control register */ 214e7300d04SMaxime Bizon #define PERF_SYS_PLL_CTL_REG 0x8 215e7300d04SMaxime Bizon #define SYS_PLL_SOFT_RESET 0x1 216e7300d04SMaxime Bizon 217e7300d04SMaxime Bizon /* Interrupt Mask register */ 2187b933421SFlorian Fainelli #define PERF_IRQMASK_3368_REG 0xc 219cc81d7f3SJonas Gorski #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10) 220f61cced9SMaxime Bizon #define PERF_IRQMASK_6338_REG 0xc 221f61cced9SMaxime Bizon #define PERF_IRQMASK_6345_REG 0xc 222f61cced9SMaxime Bizon #define PERF_IRQMASK_6348_REG 0xc 223cc81d7f3SJonas Gorski #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) 224cc81d7f3SJonas Gorski #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) 225cc81d7f3SJonas Gorski #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) 226e7300d04SMaxime Bizon 227e7300d04SMaxime Bizon /* Interrupt Status register */ 2287b933421SFlorian Fainelli #define PERF_IRQSTAT_3368_REG 0x10 229cc81d7f3SJonas Gorski #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10) 230f61cced9SMaxime Bizon #define PERF_IRQSTAT_6338_REG 0x10 231f61cced9SMaxime Bizon #define PERF_IRQSTAT_6345_REG 0x10 232f61cced9SMaxime Bizon #define PERF_IRQSTAT_6348_REG 0x10 233cc81d7f3SJonas Gorski #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) 234cc81d7f3SJonas Gorski #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) 235cc81d7f3SJonas Gorski #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) 236e7300d04SMaxime Bizon 237e7300d04SMaxime Bizon /* External Interrupt Configuration register */ 2387b933421SFlorian Fainelli #define PERF_EXTIRQ_CFG_REG_3368 0x14 239e5766aeaSJonas Gorski #define PERF_EXTIRQ_CFG_REG_6328 0x18 2406224892cSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6338 0x14 24164eaea4aSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6345 0x14 2426224892cSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6348 0x14 2436224892cSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6358 0x14 2442c8aaf71SJonas Gorski #define PERF_EXTIRQ_CFG_REG_6362 0x18 24504712f3fSMaxime Bizon #define PERF_EXTIRQ_CFG_REG_6368 0x18 24604712f3fSMaxime Bizon 24704712f3fSMaxime Bizon #define PERF_EXTIRQ_CFG_REG2_6368 0x1c 248e7300d04SMaxime Bizon 2496224892cSMaxime Bizon /* for 6348 only */ 2506224892cSMaxime Bizon #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) 2516224892cSMaxime Bizon #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5)) 2526224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10)) 2536224892cSMaxime Bizon #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15)) 2546224892cSMaxime Bizon #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20)) 2556224892cSMaxime Bizon #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25)) 2566224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10) 2576224892cSMaxime Bizon #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15) 2586224892cSMaxime Bizon 2596224892cSMaxime Bizon /* for all others */ 2606224892cSMaxime Bizon #define EXTIRQ_CFG_SENSE(x) (1 << (x)) 2616224892cSMaxime Bizon #define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) 2626224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) 2636224892cSMaxime Bizon #define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) 2646224892cSMaxime Bizon #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) 2656224892cSMaxime Bizon #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) 2666224892cSMaxime Bizon #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) 2676224892cSMaxime Bizon #define EXTIRQ_CFG_MASK_ALL (0xf << 12) 268e7300d04SMaxime Bizon 269e7300d04SMaxime Bizon /* Soft Reset register */ 270e7300d04SMaxime Bizon #define PERF_SOFTRESET_REG 0x28 271e5766aeaSJonas Gorski #define PERF_SOFTRESET_6328_REG 0x10 272e7e9937fSJonas Gorski #define PERF_SOFTRESET_6358_REG 0x34 2732c8aaf71SJonas Gorski #define PERF_SOFTRESET_6362_REG 0x10 27404712f3fSMaxime Bizon #define PERF_SOFTRESET_6368_REG 0x10 275e7300d04SMaxime Bizon 2767b933421SFlorian Fainelli #define SOFTRESET_3368_SPI_MASK (1 << 0) 2777b933421SFlorian Fainelli #define SOFTRESET_3368_ENET_MASK (1 << 2) 2787b933421SFlorian Fainelli #define SOFTRESET_3368_MPI_MASK (1 << 3) 2797b933421SFlorian Fainelli #define SOFTRESET_3368_EPHY_MASK (1 << 6) 2807b933421SFlorian Fainelli #define SOFTRESET_3368_USBS_MASK (1 << 11) 2817b933421SFlorian Fainelli #define SOFTRESET_3368_PCM_MASK (1 << 13) 2827b933421SFlorian Fainelli 283e5766aeaSJonas Gorski #define SOFTRESET_6328_SPI_MASK (1 << 0) 284e5766aeaSJonas Gorski #define SOFTRESET_6328_EPHY_MASK (1 << 1) 285e5766aeaSJonas Gorski #define SOFTRESET_6328_SAR_MASK (1 << 2) 286e5766aeaSJonas Gorski #define SOFTRESET_6328_ENETSW_MASK (1 << 3) 287e5766aeaSJonas Gorski #define SOFTRESET_6328_USBS_MASK (1 << 4) 288e5766aeaSJonas Gorski #define SOFTRESET_6328_USBH_MASK (1 << 5) 289e5766aeaSJonas Gorski #define SOFTRESET_6328_PCM_MASK (1 << 6) 290e5766aeaSJonas Gorski #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7) 291e5766aeaSJonas Gorski #define SOFTRESET_6328_PCIE_MASK (1 << 8) 292e5766aeaSJonas Gorski #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9) 293e5766aeaSJonas Gorski #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10) 294e5766aeaSJonas Gorski 295e7300d04SMaxime Bizon #define SOFTRESET_6338_SPI_MASK (1 << 0) 296e7300d04SMaxime Bizon #define SOFTRESET_6338_ENET_MASK (1 << 2) 297e7300d04SMaxime Bizon #define SOFTRESET_6338_USBH_MASK (1 << 3) 298e7300d04SMaxime Bizon #define SOFTRESET_6338_USBS_MASK (1 << 4) 299e7300d04SMaxime Bizon #define SOFTRESET_6338_ADSL_MASK (1 << 5) 300e7300d04SMaxime Bizon #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) 301e7300d04SMaxime Bizon #define SOFTRESET_6338_SAR_MASK (1 << 7) 302e7300d04SMaxime Bizon #define SOFTRESET_6338_ACLC_MASK (1 << 8) 303e7300d04SMaxime Bizon #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) 304e7300d04SMaxime Bizon #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ 305e7300d04SMaxime Bizon SOFTRESET_6338_ENET_MASK | \ 306e7300d04SMaxime Bizon SOFTRESET_6338_USBH_MASK | \ 307e7300d04SMaxime Bizon SOFTRESET_6338_USBS_MASK | \ 308e7300d04SMaxime Bizon SOFTRESET_6338_ADSL_MASK | \ 309e7300d04SMaxime Bizon SOFTRESET_6338_DMAMEM_MASK | \ 310e7300d04SMaxime Bizon SOFTRESET_6338_SAR_MASK | \ 311e7300d04SMaxime Bizon SOFTRESET_6338_ACLC_MASK | \ 312e7300d04SMaxime Bizon SOFTRESET_6338_ADSLMIPSPLL_MASK) 313e7300d04SMaxime Bizon 314e7300d04SMaxime Bizon #define SOFTRESET_6348_SPI_MASK (1 << 0) 315e7300d04SMaxime Bizon #define SOFTRESET_6348_ENET_MASK (1 << 2) 316e7300d04SMaxime Bizon #define SOFTRESET_6348_USBH_MASK (1 << 3) 317e7300d04SMaxime Bizon #define SOFTRESET_6348_USBS_MASK (1 << 4) 318e7300d04SMaxime Bizon #define SOFTRESET_6348_ADSL_MASK (1 << 5) 319e7300d04SMaxime Bizon #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) 320e7300d04SMaxime Bizon #define SOFTRESET_6348_SAR_MASK (1 << 7) 321e7300d04SMaxime Bizon #define SOFTRESET_6348_ACLC_MASK (1 << 8) 322e7300d04SMaxime Bizon #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) 323e7300d04SMaxime Bizon 324e7300d04SMaxime Bizon #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ 325e7300d04SMaxime Bizon SOFTRESET_6348_ENET_MASK | \ 326e7300d04SMaxime Bizon SOFTRESET_6348_USBH_MASK | \ 327e7300d04SMaxime Bizon SOFTRESET_6348_USBS_MASK | \ 328e7300d04SMaxime Bizon SOFTRESET_6348_ADSL_MASK | \ 329e7300d04SMaxime Bizon SOFTRESET_6348_DMAMEM_MASK | \ 330e7300d04SMaxime Bizon SOFTRESET_6348_SAR_MASK | \ 331e7300d04SMaxime Bizon SOFTRESET_6348_ACLC_MASK | \ 332e7300d04SMaxime Bizon SOFTRESET_6348_ADSLMIPSPLL_MASK) 333e7300d04SMaxime Bizon 334e7e9937fSJonas Gorski #define SOFTRESET_6358_SPI_MASK (1 << 0) 335e7e9937fSJonas Gorski #define SOFTRESET_6358_ENET_MASK (1 << 2) 336e7e9937fSJonas Gorski #define SOFTRESET_6358_MPI_MASK (1 << 3) 337e7e9937fSJonas Gorski #define SOFTRESET_6358_EPHY_MASK (1 << 6) 338e7e9937fSJonas Gorski #define SOFTRESET_6358_SAR_MASK (1 << 7) 339e7e9937fSJonas Gorski #define SOFTRESET_6358_USBH_MASK (1 << 12) 340e7e9937fSJonas Gorski #define SOFTRESET_6358_PCM_MASK (1 << 13) 341e7e9937fSJonas Gorski #define SOFTRESET_6358_ADSL_MASK (1 << 14) 342e7e9937fSJonas Gorski 3432c8aaf71SJonas Gorski #define SOFTRESET_6362_SPI_MASK (1 << 0) 3442c8aaf71SJonas Gorski #define SOFTRESET_6362_IPSEC_MASK (1 << 1) 3452c8aaf71SJonas Gorski #define SOFTRESET_6362_EPHY_MASK (1 << 2) 3462c8aaf71SJonas Gorski #define SOFTRESET_6362_SAR_MASK (1 << 3) 3472c8aaf71SJonas Gorski #define SOFTRESET_6362_ENETSW_MASK (1 << 4) 3482c8aaf71SJonas Gorski #define SOFTRESET_6362_USBS_MASK (1 << 5) 3492c8aaf71SJonas Gorski #define SOFTRESET_6362_USBH_MASK (1 << 6) 3502c8aaf71SJonas Gorski #define SOFTRESET_6362_PCM_MASK (1 << 7) 3512c8aaf71SJonas Gorski #define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8) 3522c8aaf71SJonas Gorski #define SOFTRESET_6362_PCIE_MASK (1 << 9) 3532c8aaf71SJonas Gorski #define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10) 3542c8aaf71SJonas Gorski #define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11) 3552c8aaf71SJonas Gorski #define SOFTRESET_6362_DDR_PHY_MASK (1 << 12) 3562c8aaf71SJonas Gorski #define SOFTRESET_6362_FAP_MASK (1 << 13) 3572c8aaf71SJonas Gorski #define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14) 3582c8aaf71SJonas Gorski 35904712f3fSMaxime Bizon #define SOFTRESET_6368_SPI_MASK (1 << 0) 36004712f3fSMaxime Bizon #define SOFTRESET_6368_MPI_MASK (1 << 3) 36104712f3fSMaxime Bizon #define SOFTRESET_6368_EPHY_MASK (1 << 6) 36204712f3fSMaxime Bizon #define SOFTRESET_6368_SAR_MASK (1 << 7) 36304712f3fSMaxime Bizon #define SOFTRESET_6368_ENETSW_MASK (1 << 10) 36404712f3fSMaxime Bizon #define SOFTRESET_6368_USBS_MASK (1 << 11) 36504712f3fSMaxime Bizon #define SOFTRESET_6368_USBH_MASK (1 << 12) 36604712f3fSMaxime Bizon #define SOFTRESET_6368_PCM_MASK (1 << 13) 36704712f3fSMaxime Bizon 368e7300d04SMaxime Bizon /* MIPS PLL control register */ 369e7300d04SMaxime Bizon #define PERF_MIPSPLLCTL_REG 0x34 370e7300d04SMaxime Bizon #define MIPSPLLCTL_N1_SHIFT 20 371e7300d04SMaxime Bizon #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) 372e7300d04SMaxime Bizon #define MIPSPLLCTL_N2_SHIFT 15 373e7300d04SMaxime Bizon #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) 374e7300d04SMaxime Bizon #define MIPSPLLCTL_M1REF_SHIFT 12 375e7300d04SMaxime Bizon #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) 376e7300d04SMaxime Bizon #define MIPSPLLCTL_M2REF_SHIFT 9 377e7300d04SMaxime Bizon #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) 378e7300d04SMaxime Bizon #define MIPSPLLCTL_M1CPU_SHIFT 6 379e7300d04SMaxime Bizon #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) 380e7300d04SMaxime Bizon #define MIPSPLLCTL_M1BUS_SHIFT 3 381e7300d04SMaxime Bizon #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) 382e7300d04SMaxime Bizon #define MIPSPLLCTL_M2BUS_SHIFT 0 383e7300d04SMaxime Bizon #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) 384e7300d04SMaxime Bizon 385e7300d04SMaxime Bizon /* ADSL PHY PLL Control register */ 386e7300d04SMaxime Bizon #define PERF_ADSLPLLCTL_REG 0x38 387e7300d04SMaxime Bizon #define ADSLPLLCTL_N1_SHIFT 20 388e7300d04SMaxime Bizon #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) 389e7300d04SMaxime Bizon #define ADSLPLLCTL_N2_SHIFT 15 390e7300d04SMaxime Bizon #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) 391e7300d04SMaxime Bizon #define ADSLPLLCTL_M1REF_SHIFT 12 392e7300d04SMaxime Bizon #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) 393e7300d04SMaxime Bizon #define ADSLPLLCTL_M2REF_SHIFT 9 394e7300d04SMaxime Bizon #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) 395e7300d04SMaxime Bizon #define ADSLPLLCTL_M1CPU_SHIFT 6 396e7300d04SMaxime Bizon #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) 397e7300d04SMaxime Bizon #define ADSLPLLCTL_M1BUS_SHIFT 3 398e7300d04SMaxime Bizon #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) 399e7300d04SMaxime Bizon #define ADSLPLLCTL_M2BUS_SHIFT 0 400e7300d04SMaxime Bizon #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) 401e7300d04SMaxime Bizon 402e7300d04SMaxime Bizon #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ 403e7300d04SMaxime Bizon (((n1) << ADSLPLLCTL_N1_SHIFT) | \ 404e7300d04SMaxime Bizon ((n2) << ADSLPLLCTL_N2_SHIFT) | \ 405e7300d04SMaxime Bizon ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ 406e7300d04SMaxime Bizon ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ 407e7300d04SMaxime Bizon ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ 408e7300d04SMaxime Bizon ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ 409e7300d04SMaxime Bizon ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) 410e7300d04SMaxime Bizon 411e7300d04SMaxime Bizon 412e7300d04SMaxime Bizon /************************************************************************* 413e7300d04SMaxime Bizon * _REG relative to RSET_TIMER 414e7300d04SMaxime Bizon *************************************************************************/ 415e7300d04SMaxime Bizon 416e7300d04SMaxime Bizon #define BCM63XX_TIMER_COUNT 4 417e7300d04SMaxime Bizon #define TIMER_T0_ID 0 418e7300d04SMaxime Bizon #define TIMER_T1_ID 1 419e7300d04SMaxime Bizon #define TIMER_T2_ID 2 420e7300d04SMaxime Bizon #define TIMER_WDT_ID 3 421e7300d04SMaxime Bizon 422e7300d04SMaxime Bizon /* Timer irqstat register */ 423e7300d04SMaxime Bizon #define TIMER_IRQSTAT_REG 0 424e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) 425e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) 426e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) 427e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) 428e7300d04SMaxime Bizon #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) 429e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) 430e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) 431e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) 432e7300d04SMaxime Bizon #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) 433e7300d04SMaxime Bizon 434e7300d04SMaxime Bizon /* Timer control register */ 435e7300d04SMaxime Bizon #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) 436e7300d04SMaxime Bizon #define TIMER_CTL0_REG 0x4 437e7300d04SMaxime Bizon #define TIMER_CTL1_REG 0x8 438e7300d04SMaxime Bizon #define TIMER_CTL2_REG 0xC 439e7300d04SMaxime Bizon #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) 440e7300d04SMaxime Bizon #define TIMER_CTL_MONOTONIC_MASK (1 << 30) 441e7300d04SMaxime Bizon #define TIMER_CTL_ENABLE_MASK (1 << 31) 442e7300d04SMaxime Bizon 443e7300d04SMaxime Bizon 444e7300d04SMaxime Bizon /************************************************************************* 445e7300d04SMaxime Bizon * _REG relative to RSET_WDT 446e7300d04SMaxime Bizon *************************************************************************/ 447e7300d04SMaxime Bizon 448e7300d04SMaxime Bizon /* Watchdog default count register */ 449e7300d04SMaxime Bizon #define WDT_DEFVAL_REG 0x0 450e7300d04SMaxime Bizon 451e7300d04SMaxime Bizon /* Watchdog control register */ 452e7300d04SMaxime Bizon #define WDT_CTL_REG 0x4 453e7300d04SMaxime Bizon 454e7300d04SMaxime Bizon /* Watchdog control register constants */ 455e7300d04SMaxime Bizon #define WDT_START_1 (0xff00) 456e7300d04SMaxime Bizon #define WDT_START_2 (0x00ff) 457e7300d04SMaxime Bizon #define WDT_STOP_1 (0xee00) 458e7300d04SMaxime Bizon #define WDT_STOP_2 (0x00ee) 459e7300d04SMaxime Bizon 460e7300d04SMaxime Bizon /* Watchdog reset length register */ 461e7300d04SMaxime Bizon #define WDT_RSTLEN_REG 0x8 462e7300d04SMaxime Bizon 463e5766aeaSJonas Gorski /* Watchdog soft reset register (BCM6328 only) */ 464e5766aeaSJonas Gorski #define WDT_SOFTRESET_REG 0xc 465e7300d04SMaxime Bizon 466e7300d04SMaxime Bizon /************************************************************************* 467e7300d04SMaxime Bizon * _REG relative to RSET_GPIO 468e7300d04SMaxime Bizon *************************************************************************/ 469e7300d04SMaxime Bizon 470e7300d04SMaxime Bizon /* GPIO registers */ 471e7300d04SMaxime Bizon #define GPIO_CTL_HI_REG 0x0 472e7300d04SMaxime Bizon #define GPIO_CTL_LO_REG 0x4 473e7300d04SMaxime Bizon #define GPIO_DATA_HI_REG 0x8 474e7300d04SMaxime Bizon #define GPIO_DATA_LO_REG 0xC 47592d9ae20SFlorian Fainelli #define GPIO_DATA_LO_REG_6345 0x8 476e7300d04SMaxime Bizon 477e7300d04SMaxime Bizon /* GPIO mux registers and constants */ 478e7300d04SMaxime Bizon #define GPIO_MODE_REG 0x18 479e7300d04SMaxime Bizon 480e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_DIAG 0x00090000 481e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_UTOPIA 0x00080000 482e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 483e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 484e7300d04SMaxime Bizon #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 485e7300d04SMaxime Bizon #define GPIO_MODE_6348_G3_DIAG 0x00009000 486e7300d04SMaxime Bizon #define GPIO_MODE_6348_G3_UTOPIA 0x00008000 487e7300d04SMaxime Bizon #define GPIO_MODE_6348_G3_EXT_MII 0x00007000 488e7300d04SMaxime Bizon #define GPIO_MODE_6348_G2_DIAG 0x00000900 489e7300d04SMaxime Bizon #define GPIO_MODE_6348_G2_PCI 0x00000500 490e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_DIAG 0x00000090 491e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_UTOPIA 0x00000080 492e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_SPI_UART 0x00000060 493e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 494e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 495e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 496e7300d04SMaxime Bizon #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 497e7300d04SMaxime Bizon #define GPIO_MODE_6348_G0_DIAG 0x00000009 498e7300d04SMaxime Bizon #define GPIO_MODE_6348_G0_EXT_MII 0x00000007 499e7300d04SMaxime Bizon 500e7300d04SMaxime Bizon #define GPIO_MODE_6358_EXTRACS (1 << 5) 501e7300d04SMaxime Bizon #define GPIO_MODE_6358_UART1 (1 << 6) 502e7300d04SMaxime Bizon #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) 503e7300d04SMaxime Bizon #define GPIO_MODE_6358_SERIAL_LED (1 << 10) 504e7300d04SMaxime Bizon #define GPIO_MODE_6358_UTOPIA (1 << 12) 505e7300d04SMaxime Bizon 50604712f3fSMaxime Bizon #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) 50704712f3fSMaxime Bizon #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) 50804712f3fSMaxime Bizon #define GPIO_MODE_6368_SYS_IRQ (1 << 2) 50904712f3fSMaxime Bizon #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3) 51004712f3fSMaxime Bizon #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4) 51104712f3fSMaxime Bizon #define GPIO_MODE_6368_INET_LED (1 << 5) 51204712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY0_LED (1 << 6) 51304712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY1_LED (1 << 7) 51404712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY2_LED (1 << 8) 51504712f3fSMaxime Bizon #define GPIO_MODE_6368_EPHY3_LED (1 << 9) 51604712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10) 51704712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11) 51804712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12) 51904712f3fSMaxime Bizon #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13) 52004712f3fSMaxime Bizon #define GPIO_MODE_6368_USBD_LED (1 << 14) 52104712f3fSMaxime Bizon #define GPIO_MODE_6368_NTR_PULSE (1 << 15) 52204712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_REQ1 (1 << 16) 52304712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_GNT1 (1 << 17) 52404712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_INTB (1 << 18) 52504712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_REQ0 (1 << 19) 52604712f3fSMaxime Bizon #define GPIO_MODE_6368_PCI_GNT0 (1 << 20) 52704712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22) 52804712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23) 52904712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24) 53004712f3fSMaxime Bizon #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25) 53104712f3fSMaxime Bizon #define GPIO_MODE_6368_EBI_CS2 (1 << 26) 53204712f3fSMaxime Bizon #define GPIO_MODE_6368_EBI_CS3 (1 << 27) 53304712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN2 (1 << 28) 53404712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN3 (1 << 29) 53504712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) 53604712f3fSMaxime Bizon #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) 53704712f3fSMaxime Bizon 53804712f3fSMaxime Bizon 53918ec0e70SKevin Cernekee #define GPIO_PINMUX_OTHR_REG 0x24 54018ec0e70SKevin Cernekee #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 54118ec0e70SKevin Cernekee #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) 54218ec0e70SKevin Cernekee #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) 54318ec0e70SKevin Cernekee #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) 54418ec0e70SKevin Cernekee 54504712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_REG 0x38 54604712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_UART2 0x1 54704712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_GPIO 0x0 54804712f3fSMaxime Bizon #define GPIO_BASEMODE_6368_MASK 0x7 54904712f3fSMaxime Bizon /* those bits must be kept as read in gpio basemode register*/ 550e7300d04SMaxime Bizon 551aaf3fedbSJonas Gorski #define GPIO_STRAPBUS_REG 0x40 552aaf3fedbSJonas Gorski #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) 553aaf3fedbSJonas Gorski #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) 554aaf3fedbSJonas Gorski #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 555aaf3fedbSJonas Gorski #define STRAPBUS_6368_BOOT_SEL_NAND 0 556aaf3fedbSJonas Gorski #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 557aaf3fedbSJonas Gorski #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 558aaf3fedbSJonas Gorski 559aaf3fedbSJonas Gorski 560e7300d04SMaxime Bizon /************************************************************************* 561e7300d04SMaxime Bizon * _REG relative to RSET_ENET 562e7300d04SMaxime Bizon *************************************************************************/ 563e7300d04SMaxime Bizon 564e7300d04SMaxime Bizon /* Receiver Configuration register */ 565e7300d04SMaxime Bizon #define ENET_RXCFG_REG 0x0 566e7300d04SMaxime Bizon #define ENET_RXCFG_ALLMCAST_SHIFT 1 567e7300d04SMaxime Bizon #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) 568e7300d04SMaxime Bizon #define ENET_RXCFG_PROMISC_SHIFT 3 569e7300d04SMaxime Bizon #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) 570e7300d04SMaxime Bizon #define ENET_RXCFG_LOOPBACK_SHIFT 4 571e7300d04SMaxime Bizon #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) 572e7300d04SMaxime Bizon #define ENET_RXCFG_ENFLOW_SHIFT 5 573e7300d04SMaxime Bizon #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) 574e7300d04SMaxime Bizon 575e7300d04SMaxime Bizon /* Receive Maximum Length register */ 576e7300d04SMaxime Bizon #define ENET_RXMAXLEN_REG 0x4 577e7300d04SMaxime Bizon #define ENET_RXMAXLEN_SHIFT 0 578e7300d04SMaxime Bizon #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) 579e7300d04SMaxime Bizon 580e7300d04SMaxime Bizon /* Transmit Maximum Length register */ 581e7300d04SMaxime Bizon #define ENET_TXMAXLEN_REG 0x8 582e7300d04SMaxime Bizon #define ENET_TXMAXLEN_SHIFT 0 583e7300d04SMaxime Bizon #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) 584e7300d04SMaxime Bizon 585e7300d04SMaxime Bizon /* MII Status/Control register */ 586e7300d04SMaxime Bizon #define ENET_MIISC_REG 0x10 587e7300d04SMaxime Bizon #define ENET_MIISC_MDCFREQDIV_SHIFT 0 588e7300d04SMaxime Bizon #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) 589e7300d04SMaxime Bizon #define ENET_MIISC_PREAMBLEEN_SHIFT 7 590e7300d04SMaxime Bizon #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) 591e7300d04SMaxime Bizon 592e7300d04SMaxime Bizon /* MII Data register */ 593e7300d04SMaxime Bizon #define ENET_MIIDATA_REG 0x14 594e7300d04SMaxime Bizon #define ENET_MIIDATA_DATA_SHIFT 0 595e7300d04SMaxime Bizon #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) 596e7300d04SMaxime Bizon #define ENET_MIIDATA_TA_SHIFT 16 597e7300d04SMaxime Bizon #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) 598e7300d04SMaxime Bizon #define ENET_MIIDATA_REG_SHIFT 18 599e7300d04SMaxime Bizon #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) 600e7300d04SMaxime Bizon #define ENET_MIIDATA_PHYID_SHIFT 23 601e7300d04SMaxime Bizon #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) 602e7300d04SMaxime Bizon #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) 603e7300d04SMaxime Bizon #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) 604e7300d04SMaxime Bizon 605e7300d04SMaxime Bizon /* Ethernet Interrupt Mask register */ 606e7300d04SMaxime Bizon #define ENET_IRMASK_REG 0x18 607e7300d04SMaxime Bizon 608e7300d04SMaxime Bizon /* Ethernet Interrupt register */ 609e7300d04SMaxime Bizon #define ENET_IR_REG 0x1c 610e7300d04SMaxime Bizon #define ENET_IR_MII (1 << 0) 611e7300d04SMaxime Bizon #define ENET_IR_MIB (1 << 1) 612e7300d04SMaxime Bizon #define ENET_IR_FLOWC (1 << 2) 613e7300d04SMaxime Bizon 614e7300d04SMaxime Bizon /* Ethernet Control register */ 615e7300d04SMaxime Bizon #define ENET_CTL_REG 0x2c 616e7300d04SMaxime Bizon #define ENET_CTL_ENABLE_SHIFT 0 617e7300d04SMaxime Bizon #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) 618e7300d04SMaxime Bizon #define ENET_CTL_DISABLE_SHIFT 1 619e7300d04SMaxime Bizon #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) 620e7300d04SMaxime Bizon #define ENET_CTL_SRESET_SHIFT 2 621e7300d04SMaxime Bizon #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) 622e7300d04SMaxime Bizon #define ENET_CTL_EPHYSEL_SHIFT 3 623e7300d04SMaxime Bizon #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) 624e7300d04SMaxime Bizon 625e7300d04SMaxime Bizon /* Transmit Control register */ 626e7300d04SMaxime Bizon #define ENET_TXCTL_REG 0x30 627e7300d04SMaxime Bizon #define ENET_TXCTL_FD_SHIFT 0 628e7300d04SMaxime Bizon #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) 629e7300d04SMaxime Bizon 630e7300d04SMaxime Bizon /* Transmit Watermask register */ 631e7300d04SMaxime Bizon #define ENET_TXWMARK_REG 0x34 632e7300d04SMaxime Bizon #define ENET_TXWMARK_WM_SHIFT 0 633e7300d04SMaxime Bizon #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) 634e7300d04SMaxime Bizon 635e7300d04SMaxime Bizon /* MIB Control register */ 636e7300d04SMaxime Bizon #define ENET_MIBCTL_REG 0x38 637e7300d04SMaxime Bizon #define ENET_MIBCTL_RDCLEAR_SHIFT 0 638e7300d04SMaxime Bizon #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) 639e7300d04SMaxime Bizon 640e7300d04SMaxime Bizon /* Perfect Match Data Low register */ 641e7300d04SMaxime Bizon #define ENET_PML_REG(x) (0x58 + (x) * 8) 642e7300d04SMaxime Bizon #define ENET_PMH_REG(x) (0x5c + (x) * 8) 643e7300d04SMaxime Bizon #define ENET_PMH_DATAVALID_SHIFT 16 644e7300d04SMaxime Bizon #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) 645e7300d04SMaxime Bizon 646e7300d04SMaxime Bizon /* MIB register */ 647e7300d04SMaxime Bizon #define ENET_MIB_REG(x) (0x200 + (x) * 4) 648e7300d04SMaxime Bizon #define ENET_MIB_REG_COUNT 55 649e7300d04SMaxime Bizon 650e7300d04SMaxime Bizon 651e7300d04SMaxime Bizon /************************************************************************* 652e7300d04SMaxime Bizon * _REG relative to RSET_ENETDMA 653e7300d04SMaxime Bizon *************************************************************************/ 6543dc6475cSFlorian Fainelli #define ENETDMA_CHAN_WIDTH 0x10 6553dc6475cSFlorian Fainelli #define ENETDMA_6345_CHAN_WIDTH 0x40 656e7300d04SMaxime Bizon 657e7300d04SMaxime Bizon /* Controller Configuration Register */ 658e7300d04SMaxime Bizon #define ENETDMA_CFG_REG (0x0) 659e7300d04SMaxime Bizon #define ENETDMA_CFG_EN_SHIFT 0 660e7300d04SMaxime Bizon #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) 661e7300d04SMaxime Bizon #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) 662e7300d04SMaxime Bizon 663e7300d04SMaxime Bizon /* Flow Control Descriptor Low Threshold register */ 664e7300d04SMaxime Bizon #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) 665e7300d04SMaxime Bizon 666e7300d04SMaxime Bizon /* Flow Control Descriptor High Threshold register */ 667e7300d04SMaxime Bizon #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) 668e7300d04SMaxime Bizon 669e7300d04SMaxime Bizon /* Flow Control Descriptor Buffer Alloca Threshold register */ 670e7300d04SMaxime Bizon #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) 671e7300d04SMaxime Bizon #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 672e7300d04SMaxime Bizon #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) 673e7300d04SMaxime Bizon 6746f942345SKevin Cernekee /* Global interrupt status */ 6756f942345SKevin Cernekee #define ENETDMA_GLB_IRQSTAT_REG (0x40) 6766f942345SKevin Cernekee 6776f942345SKevin Cernekee /* Global interrupt mask */ 6786f942345SKevin Cernekee #define ENETDMA_GLB_IRQMASK_REG (0x44) 6796f942345SKevin Cernekee 680e7300d04SMaxime Bizon /* Channel Configuration register */ 681e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) 682e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_EN_SHIFT 0 683e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) 684e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 685e7300d04SMaxime Bizon #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) 686e7300d04SMaxime Bizon 687e7300d04SMaxime Bizon /* Interrupt Control/Status register */ 688e7300d04SMaxime Bizon #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) 689e7300d04SMaxime Bizon #define ENETDMA_IR_BUFDONE_MASK (1 << 0) 690e7300d04SMaxime Bizon #define ENETDMA_IR_PKTDONE_MASK (1 << 1) 691e7300d04SMaxime Bizon #define ENETDMA_IR_NOTOWNER_MASK (1 << 2) 692e7300d04SMaxime Bizon 693e7300d04SMaxime Bizon /* Interrupt Mask register */ 694e7300d04SMaxime Bizon #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) 695e7300d04SMaxime Bizon 696e7300d04SMaxime Bizon /* Maximum Burst Length */ 697e7300d04SMaxime Bizon #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) 698e7300d04SMaxime Bizon 699e7300d04SMaxime Bizon /* Ring Start Address register */ 700e7300d04SMaxime Bizon #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) 701e7300d04SMaxime Bizon 702e7300d04SMaxime Bizon /* State Ram Word 2 */ 703e7300d04SMaxime Bizon #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) 704e7300d04SMaxime Bizon 705e7300d04SMaxime Bizon /* State Ram Word 3 */ 706e7300d04SMaxime Bizon #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) 707e7300d04SMaxime Bizon 708e7300d04SMaxime Bizon /* State Ram Word 4 */ 709e7300d04SMaxime Bizon #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) 710e7300d04SMaxime Bizon 7113dc6475cSFlorian Fainelli /* Broadcom 6345 ENET DMA definitions */ 7123dc6475cSFlorian Fainelli #define ENETDMA_6345_CHANCFG_REG (0x00) 7133dc6475cSFlorian Fainelli 714eebc6056SJonas Gorski #define ENETDMA_6345_MAXBURST_REG (0x04) 7153dc6475cSFlorian Fainelli 7163dc6475cSFlorian Fainelli #define ENETDMA_6345_RSTART_REG (0x08) 7173dc6475cSFlorian Fainelli 7183dc6475cSFlorian Fainelli #define ENETDMA_6345_LEN_REG (0x0C) 7193dc6475cSFlorian Fainelli 7203dc6475cSFlorian Fainelli #define ENETDMA_6345_IR_REG (0x14) 7213dc6475cSFlorian Fainelli 7223dc6475cSFlorian Fainelli #define ENETDMA_6345_IRMASK_REG (0x18) 7233dc6475cSFlorian Fainelli 7243dc6475cSFlorian Fainelli #define ENETDMA_6345_FC_REG (0x1C) 7253dc6475cSFlorian Fainelli 7263dc6475cSFlorian Fainelli #define ENETDMA_6345_BUFALLOC_REG (0x20) 7273dc6475cSFlorian Fainelli 7283dc6475cSFlorian Fainelli /* Shift down for EOP, SOP and WRAP bits */ 7293dc6475cSFlorian Fainelli #define ENETDMA_6345_DESC_SHIFT (3) 730e7300d04SMaxime Bizon 731e7300d04SMaxime Bizon /************************************************************************* 732d430b6c5SMaxime Bizon * _REG relative to RSET_ENETDMAC 733d430b6c5SMaxime Bizon *************************************************************************/ 734d430b6c5SMaxime Bizon 735d430b6c5SMaxime Bizon /* Channel Configuration register */ 7363dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_REG (0x0) 737d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_EN_SHIFT 0 7386f942345SKevin Cernekee #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) 739d430b6c5SMaxime Bizon #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 7406f942345SKevin Cernekee #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) 7416f942345SKevin Cernekee #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 7426f942345SKevin Cernekee #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) 7433dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_CHAINING_SHIFT 2 7443dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT) 7453dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3 7463dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT) 7473dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4 7483dc6475cSFlorian Fainelli #define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT) 749d430b6c5SMaxime Bizon 750d430b6c5SMaxime Bizon /* Interrupt Control/Status register */ 7513dc6475cSFlorian Fainelli #define ENETDMAC_IR_REG (0x4) 752d430b6c5SMaxime Bizon #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) 753d430b6c5SMaxime Bizon #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) 754d430b6c5SMaxime Bizon #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) 755d430b6c5SMaxime Bizon 756d430b6c5SMaxime Bizon /* Interrupt Mask register */ 7573dc6475cSFlorian Fainelli #define ENETDMAC_IRMASK_REG (0x8) 758d430b6c5SMaxime Bizon 759d430b6c5SMaxime Bizon /* Maximum Burst Length */ 7603dc6475cSFlorian Fainelli #define ENETDMAC_MAXBURST_REG (0xc) 761d430b6c5SMaxime Bizon 762d430b6c5SMaxime Bizon 763d430b6c5SMaxime Bizon /************************************************************************* 764d430b6c5SMaxime Bizon * _REG relative to RSET_ENETDMAS 765d430b6c5SMaxime Bizon *************************************************************************/ 766d430b6c5SMaxime Bizon 767d430b6c5SMaxime Bizon /* Ring Start Address register */ 7683dc6475cSFlorian Fainelli #define ENETDMAS_RSTART_REG (0x0) 769d430b6c5SMaxime Bizon 770d430b6c5SMaxime Bizon /* State Ram Word 2 */ 7713dc6475cSFlorian Fainelli #define ENETDMAS_SRAM2_REG (0x4) 772d430b6c5SMaxime Bizon 773d430b6c5SMaxime Bizon /* State Ram Word 3 */ 7743dc6475cSFlorian Fainelli #define ENETDMAS_SRAM3_REG (0x8) 775d430b6c5SMaxime Bizon 776d430b6c5SMaxime Bizon /* State Ram Word 4 */ 7773dc6475cSFlorian Fainelli #define ENETDMAS_SRAM4_REG (0xc) 778d430b6c5SMaxime Bizon 779d430b6c5SMaxime Bizon 780d430b6c5SMaxime Bizon /************************************************************************* 781d430b6c5SMaxime Bizon * _REG relative to RSET_ENETSW 782d430b6c5SMaxime Bizon *************************************************************************/ 783d430b6c5SMaxime Bizon 7846f00a022SMaxime Bizon /* Port traffic control */ 7856f00a022SMaxime Bizon #define ENETSW_PTCTRL_REG(x) (0x0 + (x)) 7866f00a022SMaxime Bizon #define ENETSW_PTCTRL_RXDIS_MASK (1 << 0) 7876f00a022SMaxime Bizon #define ENETSW_PTCTRL_TXDIS_MASK (1 << 1) 7886f00a022SMaxime Bizon 7896f00a022SMaxime Bizon /* Switch mode register */ 7906f00a022SMaxime Bizon #define ENETSW_SWMODE_REG (0xb) 7916f00a022SMaxime Bizon #define ENETSW_SWMODE_FWD_EN_MASK (1 << 1) 7926f00a022SMaxime Bizon 7936f00a022SMaxime Bizon /* IMP override Register */ 7946f00a022SMaxime Bizon #define ENETSW_IMPOV_REG (0xe) 7956f00a022SMaxime Bizon #define ENETSW_IMPOV_FORCE_MASK (1 << 7) 7966f00a022SMaxime Bizon #define ENETSW_IMPOV_TXFLOW_MASK (1 << 5) 7976f00a022SMaxime Bizon #define ENETSW_IMPOV_RXFLOW_MASK (1 << 4) 7986f00a022SMaxime Bizon #define ENETSW_IMPOV_1000_MASK (1 << 3) 7996f00a022SMaxime Bizon #define ENETSW_IMPOV_100_MASK (1 << 2) 8006f00a022SMaxime Bizon #define ENETSW_IMPOV_FDX_MASK (1 << 1) 8016f00a022SMaxime Bizon #define ENETSW_IMPOV_LINKUP_MASK (1 << 0) 8026f00a022SMaxime Bizon 8036f00a022SMaxime Bizon /* Port override Register */ 8046f00a022SMaxime Bizon #define ENETSW_PORTOV_REG(x) (0x58 + (x)) 8056f00a022SMaxime Bizon #define ENETSW_PORTOV_ENABLE_MASK (1 << 6) 8066f00a022SMaxime Bizon #define ENETSW_PORTOV_TXFLOW_MASK (1 << 5) 8076f00a022SMaxime Bizon #define ENETSW_PORTOV_RXFLOW_MASK (1 << 4) 8086f00a022SMaxime Bizon #define ENETSW_PORTOV_1000_MASK (1 << 3) 8096f00a022SMaxime Bizon #define ENETSW_PORTOV_100_MASK (1 << 2) 8106f00a022SMaxime Bizon #define ENETSW_PORTOV_FDX_MASK (1 << 1) 8116f00a022SMaxime Bizon #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) 8126f00a022SMaxime Bizon 8136f00a022SMaxime Bizon /* MDIO control register */ 8146f00a022SMaxime Bizon #define ENETSW_MDIOC_REG (0xb0) 8156f00a022SMaxime Bizon #define ENETSW_MDIOC_EXT_MASK (1 << 16) 8166f00a022SMaxime Bizon #define ENETSW_MDIOC_REG_SHIFT 20 8176f00a022SMaxime Bizon #define ENETSW_MDIOC_PHYID_SHIFT 25 8186f00a022SMaxime Bizon #define ENETSW_MDIOC_RD_MASK (1 << 30) 8196f00a022SMaxime Bizon #define ENETSW_MDIOC_WR_MASK (1 << 31) 8206f00a022SMaxime Bizon 8216f00a022SMaxime Bizon /* MDIO data register */ 8226f00a022SMaxime Bizon #define ENETSW_MDIOD_REG (0xb4) 8236f00a022SMaxime Bizon 8246f00a022SMaxime Bizon /* Global Management Configuration Register */ 8256f00a022SMaxime Bizon #define ENETSW_GMCR_REG (0x200) 8266f00a022SMaxime Bizon #define ENETSW_GMCR_RST_MIB_MASK (1 << 0) 8276f00a022SMaxime Bizon 828d430b6c5SMaxime Bizon /* MIB register */ 829d430b6c5SMaxime Bizon #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) 830d430b6c5SMaxime Bizon #define ENETSW_MIB_REG_COUNT 47 831d430b6c5SMaxime Bizon 8326f00a022SMaxime Bizon /* Jumbo control register port mask register */ 8336f00a022SMaxime Bizon #define ENETSW_JMBCTL_PORT_REG (0x4004) 8346f00a022SMaxime Bizon 8356f00a022SMaxime Bizon /* Jumbo control mib good frame register */ 8366f00a022SMaxime Bizon #define ENETSW_JMBCTL_MAXSIZE_REG (0x4008) 8376f00a022SMaxime Bizon 838d430b6c5SMaxime Bizon 839d430b6c5SMaxime Bizon /************************************************************************* 840e7300d04SMaxime Bizon * _REG relative to RSET_OHCI_PRIV 841e7300d04SMaxime Bizon *************************************************************************/ 842e7300d04SMaxime Bizon 843e7300d04SMaxime Bizon #define OHCI_PRIV_REG 0x0 844e7300d04SMaxime Bizon #define OHCI_PRIV_PORT1_HOST_SHIFT 0 845e7300d04SMaxime Bizon #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) 846e7300d04SMaxime Bizon #define OHCI_PRIV_REG_SWAP_SHIFT 3 847e7300d04SMaxime Bizon #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) 848e7300d04SMaxime Bizon 849e7300d04SMaxime Bizon 850e7300d04SMaxime Bizon /************************************************************************* 851e7300d04SMaxime Bizon * _REG relative to RSET_USBH_PRIV 852e7300d04SMaxime Bizon *************************************************************************/ 853e7300d04SMaxime Bizon 85404712f3fSMaxime Bizon #define USBH_PRIV_SWAP_6358_REG 0x0 85504712f3fSMaxime Bizon #define USBH_PRIV_SWAP_6368_REG 0x1c 85604712f3fSMaxime Bizon 85718ec0e70SKevin Cernekee #define USBH_PRIV_SWAP_USBD_SHIFT 6 85818ec0e70SKevin Cernekee #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) 859e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 860e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 861e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 862e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) 863e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 864e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) 865e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 866e7300d04SMaxime Bizon #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 867e7300d04SMaxime Bizon 8685fd66c2bSKevin Cernekee #define USBH_PRIV_UTMI_CTL_6368_REG 0x10 8695fd66c2bSKevin Cernekee #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 8705fd66c2bSKevin Cernekee #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) 8715fd66c2bSKevin Cernekee #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 8725fd66c2bSKevin Cernekee #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) 8735fd66c2bSKevin Cernekee 87404712f3fSMaxime Bizon #define USBH_PRIV_TEST_6358_REG 0x24 87504712f3fSMaxime Bizon #define USBH_PRIV_TEST_6368_REG 0x14 87604712f3fSMaxime Bizon 87704712f3fSMaxime Bizon #define USBH_PRIV_SETUP_6368_REG 0x28 87804712f3fSMaxime Bizon #define USBH_PRIV_SETUP_IOC_SHIFT 4 87904712f3fSMaxime Bizon #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) 88004712f3fSMaxime Bizon 881e7300d04SMaxime Bizon 8825fd66c2bSKevin Cernekee /************************************************************************* 8835fd66c2bSKevin Cernekee * _REG relative to RSET_USBD 8845fd66c2bSKevin Cernekee *************************************************************************/ 8855fd66c2bSKevin Cernekee 8865fd66c2bSKevin Cernekee /* General control */ 8875fd66c2bSKevin Cernekee #define USBD_CONTROL_REG 0x00 8885fd66c2bSKevin Cernekee #define USBD_CONTROL_TXZLENINS_SHIFT 14 8895fd66c2bSKevin Cernekee #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) 8905fd66c2bSKevin Cernekee #define USBD_CONTROL_AUTO_CSRS_SHIFT 13 8915fd66c2bSKevin Cernekee #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) 8925fd66c2bSKevin Cernekee #define USBD_CONTROL_RXZSCFG_SHIFT 12 8935fd66c2bSKevin Cernekee #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) 8945fd66c2bSKevin Cernekee #define USBD_CONTROL_INIT_SEL_SHIFT 8 8955fd66c2bSKevin Cernekee #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) 8965fd66c2bSKevin Cernekee #define USBD_CONTROL_FIFO_RESET_SHIFT 6 8975fd66c2bSKevin Cernekee #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) 8985fd66c2bSKevin Cernekee #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 8995fd66c2bSKevin Cernekee #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) 9005fd66c2bSKevin Cernekee #define USBD_CONTROL_DONE_CSRS_SHIFT 0 9015fd66c2bSKevin Cernekee #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) 9025fd66c2bSKevin Cernekee 9035fd66c2bSKevin Cernekee /* Strap options */ 9045fd66c2bSKevin Cernekee #define USBD_STRAPS_REG 0x04 9055fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 9065fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) 9075fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_DISCON_SHIFT 9 9085fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) 9095fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 9105fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) 9115fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 9125fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) 9135fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_RAM_IF_SHIFT 7 9145fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) 9155fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_8BITPHY_SHIFT 2 9165fd66c2bSKevin Cernekee #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) 9175fd66c2bSKevin Cernekee #define USBD_STRAPS_SPEED_SHIFT 0 9185fd66c2bSKevin Cernekee #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) 9195fd66c2bSKevin Cernekee 9205fd66c2bSKevin Cernekee /* Stall control */ 9215fd66c2bSKevin Cernekee #define USBD_STALL_REG 0x08 9225fd66c2bSKevin Cernekee #define USBD_STALL_UPDATE_SHIFT 7 9235fd66c2bSKevin Cernekee #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) 9245fd66c2bSKevin Cernekee #define USBD_STALL_ENABLE_SHIFT 6 9255fd66c2bSKevin Cernekee #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) 9265fd66c2bSKevin Cernekee #define USBD_STALL_EPNUM_SHIFT 0 9275fd66c2bSKevin Cernekee #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) 9285fd66c2bSKevin Cernekee 9295fd66c2bSKevin Cernekee /* General status */ 9305fd66c2bSKevin Cernekee #define USBD_STATUS_REG 0x0c 9315fd66c2bSKevin Cernekee #define USBD_STATUS_SOF_SHIFT 16 9325fd66c2bSKevin Cernekee #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) 9335fd66c2bSKevin Cernekee #define USBD_STATUS_SPD_SHIFT 12 9345fd66c2bSKevin Cernekee #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) 9355fd66c2bSKevin Cernekee #define USBD_STATUS_ALTINTF_SHIFT 8 9365fd66c2bSKevin Cernekee #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) 9375fd66c2bSKevin Cernekee #define USBD_STATUS_INTF_SHIFT 4 9385fd66c2bSKevin Cernekee #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) 9395fd66c2bSKevin Cernekee #define USBD_STATUS_CFG_SHIFT 0 9405fd66c2bSKevin Cernekee #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) 9415fd66c2bSKevin Cernekee 9425fd66c2bSKevin Cernekee /* Other events */ 9435fd66c2bSKevin Cernekee #define USBD_EVENTS_REG 0x10 9445fd66c2bSKevin Cernekee #define USBD_EVENTS_USB_LINK_SHIFT 10 9455fd66c2bSKevin Cernekee #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) 9465fd66c2bSKevin Cernekee 9475fd66c2bSKevin Cernekee /* IRQ status */ 9485fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_STATUS_REG 0x14 9495fd66c2bSKevin Cernekee 9505fd66c2bSKevin Cernekee /* IRQ level (2 bits per IRQ event) */ 9515fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_CFG_HI_REG 0x18 9525fd66c2bSKevin Cernekee 9535fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c 9545fd66c2bSKevin Cernekee 9555fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) 9565fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) 9575fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) 9585fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) 9595fd66c2bSKevin Cernekee 9605fd66c2bSKevin Cernekee /* IRQ mask (1=unmasked) */ 9615fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_MASK_REG 0x20 9625fd66c2bSKevin Cernekee 9635fd66c2bSKevin Cernekee /* IRQ bits */ 9645fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_USB_LINK 10 9655fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_SETCFG 9 9665fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_SETINTF 8 9675fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_ERRATIC_ERR 7 9685fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_SET_CSRS 6 9695fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_SUSPEND 5 9705fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_EARLY_SUSPEND 4 9715fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_SOF 3 9725fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_ENUM_ON 2 9735fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_SETUP 1 9745fd66c2bSKevin Cernekee #define USBD_EVENT_IRQ_USB_RESET 0 9755fd66c2bSKevin Cernekee 9765fd66c2bSKevin Cernekee /* TX FIFO partitioning */ 9775fd66c2bSKevin Cernekee #define USBD_TXFIFO_CONFIG_REG 0x40 9785fd66c2bSKevin Cernekee #define USBD_TXFIFO_CONFIG_END_SHIFT 16 9795fd66c2bSKevin Cernekee #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) 9805fd66c2bSKevin Cernekee #define USBD_TXFIFO_CONFIG_START_SHIFT 0 9815fd66c2bSKevin Cernekee #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) 9825fd66c2bSKevin Cernekee 9835fd66c2bSKevin Cernekee /* RX FIFO partitioning */ 9845fd66c2bSKevin Cernekee #define USBD_RXFIFO_CONFIG_REG 0x44 9855fd66c2bSKevin Cernekee #define USBD_RXFIFO_CONFIG_END_SHIFT 16 9865fd66c2bSKevin Cernekee #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) 9875fd66c2bSKevin Cernekee #define USBD_RXFIFO_CONFIG_START_SHIFT 0 9885fd66c2bSKevin Cernekee #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) 9895fd66c2bSKevin Cernekee 9905fd66c2bSKevin Cernekee /* TX FIFO/endpoint configuration */ 9915fd66c2bSKevin Cernekee #define USBD_TXFIFO_EPSIZE_REG 0x48 9925fd66c2bSKevin Cernekee 9935fd66c2bSKevin Cernekee /* RX FIFO/endpoint configuration */ 9945fd66c2bSKevin Cernekee #define USBD_RXFIFO_EPSIZE_REG 0x4c 9955fd66c2bSKevin Cernekee 9965fd66c2bSKevin Cernekee /* Endpoint<->DMA mappings */ 9975fd66c2bSKevin Cernekee #define USBD_EPNUM_TYPEMAP_REG 0x50 9985fd66c2bSKevin Cernekee #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 9995fd66c2bSKevin Cernekee #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) 10005fd66c2bSKevin Cernekee #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 10015fd66c2bSKevin Cernekee #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) 10025fd66c2bSKevin Cernekee 10035fd66c2bSKevin Cernekee /* Misc per-endpoint settings */ 10045fd66c2bSKevin Cernekee #define USBD_CSR_SETUPADDR_REG 0x80 10055fd66c2bSKevin Cernekee #define USBD_CSR_SETUPADDR_DEF 0xb550 10065fd66c2bSKevin Cernekee 10075fd66c2bSKevin Cernekee #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) 10085fd66c2bSKevin Cernekee #define USBD_CSR_EP_MAXPKT_SHIFT 19 10095fd66c2bSKevin Cernekee #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) 10105fd66c2bSKevin Cernekee #define USBD_CSR_EP_ALTIFACE_SHIFT 15 10115fd66c2bSKevin Cernekee #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) 10125fd66c2bSKevin Cernekee #define USBD_CSR_EP_IFACE_SHIFT 11 10135fd66c2bSKevin Cernekee #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) 10145fd66c2bSKevin Cernekee #define USBD_CSR_EP_CFG_SHIFT 7 10155fd66c2bSKevin Cernekee #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) 10165fd66c2bSKevin Cernekee #define USBD_CSR_EP_TYPE_SHIFT 5 10175fd66c2bSKevin Cernekee #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) 10185fd66c2bSKevin Cernekee #define USBD_CSR_EP_DIR_SHIFT 4 10195fd66c2bSKevin Cernekee #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) 10205fd66c2bSKevin Cernekee #define USBD_CSR_EP_LOG_SHIFT 0 10215fd66c2bSKevin Cernekee #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) 10225fd66c2bSKevin Cernekee 1023e7300d04SMaxime Bizon 1024e7300d04SMaxime Bizon /************************************************************************* 1025e7300d04SMaxime Bizon * _REG relative to RSET_MPI 1026e7300d04SMaxime Bizon *************************************************************************/ 1027e7300d04SMaxime Bizon 1028e7300d04SMaxime Bizon /* well known (hard wired) chip select */ 1029e7300d04SMaxime Bizon #define MPI_CS_PCMCIA_COMMON 4 1030e7300d04SMaxime Bizon #define MPI_CS_PCMCIA_ATTR 5 1031e7300d04SMaxime Bizon #define MPI_CS_PCMCIA_IO 6 1032e7300d04SMaxime Bizon 1033e7300d04SMaxime Bizon /* Chip select base register */ 1034e7300d04SMaxime Bizon #define MPI_CSBASE_REG(x) (0x0 + (x) * 8) 1035e7300d04SMaxime Bizon #define MPI_CSBASE_BASE_SHIFT 13 1036e7300d04SMaxime Bizon #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) 1037e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_SHIFT 0 1038e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) 1039e7300d04SMaxime Bizon 1040e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_8K 0 1041e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_16K 1 1042e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_32K 2 1043e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_64K 3 1044e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_128K 4 1045e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_256K 5 1046e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_512K 6 1047e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_1M 7 1048e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_2M 8 1049e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_4M 9 1050e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_8M 10 1051e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_16M 11 1052e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_32M 12 1053e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_64M 13 1054e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_128M 14 1055e7300d04SMaxime Bizon #define MPI_CSBASE_SIZE_256M 15 1056e7300d04SMaxime Bizon 1057e7300d04SMaxime Bizon /* Chip select control register */ 1058e7300d04SMaxime Bizon #define MPI_CSCTL_REG(x) (0x4 + (x) * 8) 1059e7300d04SMaxime Bizon #define MPI_CSCTL_ENABLE_MASK (1 << 0) 1060e7300d04SMaxime Bizon #define MPI_CSCTL_WAIT_SHIFT 1 1061e7300d04SMaxime Bizon #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) 1062e7300d04SMaxime Bizon #define MPI_CSCTL_DATA16_MASK (1 << 4) 1063e7300d04SMaxime Bizon #define MPI_CSCTL_SYNCMODE_MASK (1 << 7) 1064e7300d04SMaxime Bizon #define MPI_CSCTL_TSIZE_MASK (1 << 8) 1065e7300d04SMaxime Bizon #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) 1066e7300d04SMaxime Bizon #define MPI_CSCTL_SETUP_SHIFT 16 1067e7300d04SMaxime Bizon #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) 1068e7300d04SMaxime Bizon #define MPI_CSCTL_HOLD_SHIFT 20 1069e7300d04SMaxime Bizon #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) 1070e7300d04SMaxime Bizon 1071e7300d04SMaxime Bizon /* PCI registers */ 1072e7300d04SMaxime Bizon #define MPI_SP0_RANGE_REG 0x100 1073e7300d04SMaxime Bizon #define MPI_SP0_REMAP_REG 0x104 1074e7300d04SMaxime Bizon #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) 1075e7300d04SMaxime Bizon #define MPI_SP1_RANGE_REG 0x10C 1076e7300d04SMaxime Bizon #define MPI_SP1_REMAP_REG 0x110 1077e7300d04SMaxime Bizon #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) 1078e7300d04SMaxime Bizon 1079e7300d04SMaxime Bizon #define MPI_L2PCFG_REG 0x11C 1080e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_TYPE_SHIFT 0 1081e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) 1082e7300d04SMaxime Bizon #define MPI_L2PCFG_REG_SHIFT 2 1083e7300d04SMaxime Bizon #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) 1084e7300d04SMaxime Bizon #define MPI_L2PCFG_FUNC_SHIFT 8 1085e7300d04SMaxime Bizon #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) 1086e7300d04SMaxime Bizon #define MPI_L2PCFG_DEVNUM_SHIFT 11 1087e7300d04SMaxime Bizon #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) 1088e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) 1089e7300d04SMaxime Bizon #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) 1090e7300d04SMaxime Bizon 1091e7300d04SMaxime Bizon #define MPI_L2PMEMRANGE1_REG 0x120 1092e7300d04SMaxime Bizon #define MPI_L2PMEMBASE1_REG 0x124 1093e7300d04SMaxime Bizon #define MPI_L2PMEMREMAP1_REG 0x128 1094e7300d04SMaxime Bizon #define MPI_L2PMEMRANGE2_REG 0x12C 1095e7300d04SMaxime Bizon #define MPI_L2PMEMBASE2_REG 0x130 1096e7300d04SMaxime Bizon #define MPI_L2PMEMREMAP2_REG 0x134 1097e7300d04SMaxime Bizon #define MPI_L2PIORANGE_REG 0x138 1098e7300d04SMaxime Bizon #define MPI_L2PIOBASE_REG 0x13C 1099e7300d04SMaxime Bizon #define MPI_L2PIOREMAP_REG 0x140 1100e7300d04SMaxime Bizon #define MPI_L2P_BASE_MASK (0xffff8000) 1101e7300d04SMaxime Bizon #define MPI_L2PREMAP_ENABLED_MASK (1 << 0) 1102e7300d04SMaxime Bizon #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) 1103e7300d04SMaxime Bizon 1104e7300d04SMaxime Bizon #define MPI_PCIMODESEL_REG 0x144 1105e7300d04SMaxime Bizon #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) 1106e7300d04SMaxime Bizon #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) 1107e7300d04SMaxime Bizon #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) 1108e7300d04SMaxime Bizon #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 1109e7300d04SMaxime Bizon #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) 1110e7300d04SMaxime Bizon 1111e7300d04SMaxime Bizon #define MPI_LOCBUSCTL_REG 0x14C 1112e7300d04SMaxime Bizon #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) 1113e7300d04SMaxime Bizon #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) 1114e7300d04SMaxime Bizon 1115e7300d04SMaxime Bizon #define MPI_LOCINT_REG 0x150 1116e7300d04SMaxime Bizon #define MPI_LOCINT_MASK(x) (1 << (x + 16)) 1117e7300d04SMaxime Bizon #define MPI_LOCINT_STAT(x) (1 << (x)) 1118e7300d04SMaxime Bizon #define MPI_LOCINT_DIR_FAILED 6 1119e7300d04SMaxime Bizon #define MPI_LOCINT_EXT_PCI_INT 7 1120e7300d04SMaxime Bizon #define MPI_LOCINT_SERR 8 1121e7300d04SMaxime Bizon #define MPI_LOCINT_CSERR 9 1122e7300d04SMaxime Bizon 1123e7300d04SMaxime Bizon #define MPI_PCICFGCTL_REG 0x178 1124e7300d04SMaxime Bizon #define MPI_PCICFGCTL_CFGADDR_SHIFT 2 1125e7300d04SMaxime Bizon #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) 1126e7300d04SMaxime Bizon #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) 1127e7300d04SMaxime Bizon 1128e7300d04SMaxime Bizon #define MPI_PCICFGDATA_REG 0x17C 1129e7300d04SMaxime Bizon 1130e7300d04SMaxime Bizon /* PCI host bridge custom register */ 1131e7300d04SMaxime Bizon #define BCMPCI_REG_TIMERS 0x40 1132e7300d04SMaxime Bizon #define REG_TIMER_TRDY_SHIFT 0 1133e7300d04SMaxime Bizon #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) 1134e7300d04SMaxime Bizon #define REG_TIMER_RETRY_SHIFT 8 1135e7300d04SMaxime Bizon #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) 1136e7300d04SMaxime Bizon 1137e7300d04SMaxime Bizon 1138e7300d04SMaxime Bizon /************************************************************************* 1139e7300d04SMaxime Bizon * _REG relative to RSET_PCMCIA 1140e7300d04SMaxime Bizon *************************************************************************/ 1141e7300d04SMaxime Bizon 1142e7300d04SMaxime Bizon #define PCMCIA_C1_REG 0x0 1143e7300d04SMaxime Bizon #define PCMCIA_C1_CD1_MASK (1 << 0) 1144e7300d04SMaxime Bizon #define PCMCIA_C1_CD2_MASK (1 << 1) 1145e7300d04SMaxime Bizon #define PCMCIA_C1_VS1_MASK (1 << 2) 1146e7300d04SMaxime Bizon #define PCMCIA_C1_VS2_MASK (1 << 3) 1147e7300d04SMaxime Bizon #define PCMCIA_C1_VS1OE_MASK (1 << 6) 1148e7300d04SMaxime Bizon #define PCMCIA_C1_VS2OE_MASK (1 << 7) 1149e7300d04SMaxime Bizon #define PCMCIA_C1_CBIDSEL_SHIFT (8) 1150e7300d04SMaxime Bizon #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) 1151e7300d04SMaxime Bizon #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) 1152e7300d04SMaxime Bizon #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) 1153e7300d04SMaxime Bizon #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) 1154e7300d04SMaxime Bizon #define PCMCIA_C1_RESET_MASK (1 << 18) 1155e7300d04SMaxime Bizon 1156e7300d04SMaxime Bizon #define PCMCIA_C2_REG 0x8 1157e7300d04SMaxime Bizon #define PCMCIA_C2_DATA16_MASK (1 << 0) 1158e7300d04SMaxime Bizon #define PCMCIA_C2_BYTESWAP_MASK (1 << 1) 1159e7300d04SMaxime Bizon #define PCMCIA_C2_RWCOUNT_SHIFT 2 1160e7300d04SMaxime Bizon #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) 1161e7300d04SMaxime Bizon #define PCMCIA_C2_INACTIVE_SHIFT 8 1162e7300d04SMaxime Bizon #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) 1163e7300d04SMaxime Bizon #define PCMCIA_C2_SETUP_SHIFT 16 1164e7300d04SMaxime Bizon #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) 1165e7300d04SMaxime Bizon #define PCMCIA_C2_HOLD_SHIFT 24 1166e7300d04SMaxime Bizon #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) 1167e7300d04SMaxime Bizon 1168e7300d04SMaxime Bizon 1169e7300d04SMaxime Bizon /************************************************************************* 1170e7300d04SMaxime Bizon * _REG relative to RSET_SDRAM 1171e7300d04SMaxime Bizon *************************************************************************/ 1172e7300d04SMaxime Bizon 1173e7300d04SMaxime Bizon #define SDRAM_CFG_REG 0x0 1174e7300d04SMaxime Bizon #define SDRAM_CFG_ROW_SHIFT 4 1175e7300d04SMaxime Bizon #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) 1176e7300d04SMaxime Bizon #define SDRAM_CFG_COL_SHIFT 6 1177e7300d04SMaxime Bizon #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) 1178e7300d04SMaxime Bizon #define SDRAM_CFG_32B_SHIFT 10 1179e7300d04SMaxime Bizon #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) 1180e7300d04SMaxime Bizon #define SDRAM_CFG_BANK_SHIFT 13 1181e7300d04SMaxime Bizon #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 1182e7300d04SMaxime Bizon 1183d61fcfe2SFlorian Fainelli #define SDRAM_MBASE_REG 0xc 1184d61fcfe2SFlorian Fainelli 1185e7300d04SMaxime Bizon #define SDRAM_PRIO_REG 0x2C 1186e7300d04SMaxime Bizon #define SDRAM_PRIO_MIPS_SHIFT 29 1187e7300d04SMaxime Bizon #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 1188e7300d04SMaxime Bizon #define SDRAM_PRIO_ADSL_SHIFT 30 1189e7300d04SMaxime Bizon #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) 1190e7300d04SMaxime Bizon #define SDRAM_PRIO_EN_SHIFT 31 1191e7300d04SMaxime Bizon #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) 1192e7300d04SMaxime Bizon 1193e7300d04SMaxime Bizon 1194e7300d04SMaxime Bizon /************************************************************************* 1195e7300d04SMaxime Bizon * _REG relative to RSET_MEMC 1196e7300d04SMaxime Bizon *************************************************************************/ 1197e7300d04SMaxime Bizon 1198e7300d04SMaxime Bizon #define MEMC_CFG_REG 0x4 1199e7300d04SMaxime Bizon #define MEMC_CFG_32B_SHIFT 1 1200e7300d04SMaxime Bizon #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) 1201e7300d04SMaxime Bizon #define MEMC_CFG_COL_SHIFT 3 1202e7300d04SMaxime Bizon #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) 1203e7300d04SMaxime Bizon #define MEMC_CFG_ROW_SHIFT 6 1204e7300d04SMaxime Bizon #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) 1205e7300d04SMaxime Bizon 1206e7300d04SMaxime Bizon 1207e7300d04SMaxime Bizon /************************************************************************* 1208e7300d04SMaxime Bizon * _REG relative to RSET_DDR 1209e7300d04SMaxime Bizon *************************************************************************/ 1210e7300d04SMaxime Bizon 1211e5766aeaSJonas Gorski #define DDR_CSEND_REG 0x8 1212e5766aeaSJonas Gorski 1213e7300d04SMaxime Bizon #define DDR_DMIPSPLLCFG_REG 0x18 1214e7300d04SMaxime Bizon #define DMIPSPLLCFG_M1_SHIFT 0 1215e7300d04SMaxime Bizon #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 1216e7300d04SMaxime Bizon #define DMIPSPLLCFG_N1_SHIFT 23 1217e7300d04SMaxime Bizon #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) 1218e7300d04SMaxime Bizon #define DMIPSPLLCFG_N2_SHIFT 29 1219e7300d04SMaxime Bizon #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 1220e7300d04SMaxime Bizon 122104712f3fSMaxime Bizon #define DDR_DMIPSPLLCFG_6368_REG 0x20 122204712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P1_SHIFT 0 122304712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) 122404712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P2_SHIFT 4 122504712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) 122604712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 122704712f3fSMaxime Bizon #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) 122804712f3fSMaxime Bizon 122904712f3fSMaxime Bizon #define DDR_DMIPSPLLDIV_6368_REG 0x24 123004712f3fSMaxime Bizon #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 123104712f3fSMaxime Bizon #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) 123204712f3fSMaxime Bizon 123304712f3fSMaxime Bizon 1234d430b6c5SMaxime Bizon /************************************************************************* 1235d430b6c5SMaxime Bizon * _REG relative to RSET_M2M 1236d430b6c5SMaxime Bizon *************************************************************************/ 1237d430b6c5SMaxime Bizon 1238d430b6c5SMaxime Bizon #define M2M_RX 0 1239d430b6c5SMaxime Bizon #define M2M_TX 1 1240d430b6c5SMaxime Bizon 1241d430b6c5SMaxime Bizon #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) 1242d430b6c5SMaxime Bizon #define M2M_DST_REG(x) ((x) * 0x40 + 0x04) 1243d430b6c5SMaxime Bizon #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) 1244d430b6c5SMaxime Bizon 1245d430b6c5SMaxime Bizon #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) 1246d430b6c5SMaxime Bizon #define M2M_CTRL_ENABLE_MASK (1 << 0) 1247d430b6c5SMaxime Bizon #define M2M_CTRL_IRQEN_MASK (1 << 1) 1248d430b6c5SMaxime Bizon #define M2M_CTRL_ERROR_CLR_MASK (1 << 6) 1249d430b6c5SMaxime Bizon #define M2M_CTRL_DONE_CLR_MASK (1 << 7) 1250d430b6c5SMaxime Bizon #define M2M_CTRL_NOINC_MASK (1 << 8) 1251d430b6c5SMaxime Bizon #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) 1252d430b6c5SMaxime Bizon #define M2M_CTRL_SWAPBYTE_MASK (1 << 10) 1253d430b6c5SMaxime Bizon #define M2M_CTRL_ENDIAN_MASK (1 << 11) 1254d430b6c5SMaxime Bizon 1255d430b6c5SMaxime Bizon #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) 1256d430b6c5SMaxime Bizon #define M2M_STAT_DONE (1 << 0) 1257d430b6c5SMaxime Bizon #define M2M_STAT_ERROR (1 << 1) 1258d430b6c5SMaxime Bizon 1259d430b6c5SMaxime Bizon #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) 1260d430b6c5SMaxime Bizon #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) 1261d430b6c5SMaxime Bizon 12620f6db0d0SFlorian Fainelli /************************************************************************* 12630f6db0d0SFlorian Fainelli * _REG relative to RSET_SPI 12640f6db0d0SFlorian Fainelli *************************************************************************/ 12650f6db0d0SFlorian Fainelli 12668a398d75SJonas Gorski /* BCM 6338/6348 SPI core */ 12670f6db0d0SFlorian Fainelli #define SPI_6348_CMD 0x00 /* 16-bits register */ 12680f6db0d0SFlorian Fainelli #define SPI_6348_INT_STATUS 0x02 12690f6db0d0SFlorian Fainelli #define SPI_6348_INT_MASK_ST 0x03 12700f6db0d0SFlorian Fainelli #define SPI_6348_INT_MASK 0x04 12710f6db0d0SFlorian Fainelli #define SPI_6348_ST 0x05 12720f6db0d0SFlorian Fainelli #define SPI_6348_CLK_CFG 0x06 12730f6db0d0SFlorian Fainelli #define SPI_6348_FILL_BYTE 0x07 12740f6db0d0SFlorian Fainelli #define SPI_6348_MSG_TAIL 0x09 12750f6db0d0SFlorian Fainelli #define SPI_6348_RX_TAIL 0x0b 12765a670445SFlorian Fainelli #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ 12775a670445SFlorian Fainelli #define SPI_6348_MSG_CTL_WIDTH 8 12780f6db0d0SFlorian Fainelli #define SPI_6348_MSG_DATA 0x41 12790f6db0d0SFlorian Fainelli #define SPI_6348_MSG_DATA_SIZE 0x3f 12800f6db0d0SFlorian Fainelli #define SPI_6348_RX_DATA 0x80 12810f6db0d0SFlorian Fainelli #define SPI_6348_RX_DATA_SIZE 0x3f 12820f6db0d0SFlorian Fainelli 12837b933421SFlorian Fainelli /* BCM 3368/6358/6262/6368 SPI core */ 12840f6db0d0SFlorian Fainelli #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 12855a670445SFlorian Fainelli #define SPI_6358_MSG_CTL_WIDTH 16 12860f6db0d0SFlorian Fainelli #define SPI_6358_MSG_DATA 0x02 12870f6db0d0SFlorian Fainelli #define SPI_6358_MSG_DATA_SIZE 0x21e 12880f6db0d0SFlorian Fainelli #define SPI_6358_RX_DATA 0x400 12890f6db0d0SFlorian Fainelli #define SPI_6358_RX_DATA_SIZE 0x220 12900f6db0d0SFlorian Fainelli #define SPI_6358_CMD 0x700 /* 16-bits register */ 12910f6db0d0SFlorian Fainelli #define SPI_6358_INT_STATUS 0x702 12920f6db0d0SFlorian Fainelli #define SPI_6358_INT_MASK_ST 0x703 12930f6db0d0SFlorian Fainelli #define SPI_6358_INT_MASK 0x704 12940f6db0d0SFlorian Fainelli #define SPI_6358_ST 0x705 12950f6db0d0SFlorian Fainelli #define SPI_6358_CLK_CFG 0x706 12960f6db0d0SFlorian Fainelli #define SPI_6358_FILL_BYTE 0x707 12970f6db0d0SFlorian Fainelli #define SPI_6358_MSG_TAIL 0x709 12980f6db0d0SFlorian Fainelli #define SPI_6358_RX_TAIL 0x70B 12990f6db0d0SFlorian Fainelli 13000f6db0d0SFlorian Fainelli /* Shared SPI definitions */ 13010f6db0d0SFlorian Fainelli 13020f6db0d0SFlorian Fainelli /* Message configuration */ 13030f6db0d0SFlorian Fainelli #define SPI_FD_RW 0x00 13040f6db0d0SFlorian Fainelli #define SPI_HD_W 0x01 13050f6db0d0SFlorian Fainelli #define SPI_HD_R 0x02 13060f6db0d0SFlorian Fainelli #define SPI_BYTE_CNT_SHIFT 0 13075a670445SFlorian Fainelli #define SPI_6348_MSG_TYPE_SHIFT 6 13085a670445SFlorian Fainelli #define SPI_6358_MSG_TYPE_SHIFT 14 13090f6db0d0SFlorian Fainelli 13100f6db0d0SFlorian Fainelli /* Command */ 13110f6db0d0SFlorian Fainelli #define SPI_CMD_NOOP 0x00 13120f6db0d0SFlorian Fainelli #define SPI_CMD_SOFT_RESET 0x01 13130f6db0d0SFlorian Fainelli #define SPI_CMD_HARD_RESET 0x02 13140f6db0d0SFlorian Fainelli #define SPI_CMD_START_IMMEDIATE 0x03 13150f6db0d0SFlorian Fainelli #define SPI_CMD_COMMAND_SHIFT 0 13160f6db0d0SFlorian Fainelli #define SPI_CMD_COMMAND_MASK 0x000f 13170f6db0d0SFlorian Fainelli #define SPI_CMD_DEVICE_ID_SHIFT 4 13180f6db0d0SFlorian Fainelli #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 13190f6db0d0SFlorian Fainelli #define SPI_CMD_ONE_BYTE_SHIFT 11 13200f6db0d0SFlorian Fainelli #define SPI_CMD_ONE_WIRE_SHIFT 12 13210f6db0d0SFlorian Fainelli #define SPI_DEV_ID_0 0 13220f6db0d0SFlorian Fainelli #define SPI_DEV_ID_1 1 13230f6db0d0SFlorian Fainelli #define SPI_DEV_ID_2 2 13240f6db0d0SFlorian Fainelli #define SPI_DEV_ID_3 3 13250f6db0d0SFlorian Fainelli 13260f6db0d0SFlorian Fainelli /* Interrupt mask */ 13270f6db0d0SFlorian Fainelli #define SPI_INTR_CMD_DONE 0x01 13280f6db0d0SFlorian Fainelli #define SPI_INTR_RX_OVERFLOW 0x02 13290f6db0d0SFlorian Fainelli #define SPI_INTR_TX_UNDERFLOW 0x04 13300f6db0d0SFlorian Fainelli #define SPI_INTR_TX_OVERFLOW 0x08 13310f6db0d0SFlorian Fainelli #define SPI_INTR_RX_UNDERFLOW 0x10 13320f6db0d0SFlorian Fainelli #define SPI_INTR_CLEAR_ALL 0x1f 13330f6db0d0SFlorian Fainelli 13340f6db0d0SFlorian Fainelli /* Status */ 13350f6db0d0SFlorian Fainelli #define SPI_RX_EMPTY 0x02 13360f6db0d0SFlorian Fainelli #define SPI_CMD_BUSY 0x04 13370f6db0d0SFlorian Fainelli #define SPI_SERIAL_BUSY 0x08 13380f6db0d0SFlorian Fainelli 13390f6db0d0SFlorian Fainelli /* Clock configuration */ 13400f6db0d0SFlorian Fainelli #define SPI_CLK_20MHZ 0x00 13410f6db0d0SFlorian Fainelli #define SPI_CLK_0_391MHZ 0x01 13420f6db0d0SFlorian Fainelli #define SPI_CLK_0_781MHZ 0x02 /* default */ 13430f6db0d0SFlorian Fainelli #define SPI_CLK_1_563MHZ 0x03 13440f6db0d0SFlorian Fainelli #define SPI_CLK_3_125MHZ 0x04 13450f6db0d0SFlorian Fainelli #define SPI_CLK_6_250MHZ 0x05 13460f6db0d0SFlorian Fainelli #define SPI_CLK_12_50MHZ 0x06 13470f6db0d0SFlorian Fainelli #define SPI_CLK_MASK 0x07 13480f6db0d0SFlorian Fainelli #define SPI_SSOFFTIME_MASK 0x38 13490f6db0d0SFlorian Fainelli #define SPI_SSOFFTIME_SHIFT 3 13500f6db0d0SFlorian Fainelli #define SPI_BYTE_SWAP 0x80 13510f6db0d0SFlorian Fainelli 1352e5766aeaSJonas Gorski /************************************************************************* 1353e5766aeaSJonas Gorski * _REG relative to RSET_MISC 1354e5766aeaSJonas Gorski *************************************************************************/ 1355a156ba61SJonas Gorski #define MISC_SERDES_CTRL_6328_REG 0x0 1356a156ba61SJonas Gorski #define MISC_SERDES_CTRL_6362_REG 0x4 135719c860d9SJonas Gorski #define SERDES_PCIE_EN (1 << 0) 135819c860d9SJonas Gorski #define SERDES_PCIE_EXD_EN (1 << 15) 1359e5766aeaSJonas Gorski 13602c8aaf71SJonas Gorski #define MISC_STRAPBUS_6362_REG 0x14 13612c8aaf71SJonas Gorski #define STRAPBUS_6362_FCVO_SHIFT 1 1362ab8ed982SJonas Gorski #define STRAPBUS_6362_HSSPI_CLK_FAST (1 << 13) 13632c8aaf71SJonas Gorski #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) 13642c8aaf71SJonas Gorski #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) 13652c8aaf71SJonas Gorski #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) 13662c8aaf71SJonas Gorski 1367e5766aeaSJonas Gorski #define MISC_STRAPBUS_6328_REG 0x240 1368e5766aeaSJonas Gorski #define STRAPBUS_6328_FCVO_SHIFT 7 1369e5766aeaSJonas Gorski #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 13702038e041SÁlvaro Fernández Rojas #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18) 13712038e041SÁlvaro Fernández Rojas #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18) 1372e5766aeaSJonas Gorski 137319c860d9SJonas Gorski /************************************************************************* 137419c860d9SJonas Gorski * _REG relative to RSET_PCIE 137519c860d9SJonas Gorski *************************************************************************/ 137619c860d9SJonas Gorski 137719c860d9SJonas Gorski #define PCIE_CONFIG2_REG 0x408 137819c860d9SJonas Gorski #define CONFIG2_BAR1_SIZE_EN 1 137919c860d9SJonas Gorski #define CONFIG2_BAR1_SIZE_MASK 0xf 138019c860d9SJonas Gorski 138119c860d9SJonas Gorski #define PCIE_IDVAL3_REG 0x43c 138219c860d9SJonas Gorski #define IDVAL3_CLASS_CODE_MASK 0xffffff 138319c860d9SJonas Gorski #define IDVAL3_SUBCLASS_SHIFT 8 138419c860d9SJonas Gorski #define IDVAL3_CLASS_SHIFT 16 138519c860d9SJonas Gorski 138619c860d9SJonas Gorski #define PCIE_DLSTATUS_REG 0x1048 138719c860d9SJonas Gorski #define DLSTATUS_PHYLINKUP (1 << 13) 138819c860d9SJonas Gorski 138919c860d9SJonas Gorski #define PCIE_BRIDGE_OPT1_REG 0x2820 139019c860d9SJonas Gorski #define OPT1_RD_BE_OPT_EN (1 << 7) 139119c860d9SJonas Gorski #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9) 139219c860d9SJonas Gorski #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11) 139319c860d9SJonas Gorski #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12) 139419c860d9SJonas Gorski 139519c860d9SJonas Gorski #define PCIE_BRIDGE_OPT2_REG 0x2824 139619c860d9SJonas Gorski #define OPT2_UBUS_UR_DECODE_DIS (1 << 2) 139719c860d9SJonas Gorski #define OPT2_TX_CREDIT_CHK_EN (1 << 4) 139819c860d9SJonas Gorski #define OPT2_CFG_TYPE1_BD_SEL (1 << 7) 139919c860d9SJonas Gorski #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16 140019c860d9SJonas Gorski #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT) 140119c860d9SJonas Gorski 140219c860d9SJonas Gorski #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828 140319c860d9SJonas Gorski #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830 140419c860d9SJonas Gorski #define BASEMASK_REMAP_EN (1 << 0) 140519c860d9SJonas Gorski #define BASEMASK_SWAP_EN (1 << 1) 140619c860d9SJonas Gorski #define BASEMASK_MASK_SHIFT 4 140719c860d9SJonas Gorski #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT) 140819c860d9SJonas Gorski #define BASEMASK_BASE_SHIFT 20 140919c860d9SJonas Gorski #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT) 141019c860d9SJonas Gorski 141119c860d9SJonas Gorski #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c 141219c860d9SJonas Gorski #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834 141319c860d9SJonas Gorski #define REBASE_ADDR_BASE_SHIFT 20 141419c860d9SJonas Gorski #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT) 141519c860d9SJonas Gorski 141619c860d9SJonas Gorski #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854 141719c860d9SJonas Gorski #define PCIE_RC_INT_A (1 << 0) 141819c860d9SJonas Gorski #define PCIE_RC_INT_B (1 << 1) 141919c860d9SJonas Gorski #define PCIE_RC_INT_C (1 << 2) 142019c860d9SJonas Gorski #define PCIE_RC_INT_D (1 << 3) 142119c860d9SJonas Gorski 142219c860d9SJonas Gorski #define PCIE_DEVICE_OFFSET 0x8000 142319c860d9SJonas Gorski 14247ac836ceSJonas Gorski /************************************************************************* 14257ac836ceSJonas Gorski * _REG relative to RSET_OTP 14267ac836ceSJonas Gorski *************************************************************************/ 14277ac836ceSJonas Gorski 14287ac836ceSJonas Gorski #define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4) 14297ac836ceSJonas Gorski #define OTP_6328_REG3_TP1_DISABLED BIT(9) 14307ac836ceSJonas Gorski 1431e7300d04SMaxime Bizon #endif /* BCM63XX_REGS_H_ */ 1432