1 #ifndef BCM63XX_CPU_H_ 2 #define BCM63XX_CPU_H_ 3 4 #include <linux/types.h> 5 #include <linux/init.h> 6 7 /* 8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 9 * compile time if only one CPU support is enabled (idea stolen from 10 * arm mach-types) 11 */ 12 #define BCM6338_CPU_ID 0x6338 13 #define BCM6345_CPU_ID 0x6345 14 #define BCM6348_CPU_ID 0x6348 15 #define BCM6358_CPU_ID 0x6358 16 #define BCM6368_CPU_ID 0x6368 17 18 void __init bcm63xx_cpu_init(void); 19 u16 __bcm63xx_get_cpu_id(void); 20 u16 bcm63xx_get_cpu_rev(void); 21 unsigned int bcm63xx_get_cpu_freq(void); 22 23 #ifdef CONFIG_BCM63XX_CPU_6338 24 # ifdef bcm63xx_get_cpu_id 25 # undef bcm63xx_get_cpu_id 26 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 27 # define BCMCPU_RUNTIME_DETECT 28 # else 29 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID 30 # endif 31 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 32 #else 33 # define BCMCPU_IS_6338() (0) 34 #endif 35 36 #ifdef CONFIG_BCM63XX_CPU_6345 37 # ifdef bcm63xx_get_cpu_id 38 # undef bcm63xx_get_cpu_id 39 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 40 # define BCMCPU_RUNTIME_DETECT 41 # else 42 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID 43 # endif 44 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 45 #else 46 # define BCMCPU_IS_6345() (0) 47 #endif 48 49 #ifdef CONFIG_BCM63XX_CPU_6348 50 # ifdef bcm63xx_get_cpu_id 51 # undef bcm63xx_get_cpu_id 52 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 53 # define BCMCPU_RUNTIME_DETECT 54 # else 55 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID 56 # endif 57 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 58 #else 59 # define BCMCPU_IS_6348() (0) 60 #endif 61 62 #ifdef CONFIG_BCM63XX_CPU_6358 63 # ifdef bcm63xx_get_cpu_id 64 # undef bcm63xx_get_cpu_id 65 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 66 # define BCMCPU_RUNTIME_DETECT 67 # else 68 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID 69 # endif 70 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 71 #else 72 # define BCMCPU_IS_6358() (0) 73 #endif 74 75 #ifdef CONFIG_BCM63XX_CPU_6368 76 # ifdef bcm63xx_get_cpu_id 77 # undef bcm63xx_get_cpu_id 78 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 79 # define BCMCPU_RUNTIME_DETECT 80 # else 81 # define bcm63xx_get_cpu_id() BCM6368_CPU_ID 82 # endif 83 # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) 84 #else 85 # define BCMCPU_IS_6368() (0) 86 #endif 87 88 #ifndef bcm63xx_get_cpu_id 89 #error "No CPU support configured" 90 #endif 91 92 /* 93 * While registers sets are (mostly) the same across 63xx CPU, base 94 * address of these sets do change. 95 */ 96 enum bcm63xx_regs_set { 97 RSET_DSL_LMEM = 0, 98 RSET_PERF, 99 RSET_TIMER, 100 RSET_WDT, 101 RSET_UART0, 102 RSET_UART1, 103 RSET_GPIO, 104 RSET_SPI, 105 RSET_SPI2, 106 RSET_UDC0, 107 RSET_OHCI0, 108 RSET_OHCI_PRIV, 109 RSET_USBH_PRIV, 110 RSET_MPI, 111 RSET_PCMCIA, 112 RSET_DSL, 113 RSET_ENET0, 114 RSET_ENET1, 115 RSET_ENETDMA, 116 RSET_ENETDMAC, 117 RSET_ENETDMAS, 118 RSET_ENETSW, 119 RSET_EHCI0, 120 RSET_SDRAM, 121 RSET_MEMC, 122 RSET_DDR, 123 RSET_M2M, 124 RSET_ATM, 125 RSET_XTM, 126 RSET_XTMDMA, 127 RSET_XTMDMAC, 128 RSET_XTMDMAS, 129 RSET_PCM, 130 RSET_PCMDMA, 131 RSET_PCMDMAC, 132 RSET_PCMDMAS, 133 }; 134 135 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 136 #define RSET_DSL_SIZE 4096 137 #define RSET_WDT_SIZE 12 138 #define RSET_ENET_SIZE 2048 139 #define RSET_ENETDMA_SIZE 2048 140 #define RSET_ENETSW_SIZE 65536 141 #define RSET_UART_SIZE 24 142 #define RSET_UDC_SIZE 256 143 #define RSET_OHCI_SIZE 256 144 #define RSET_EHCI_SIZE 256 145 #define RSET_PCMCIA_SIZE 12 146 #define RSET_M2M_SIZE 256 147 #define RSET_ATM_SIZE 4096 148 #define RSET_XTM_SIZE 10240 149 #define RSET_XTMDMA_SIZE 256 150 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 151 #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 152 153 /* 154 * 6338 register sets base address 155 */ 156 #define BCM_6338_DSL_LMEM_BASE (0xfff00000) 157 #define BCM_6338_PERF_BASE (0xfffe0000) 158 #define BCM_6338_BB_BASE (0xfffe0100) 159 #define BCM_6338_TIMER_BASE (0xfffe0200) 160 #define BCM_6338_WDT_BASE (0xfffe021c) 161 #define BCM_6338_UART0_BASE (0xfffe0300) 162 #define BCM_6338_UART1_BASE (0xdeadbeef) 163 #define BCM_6338_GPIO_BASE (0xfffe0400) 164 #define BCM_6338_SPI_BASE (0xfffe0c00) 165 #define BCM_6338_SPI2_BASE (0xdeadbeef) 166 #define BCM_6338_UDC0_BASE (0xdeadbeef) 167 #define BCM_6338_USBDMA_BASE (0xfffe2400) 168 #define BCM_6338_OHCI0_BASE (0xdeadbeef) 169 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 170 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 171 #define BCM_6338_MPI_BASE (0xfffe3160) 172 #define BCM_6338_PCMCIA_BASE (0xdeadbeef) 173 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 174 #define BCM_6338_DSL_BASE (0xfffe1000) 175 #define BCM_6338_UBUS_BASE (0xdeadbeef) 176 #define BCM_6338_ENET0_BASE (0xfffe2800) 177 #define BCM_6338_ENET1_BASE (0xdeadbeef) 178 #define BCM_6338_ENETDMA_BASE (0xfffe2400) 179 #define BCM_6338_ENETDMAC_BASE (0xfffe2500) 180 #define BCM_6338_ENETDMAS_BASE (0xfffe2600) 181 #define BCM_6338_ENETSW_BASE (0xdeadbeef) 182 #define BCM_6338_EHCI0_BASE (0xdeadbeef) 183 #define BCM_6338_SDRAM_BASE (0xfffe3100) 184 #define BCM_6338_MEMC_BASE (0xdeadbeef) 185 #define BCM_6338_DDR_BASE (0xdeadbeef) 186 #define BCM_6338_M2M_BASE (0xdeadbeef) 187 #define BCM_6338_ATM_BASE (0xfffe2000) 188 #define BCM_6338_XTM_BASE (0xdeadbeef) 189 #define BCM_6338_XTMDMA_BASE (0xdeadbeef) 190 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef) 191 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef) 192 #define BCM_6338_PCM_BASE (0xdeadbeef) 193 #define BCM_6338_PCMDMA_BASE (0xdeadbeef) 194 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 195 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 196 197 /* 198 * 6345 register sets base address 199 */ 200 #define BCM_6345_DSL_LMEM_BASE (0xfff00000) 201 #define BCM_6345_PERF_BASE (0xfffe0000) 202 #define BCM_6345_BB_BASE (0xfffe0100) 203 #define BCM_6345_TIMER_BASE (0xfffe0200) 204 #define BCM_6345_WDT_BASE (0xfffe021c) 205 #define BCM_6345_UART0_BASE (0xfffe0300) 206 #define BCM_6345_UART1_BASE (0xdeadbeef) 207 #define BCM_6345_GPIO_BASE (0xfffe0400) 208 #define BCM_6345_SPI_BASE (0xdeadbeef) 209 #define BCM_6345_SPI2_BASE (0xdeadbeef) 210 #define BCM_6345_UDC0_BASE (0xdeadbeef) 211 #define BCM_6345_USBDMA_BASE (0xfffe2800) 212 #define BCM_6345_ENET0_BASE (0xfffe1800) 213 #define BCM_6345_ENETDMA_BASE (0xfffe2800) 214 #define BCM_6345_ENETDMAC_BASE (0xfffe2900) 215 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 216 #define BCM_6345_ENETSW_BASE (0xdeadbeef) 217 #define BCM_6345_PCMCIA_BASE (0xfffe2028) 218 #define BCM_6345_MPI_BASE (0xfffe2000) 219 #define BCM_6345_OHCI0_BASE (0xfffe2100) 220 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 221 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 222 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 223 #define BCM_6345_DSL_BASE (0xdeadbeef) 224 #define BCM_6345_UBUS_BASE (0xdeadbeef) 225 #define BCM_6345_ENET1_BASE (0xdeadbeef) 226 #define BCM_6345_EHCI0_BASE (0xdeadbeef) 227 #define BCM_6345_SDRAM_BASE (0xfffe2300) 228 #define BCM_6345_MEMC_BASE (0xdeadbeef) 229 #define BCM_6345_DDR_BASE (0xdeadbeef) 230 #define BCM_6345_M2M_BASE (0xdeadbeef) 231 #define BCM_6345_ATM_BASE (0xfffe4000) 232 #define BCM_6345_XTM_BASE (0xdeadbeef) 233 #define BCM_6345_XTMDMA_BASE (0xdeadbeef) 234 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef) 235 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef) 236 #define BCM_6345_PCM_BASE (0xdeadbeef) 237 #define BCM_6345_PCMDMA_BASE (0xdeadbeef) 238 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 239 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 240 241 /* 242 * 6348 register sets base address 243 */ 244 #define BCM_6348_DSL_LMEM_BASE (0xfff00000) 245 #define BCM_6348_PERF_BASE (0xfffe0000) 246 #define BCM_6348_TIMER_BASE (0xfffe0200) 247 #define BCM_6348_WDT_BASE (0xfffe021c) 248 #define BCM_6348_UART0_BASE (0xfffe0300) 249 #define BCM_6348_UART1_BASE (0xdeadbeef) 250 #define BCM_6348_GPIO_BASE (0xfffe0400) 251 #define BCM_6348_SPI_BASE (0xfffe0c00) 252 #define BCM_6348_SPI2_BASE (0xdeadbeef) 253 #define BCM_6348_UDC0_BASE (0xfffe1000) 254 #define BCM_6348_OHCI0_BASE (0xfffe1b00) 255 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 256 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 257 #define BCM_6348_MPI_BASE (0xfffe2000) 258 #define BCM_6348_PCMCIA_BASE (0xfffe2054) 259 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 260 #define BCM_6348_M2M_BASE (0xfffe2800) 261 #define BCM_6348_DSL_BASE (0xfffe3000) 262 #define BCM_6348_ENET0_BASE (0xfffe6000) 263 #define BCM_6348_ENET1_BASE (0xfffe6800) 264 #define BCM_6348_ENETDMA_BASE (0xfffe7000) 265 #define BCM_6348_ENETDMAC_BASE (0xfffe7100) 266 #define BCM_6348_ENETDMAS_BASE (0xfffe7200) 267 #define BCM_6348_ENETSW_BASE (0xdeadbeef) 268 #define BCM_6348_EHCI0_BASE (0xdeadbeef) 269 #define BCM_6348_SDRAM_BASE (0xfffe2300) 270 #define BCM_6348_MEMC_BASE (0xdeadbeef) 271 #define BCM_6348_DDR_BASE (0xdeadbeef) 272 #define BCM_6348_ATM_BASE (0xfffe4000) 273 #define BCM_6348_XTM_BASE (0xdeadbeef) 274 #define BCM_6348_XTMDMA_BASE (0xdeadbeef) 275 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef) 276 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef) 277 #define BCM_6348_PCM_BASE (0xdeadbeef) 278 #define BCM_6348_PCMDMA_BASE (0xdeadbeef) 279 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 280 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 281 282 /* 283 * 6358 register sets base address 284 */ 285 #define BCM_6358_DSL_LMEM_BASE (0xfff00000) 286 #define BCM_6358_PERF_BASE (0xfffe0000) 287 #define BCM_6358_TIMER_BASE (0xfffe0040) 288 #define BCM_6358_WDT_BASE (0xfffe005c) 289 #define BCM_6358_UART0_BASE (0xfffe0100) 290 #define BCM_6358_UART1_BASE (0xfffe0120) 291 #define BCM_6358_GPIO_BASE (0xfffe0080) 292 #define BCM_6358_SPI_BASE (0xdeadbeef) 293 #define BCM_6358_SPI2_BASE (0xfffe0800) 294 #define BCM_6358_UDC0_BASE (0xfffe0800) 295 #define BCM_6358_OHCI0_BASE (0xfffe1400) 296 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 297 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 298 #define BCM_6358_MPI_BASE (0xfffe1000) 299 #define BCM_6358_PCMCIA_BASE (0xfffe1054) 300 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 301 #define BCM_6358_M2M_BASE (0xdeadbeef) 302 #define BCM_6358_DSL_BASE (0xfffe3000) 303 #define BCM_6358_ENET0_BASE (0xfffe4000) 304 #define BCM_6358_ENET1_BASE (0xfffe4800) 305 #define BCM_6358_ENETDMA_BASE (0xfffe5000) 306 #define BCM_6358_ENETDMAC_BASE (0xfffe5100) 307 #define BCM_6358_ENETDMAS_BASE (0xfffe5200) 308 #define BCM_6358_ENETSW_BASE (0xdeadbeef) 309 #define BCM_6358_EHCI0_BASE (0xfffe1300) 310 #define BCM_6358_SDRAM_BASE (0xdeadbeef) 311 #define BCM_6358_MEMC_BASE (0xfffe1200) 312 #define BCM_6358_DDR_BASE (0xfffe12a0) 313 #define BCM_6358_ATM_BASE (0xfffe2000) 314 #define BCM_6358_XTM_BASE (0xdeadbeef) 315 #define BCM_6358_XTMDMA_BASE (0xdeadbeef) 316 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef) 317 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef) 318 #define BCM_6358_PCM_BASE (0xfffe1600) 319 #define BCM_6358_PCMDMA_BASE (0xfffe1800) 320 #define BCM_6358_PCMDMAC_BASE (0xfffe1900) 321 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 322 323 324 /* 325 * 6368 register sets base address 326 */ 327 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) 328 #define BCM_6368_PERF_BASE (0xb0000000) 329 #define BCM_6368_TIMER_BASE (0xb0000040) 330 #define BCM_6368_WDT_BASE (0xb000005c) 331 #define BCM_6368_UART0_BASE (0xb0000100) 332 #define BCM_6368_UART1_BASE (0xb0000120) 333 #define BCM_6368_GPIO_BASE (0xb0000080) 334 #define BCM_6368_SPI_BASE (0xdeadbeef) 335 #define BCM_6368_SPI2_BASE (0xb0000800) 336 #define BCM_6368_UDC0_BASE (0xdeadbeef) 337 #define BCM_6368_OHCI0_BASE (0xb0001600) 338 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 339 #define BCM_6368_USBH_PRIV_BASE (0xb0001700) 340 #define BCM_6368_MPI_BASE (0xb0001000) 341 #define BCM_6368_PCMCIA_BASE (0xb0001054) 342 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 343 #define BCM_6368_M2M_BASE (0xdeadbeef) 344 #define BCM_6368_DSL_BASE (0xdeadbeef) 345 #define BCM_6368_ENET0_BASE (0xdeadbeef) 346 #define BCM_6368_ENET1_BASE (0xdeadbeef) 347 #define BCM_6368_ENETDMA_BASE (0xb0006800) 348 #define BCM_6368_ENETDMAC_BASE (0xb0006a00) 349 #define BCM_6368_ENETDMAS_BASE (0xb0006c00) 350 #define BCM_6368_ENETSW_BASE (0xb0f00000) 351 #define BCM_6368_EHCI0_BASE (0xb0001500) 352 #define BCM_6368_SDRAM_BASE (0xdeadbeef) 353 #define BCM_6368_MEMC_BASE (0xb0001200) 354 #define BCM_6368_DDR_BASE (0xb0001280) 355 #define BCM_6368_ATM_BASE (0xdeadbeef) 356 #define BCM_6368_XTM_BASE (0xb0001800) 357 #define BCM_6368_XTMDMA_BASE (0xb0005000) 358 #define BCM_6368_XTMDMAC_BASE (0xb0005200) 359 #define BCM_6368_XTMDMAS_BASE (0xb0005400) 360 #define BCM_6368_PCM_BASE (0xb0004000) 361 #define BCM_6368_PCMDMA_BASE (0xb0005800) 362 #define BCM_6368_PCMDMAC_BASE (0xb0005a00) 363 #define BCM_6368_PCMDMAS_BASE (0xb0005c00) 364 365 366 extern const unsigned long *bcm63xx_regs_base; 367 368 #define __GEN_RSET_BASE(__cpu, __rset) \ 369 case RSET_## __rset : \ 370 return BCM_## __cpu ##_## __rset ##_BASE; 371 372 #define __GEN_RSET(__cpu) \ 373 switch (set) { \ 374 __GEN_RSET_BASE(__cpu, DSL_LMEM) \ 375 __GEN_RSET_BASE(__cpu, PERF) \ 376 __GEN_RSET_BASE(__cpu, TIMER) \ 377 __GEN_RSET_BASE(__cpu, WDT) \ 378 __GEN_RSET_BASE(__cpu, UART0) \ 379 __GEN_RSET_BASE(__cpu, UART1) \ 380 __GEN_RSET_BASE(__cpu, GPIO) \ 381 __GEN_RSET_BASE(__cpu, SPI) \ 382 __GEN_RSET_BASE(__cpu, SPI2) \ 383 __GEN_RSET_BASE(__cpu, UDC0) \ 384 __GEN_RSET_BASE(__cpu, OHCI0) \ 385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \ 387 __GEN_RSET_BASE(__cpu, MPI) \ 388 __GEN_RSET_BASE(__cpu, PCMCIA) \ 389 __GEN_RSET_BASE(__cpu, DSL) \ 390 __GEN_RSET_BASE(__cpu, ENET0) \ 391 __GEN_RSET_BASE(__cpu, ENET1) \ 392 __GEN_RSET_BASE(__cpu, ENETDMA) \ 393 __GEN_RSET_BASE(__cpu, ENETDMAC) \ 394 __GEN_RSET_BASE(__cpu, ENETDMAS) \ 395 __GEN_RSET_BASE(__cpu, ENETSW) \ 396 __GEN_RSET_BASE(__cpu, EHCI0) \ 397 __GEN_RSET_BASE(__cpu, SDRAM) \ 398 __GEN_RSET_BASE(__cpu, MEMC) \ 399 __GEN_RSET_BASE(__cpu, DDR) \ 400 __GEN_RSET_BASE(__cpu, M2M) \ 401 __GEN_RSET_BASE(__cpu, ATM) \ 402 __GEN_RSET_BASE(__cpu, XTM) \ 403 __GEN_RSET_BASE(__cpu, XTMDMA) \ 404 __GEN_RSET_BASE(__cpu, XTMDMAC) \ 405 __GEN_RSET_BASE(__cpu, XTMDMAS) \ 406 __GEN_RSET_BASE(__cpu, PCM) \ 407 __GEN_RSET_BASE(__cpu, PCMDMA) \ 408 __GEN_RSET_BASE(__cpu, PCMDMAC) \ 409 __GEN_RSET_BASE(__cpu, PCMDMAS) \ 410 } 411 412 #define __GEN_CPU_REGS_TABLE(__cpu) \ 413 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ 414 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ 415 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ 416 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ 417 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ 418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \ 422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 431 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ 432 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ 433 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ 434 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ 435 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ 436 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ 437 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ 438 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ 439 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ 440 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ 441 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ 442 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ 443 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ 444 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ 445 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ 446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 449 450 451 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 452 { 453 #ifdef BCMCPU_RUNTIME_DETECT 454 return bcm63xx_regs_base[set]; 455 #else 456 #ifdef CONFIG_BCM63XX_CPU_6338 457 __GEN_RSET(6338) 458 #endif 459 #ifdef CONFIG_BCM63XX_CPU_6345 460 __GEN_RSET(6345) 461 #endif 462 #ifdef CONFIG_BCM63XX_CPU_6348 463 __GEN_RSET(6348) 464 #endif 465 #ifdef CONFIG_BCM63XX_CPU_6358 466 __GEN_RSET(6358) 467 #endif 468 #ifdef CONFIG_BCM63XX_CPU_6368 469 __GEN_RSET(6368) 470 #endif 471 #endif 472 /* unreached */ 473 return 0; 474 } 475 476 /* 477 * IRQ number changes across CPU too 478 */ 479 enum bcm63xx_irq { 480 IRQ_TIMER = 0, 481 IRQ_UART0, 482 IRQ_UART1, 483 IRQ_DSL, 484 IRQ_ENET0, 485 IRQ_ENET1, 486 IRQ_ENET_PHY, 487 IRQ_OHCI0, 488 IRQ_EHCI0, 489 IRQ_ENET0_RXDMA, 490 IRQ_ENET0_TXDMA, 491 IRQ_ENET1_RXDMA, 492 IRQ_ENET1_TXDMA, 493 IRQ_PCI, 494 IRQ_PCMCIA, 495 IRQ_ATM, 496 IRQ_ENETSW_RXDMA0, 497 IRQ_ENETSW_RXDMA1, 498 IRQ_ENETSW_RXDMA2, 499 IRQ_ENETSW_RXDMA3, 500 IRQ_ENETSW_TXDMA0, 501 IRQ_ENETSW_TXDMA1, 502 IRQ_ENETSW_TXDMA2, 503 IRQ_ENETSW_TXDMA3, 504 IRQ_XTM, 505 IRQ_XTM_DMA0, 506 }; 507 508 /* 509 * 6338 irqs 510 */ 511 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 512 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 513 #define BCM_6338_UART1_IRQ 0 514 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 515 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 516 #define BCM_6338_ENET1_IRQ 0 517 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 518 #define BCM_6338_OHCI0_IRQ 0 519 #define BCM_6338_EHCI0_IRQ 0 520 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 521 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 522 #define BCM_6338_ENET1_RXDMA_IRQ 0 523 #define BCM_6338_ENET1_TXDMA_IRQ 0 524 #define BCM_6338_PCI_IRQ 0 525 #define BCM_6338_PCMCIA_IRQ 0 526 #define BCM_6338_ATM_IRQ 0 527 #define BCM_6338_ENETSW_RXDMA0_IRQ 0 528 #define BCM_6338_ENETSW_RXDMA1_IRQ 0 529 #define BCM_6338_ENETSW_RXDMA2_IRQ 0 530 #define BCM_6338_ENETSW_RXDMA3_IRQ 0 531 #define BCM_6338_ENETSW_TXDMA0_IRQ 0 532 #define BCM_6338_ENETSW_TXDMA1_IRQ 0 533 #define BCM_6338_ENETSW_TXDMA2_IRQ 0 534 #define BCM_6338_ENETSW_TXDMA3_IRQ 0 535 #define BCM_6338_XTM_IRQ 0 536 #define BCM_6338_XTM_DMA0_IRQ 0 537 538 /* 539 * 6345 irqs 540 */ 541 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 542 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 543 #define BCM_6345_UART1_IRQ 0 544 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 545 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 546 #define BCM_6345_ENET1_IRQ 0 547 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 548 #define BCM_6345_OHCI0_IRQ 0 549 #define BCM_6345_EHCI0_IRQ 0 550 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 551 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 552 #define BCM_6345_ENET1_RXDMA_IRQ 0 553 #define BCM_6345_ENET1_TXDMA_IRQ 0 554 #define BCM_6345_PCI_IRQ 0 555 #define BCM_6345_PCMCIA_IRQ 0 556 #define BCM_6345_ATM_IRQ 0 557 #define BCM_6345_ENETSW_RXDMA0_IRQ 0 558 #define BCM_6345_ENETSW_RXDMA1_IRQ 0 559 #define BCM_6345_ENETSW_RXDMA2_IRQ 0 560 #define BCM_6345_ENETSW_RXDMA3_IRQ 0 561 #define BCM_6345_ENETSW_TXDMA0_IRQ 0 562 #define BCM_6345_ENETSW_TXDMA1_IRQ 0 563 #define BCM_6345_ENETSW_TXDMA2_IRQ 0 564 #define BCM_6345_ENETSW_TXDMA3_IRQ 0 565 #define BCM_6345_XTM_IRQ 0 566 #define BCM_6345_XTM_DMA0_IRQ 0 567 568 /* 569 * 6348 irqs 570 */ 571 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 572 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 573 #define BCM_6348_UART1_IRQ 0 574 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 575 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 576 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 577 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 578 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 579 #define BCM_6348_EHCI0_IRQ 0 580 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 581 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 582 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 583 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 584 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 585 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 586 #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) 587 #define BCM_6348_ENETSW_RXDMA0_IRQ 0 588 #define BCM_6348_ENETSW_RXDMA1_IRQ 0 589 #define BCM_6348_ENETSW_RXDMA2_IRQ 0 590 #define BCM_6348_ENETSW_RXDMA3_IRQ 0 591 #define BCM_6348_ENETSW_TXDMA0_IRQ 0 592 #define BCM_6348_ENETSW_TXDMA1_IRQ 0 593 #define BCM_6348_ENETSW_TXDMA2_IRQ 0 594 #define BCM_6348_ENETSW_TXDMA3_IRQ 0 595 #define BCM_6348_XTM_IRQ 0 596 #define BCM_6348_XTM_DMA0_IRQ 0 597 598 /* 599 * 6358 irqs 600 */ 601 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 602 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 603 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 604 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 605 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 606 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 607 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 608 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 609 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 610 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 611 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 612 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 613 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 614 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 615 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 616 #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) 617 #define BCM_6358_ENETSW_RXDMA0_IRQ 0 618 #define BCM_6358_ENETSW_RXDMA1_IRQ 0 619 #define BCM_6358_ENETSW_RXDMA2_IRQ 0 620 #define BCM_6358_ENETSW_RXDMA3_IRQ 0 621 #define BCM_6358_ENETSW_TXDMA0_IRQ 0 622 #define BCM_6358_ENETSW_TXDMA1_IRQ 0 623 #define BCM_6358_ENETSW_TXDMA2_IRQ 0 624 #define BCM_6358_ENETSW_TXDMA3_IRQ 0 625 #define BCM_6358_XTM_IRQ 0 626 #define BCM_6358_XTM_DMA0_IRQ 0 627 628 #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) 629 #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) 630 #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 631 #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 632 #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 633 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 634 635 /* 636 * 6368 irqs 637 */ 638 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 639 640 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 641 #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 642 #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 643 #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 644 #define BCM_6368_ENET0_IRQ 0 645 #define BCM_6368_ENET1_IRQ 0 646 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 647 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 648 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 649 #define BCM_6368_PCMCIA_IRQ 0 650 #define BCM_6368_ENET0_RXDMA_IRQ 0 651 #define BCM_6368_ENET0_TXDMA_IRQ 0 652 #define BCM_6368_ENET1_RXDMA_IRQ 0 653 #define BCM_6368_ENET1_TXDMA_IRQ 0 654 #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) 655 #define BCM_6368_ATM_IRQ 0 656 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) 657 #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) 658 #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) 659 #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) 660 #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) 661 #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) 662 #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) 663 #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) 664 #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) 665 #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) 666 667 #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) 668 #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) 669 #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) 670 #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) 671 #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) 672 #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) 673 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) 674 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) 675 676 extern const int *bcm63xx_irqs; 677 678 #define __GEN_CPU_IRQ_TABLE(__cpu) \ 679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 683 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 684 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 685 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 686 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 687 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 688 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ 689 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ 690 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ 691 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ 692 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ 693 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ 694 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ 695 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ 696 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ 697 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ 698 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ 699 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ 700 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ 701 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ 702 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ 703 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ 704 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ 705 706 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 707 { 708 return bcm63xx_irqs[irq]; 709 } 710 711 /* 712 * return installed memory size 713 */ 714 unsigned int bcm63xx_get_memory_size(void); 715 716 void bcm63xx_machine_halt(void); 717 718 void bcm63xx_machine_reboot(void); 719 720 #endif /* !BCM63XX_CPU_H_ */ 721