1 #ifndef BCM63XX_CPU_H_ 2 #define BCM63XX_CPU_H_ 3 4 #include <linux/types.h> 5 #include <linux/init.h> 6 7 /* 8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 9 * compile time if only one CPU support is enabled (idea stolen from 10 * arm mach-types) 11 */ 12 #define BCM3368_CPU_ID 0x3368 13 #define BCM6328_CPU_ID 0x6328 14 #define BCM6338_CPU_ID 0x6338 15 #define BCM6345_CPU_ID 0x6345 16 #define BCM6348_CPU_ID 0x6348 17 #define BCM6358_CPU_ID 0x6358 18 #define BCM6362_CPU_ID 0x6362 19 #define BCM6368_CPU_ID 0x6368 20 21 void __init bcm63xx_cpu_init(void); 22 u16 __bcm63xx_get_cpu_id(void); 23 u8 bcm63xx_get_cpu_rev(void); 24 unsigned int bcm63xx_get_cpu_freq(void); 25 26 #ifdef CONFIG_BCM63XX_CPU_3368 27 # ifdef bcm63xx_get_cpu_id 28 # undef bcm63xx_get_cpu_id 29 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 30 # define BCMCPU_RUNTIME_DETECT 31 # else 32 # define bcm63xx_get_cpu_id() BCM3368_CPU_ID 33 # endif 34 # define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) 35 #else 36 # define BCMCPU_IS_3368() (0) 37 #endif 38 39 #ifdef CONFIG_BCM63XX_CPU_6328 40 # ifdef bcm63xx_get_cpu_id 41 # undef bcm63xx_get_cpu_id 42 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 43 # define BCMCPU_RUNTIME_DETECT 44 # else 45 # define bcm63xx_get_cpu_id() BCM6328_CPU_ID 46 # endif 47 # define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) 48 #else 49 # define BCMCPU_IS_6328() (0) 50 #endif 51 52 #ifdef CONFIG_BCM63XX_CPU_6338 53 # ifdef bcm63xx_get_cpu_id 54 # undef bcm63xx_get_cpu_id 55 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 56 # define BCMCPU_RUNTIME_DETECT 57 # else 58 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID 59 # endif 60 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 61 #else 62 # define BCMCPU_IS_6338() (0) 63 #endif 64 65 #ifdef CONFIG_BCM63XX_CPU_6345 66 # ifdef bcm63xx_get_cpu_id 67 # undef bcm63xx_get_cpu_id 68 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 69 # define BCMCPU_RUNTIME_DETECT 70 # else 71 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID 72 # endif 73 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 74 #else 75 # define BCMCPU_IS_6345() (0) 76 #endif 77 78 #ifdef CONFIG_BCM63XX_CPU_6348 79 # ifdef bcm63xx_get_cpu_id 80 # undef bcm63xx_get_cpu_id 81 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 82 # define BCMCPU_RUNTIME_DETECT 83 # else 84 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID 85 # endif 86 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 87 #else 88 # define BCMCPU_IS_6348() (0) 89 #endif 90 91 #ifdef CONFIG_BCM63XX_CPU_6358 92 # ifdef bcm63xx_get_cpu_id 93 # undef bcm63xx_get_cpu_id 94 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 95 # define BCMCPU_RUNTIME_DETECT 96 # else 97 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID 98 # endif 99 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 100 #else 101 # define BCMCPU_IS_6358() (0) 102 #endif 103 104 #ifdef CONFIG_BCM63XX_CPU_6362 105 # ifdef bcm63xx_get_cpu_id 106 # undef bcm63xx_get_cpu_id 107 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 108 # define BCMCPU_RUNTIME_DETECT 109 # else 110 # define bcm63xx_get_cpu_id() BCM6362_CPU_ID 111 # endif 112 # define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) 113 #else 114 # define BCMCPU_IS_6362() (0) 115 #endif 116 117 118 #ifdef CONFIG_BCM63XX_CPU_6368 119 # ifdef bcm63xx_get_cpu_id 120 # undef bcm63xx_get_cpu_id 121 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 122 # define BCMCPU_RUNTIME_DETECT 123 # else 124 # define bcm63xx_get_cpu_id() BCM6368_CPU_ID 125 # endif 126 # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) 127 #else 128 # define BCMCPU_IS_6368() (0) 129 #endif 130 131 #ifndef bcm63xx_get_cpu_id 132 #error "No CPU support configured" 133 #endif 134 135 /* 136 * While registers sets are (mostly) the same across 63xx CPU, base 137 * address of these sets do change. 138 */ 139 enum bcm63xx_regs_set { 140 RSET_DSL_LMEM = 0, 141 RSET_PERF, 142 RSET_TIMER, 143 RSET_WDT, 144 RSET_UART0, 145 RSET_UART1, 146 RSET_GPIO, 147 RSET_SPI, 148 RSET_HSSPI, 149 RSET_UDC0, 150 RSET_OHCI0, 151 RSET_OHCI_PRIV, 152 RSET_USBH_PRIV, 153 RSET_USBD, 154 RSET_USBDMA, 155 RSET_MPI, 156 RSET_PCMCIA, 157 RSET_PCIE, 158 RSET_DSL, 159 RSET_ENET0, 160 RSET_ENET1, 161 RSET_ENETDMA, 162 RSET_ENETDMAC, 163 RSET_ENETDMAS, 164 RSET_ENETSW, 165 RSET_EHCI0, 166 RSET_SDRAM, 167 RSET_MEMC, 168 RSET_DDR, 169 RSET_M2M, 170 RSET_ATM, 171 RSET_XTM, 172 RSET_XTMDMA, 173 RSET_XTMDMAC, 174 RSET_XTMDMAS, 175 RSET_PCM, 176 RSET_PCMDMA, 177 RSET_PCMDMAC, 178 RSET_PCMDMAS, 179 RSET_RNG, 180 RSET_MISC 181 }; 182 183 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 184 #define RSET_DSL_SIZE 4096 185 #define RSET_WDT_SIZE 12 186 #define BCM_6338_RSET_SPI_SIZE 64 187 #define BCM_6348_RSET_SPI_SIZE 64 188 #define BCM_6358_RSET_SPI_SIZE 1804 189 #define BCM_6368_RSET_SPI_SIZE 1804 190 #define RSET_ENET_SIZE 2048 191 #define RSET_ENETDMA_SIZE 256 192 #define RSET_6345_ENETDMA_SIZE 64 193 #define RSET_ENETDMAC_SIZE(chans) (16 * (chans)) 194 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 195 #define RSET_ENETSW_SIZE 65536 196 #define RSET_UART_SIZE 24 197 #define RSET_HSSPI_SIZE 1536 198 #define RSET_UDC_SIZE 256 199 #define RSET_OHCI_SIZE 256 200 #define RSET_EHCI_SIZE 256 201 #define RSET_USBD_SIZE 256 202 #define RSET_USBDMA_SIZE 1280 203 #define RSET_PCMCIA_SIZE 12 204 #define RSET_M2M_SIZE 256 205 #define RSET_ATM_SIZE 4096 206 #define RSET_XTM_SIZE 10240 207 #define RSET_XTMDMA_SIZE 256 208 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 209 #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 210 #define RSET_RNG_SIZE 20 211 212 /* 213 * 3368 register sets base address 214 */ 215 #define BCM_3368_DSL_LMEM_BASE (0xdeadbeef) 216 #define BCM_3368_PERF_BASE (0xfff8c000) 217 #define BCM_3368_TIMER_BASE (0xfff8c040) 218 #define BCM_3368_WDT_BASE (0xfff8c080) 219 #define BCM_3368_UART0_BASE (0xfff8c100) 220 #define BCM_3368_UART1_BASE (0xfff8c120) 221 #define BCM_3368_GPIO_BASE (0xfff8c080) 222 #define BCM_3368_SPI_BASE (0xfff8c800) 223 #define BCM_3368_HSSPI_BASE (0xdeadbeef) 224 #define BCM_3368_UDC0_BASE (0xdeadbeef) 225 #define BCM_3368_USBDMA_BASE (0xdeadbeef) 226 #define BCM_3368_OHCI0_BASE (0xdeadbeef) 227 #define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef) 228 #define BCM_3368_USBH_PRIV_BASE (0xdeadbeef) 229 #define BCM_3368_USBD_BASE (0xdeadbeef) 230 #define BCM_3368_MPI_BASE (0xfff80000) 231 #define BCM_3368_PCMCIA_BASE (0xfff80054) 232 #define BCM_3368_PCIE_BASE (0xdeadbeef) 233 #define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef) 234 #define BCM_3368_DSL_BASE (0xdeadbeef) 235 #define BCM_3368_UBUS_BASE (0xdeadbeef) 236 #define BCM_3368_ENET0_BASE (0xfff98000) 237 #define BCM_3368_ENET1_BASE (0xfff98800) 238 #define BCM_3368_ENETDMA_BASE (0xfff99800) 239 #define BCM_3368_ENETDMAC_BASE (0xfff99900) 240 #define BCM_3368_ENETDMAS_BASE (0xfff99a00) 241 #define BCM_3368_ENETSW_BASE (0xdeadbeef) 242 #define BCM_3368_EHCI0_BASE (0xdeadbeef) 243 #define BCM_3368_SDRAM_BASE (0xdeadbeef) 244 #define BCM_3368_MEMC_BASE (0xfff84000) 245 #define BCM_3368_DDR_BASE (0xdeadbeef) 246 #define BCM_3368_M2M_BASE (0xdeadbeef) 247 #define BCM_3368_ATM_BASE (0xdeadbeef) 248 #define BCM_3368_XTM_BASE (0xdeadbeef) 249 #define BCM_3368_XTMDMA_BASE (0xdeadbeef) 250 #define BCM_3368_XTMDMAC_BASE (0xdeadbeef) 251 #define BCM_3368_XTMDMAS_BASE (0xdeadbeef) 252 #define BCM_3368_PCM_BASE (0xfff9c200) 253 #define BCM_3368_PCMDMA_BASE (0xdeadbeef) 254 #define BCM_3368_PCMDMAC_BASE (0xdeadbeef) 255 #define BCM_3368_PCMDMAS_BASE (0xdeadbeef) 256 #define BCM_3368_RNG_BASE (0xdeadbeef) 257 #define BCM_3368_MISC_BASE (0xdeadbeef) 258 259 /* 260 * 6328 register sets base address 261 */ 262 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 263 #define BCM_6328_PERF_BASE (0xb0000000) 264 #define BCM_6328_TIMER_BASE (0xb0000040) 265 #define BCM_6328_WDT_BASE (0xb000005c) 266 #define BCM_6328_UART0_BASE (0xb0000100) 267 #define BCM_6328_UART1_BASE (0xb0000120) 268 #define BCM_6328_GPIO_BASE (0xb0000080) 269 #define BCM_6328_SPI_BASE (0xdeadbeef) 270 #define BCM_6328_HSSPI_BASE (0xb0001000) 271 #define BCM_6328_UDC0_BASE (0xdeadbeef) 272 #define BCM_6328_USBDMA_BASE (0xb000c000) 273 #define BCM_6328_OHCI0_BASE (0xb0002600) 274 #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) 275 #define BCM_6328_USBH_PRIV_BASE (0xb0002700) 276 #define BCM_6328_USBD_BASE (0xb0002400) 277 #define BCM_6328_MPI_BASE (0xdeadbeef) 278 #define BCM_6328_PCMCIA_BASE (0xdeadbeef) 279 #define BCM_6328_PCIE_BASE (0xb0e40000) 280 #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) 281 #define BCM_6328_DSL_BASE (0xb0001900) 282 #define BCM_6328_UBUS_BASE (0xdeadbeef) 283 #define BCM_6328_ENET0_BASE (0xdeadbeef) 284 #define BCM_6328_ENET1_BASE (0xdeadbeef) 285 #define BCM_6328_ENETDMA_BASE (0xb000d800) 286 #define BCM_6328_ENETDMAC_BASE (0xb000da00) 287 #define BCM_6328_ENETDMAS_BASE (0xb000dc00) 288 #define BCM_6328_ENETSW_BASE (0xb0e00000) 289 #define BCM_6328_EHCI0_BASE (0xb0002500) 290 #define BCM_6328_SDRAM_BASE (0xdeadbeef) 291 #define BCM_6328_MEMC_BASE (0xdeadbeef) 292 #define BCM_6328_DDR_BASE (0xb0003000) 293 #define BCM_6328_M2M_BASE (0xdeadbeef) 294 #define BCM_6328_ATM_BASE (0xdeadbeef) 295 #define BCM_6328_XTM_BASE (0xdeadbeef) 296 #define BCM_6328_XTMDMA_BASE (0xb000b800) 297 #define BCM_6328_XTMDMAC_BASE (0xdeadbeef) 298 #define BCM_6328_XTMDMAS_BASE (0xdeadbeef) 299 #define BCM_6328_PCM_BASE (0xb000a800) 300 #define BCM_6328_PCMDMA_BASE (0xdeadbeef) 301 #define BCM_6328_PCMDMAC_BASE (0xdeadbeef) 302 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 303 #define BCM_6328_RNG_BASE (0xdeadbeef) 304 #define BCM_6328_MISC_BASE (0xb0001800) 305 #define BCM_6328_OTP_BASE (0xb0000600) 306 307 /* 308 * 6338 register sets base address 309 */ 310 #define BCM_6338_DSL_LMEM_BASE (0xfff00000) 311 #define BCM_6338_PERF_BASE (0xfffe0000) 312 #define BCM_6338_BB_BASE (0xfffe0100) 313 #define BCM_6338_TIMER_BASE (0xfffe0200) 314 #define BCM_6338_WDT_BASE (0xfffe021c) 315 #define BCM_6338_UART0_BASE (0xfffe0300) 316 #define BCM_6338_UART1_BASE (0xdeadbeef) 317 #define BCM_6338_GPIO_BASE (0xfffe0400) 318 #define BCM_6338_SPI_BASE (0xfffe0c00) 319 #define BCM_6338_HSSPI_BASE (0xdeadbeef) 320 #define BCM_6338_UDC0_BASE (0xdeadbeef) 321 #define BCM_6338_USBDMA_BASE (0xfffe2400) 322 #define BCM_6338_OHCI0_BASE (0xdeadbeef) 323 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 324 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 325 #define BCM_6338_USBD_BASE (0xdeadbeef) 326 #define BCM_6338_MPI_BASE (0xfffe3160) 327 #define BCM_6338_PCMCIA_BASE (0xdeadbeef) 328 #define BCM_6338_PCIE_BASE (0xdeadbeef) 329 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 330 #define BCM_6338_DSL_BASE (0xfffe1000) 331 #define BCM_6338_UBUS_BASE (0xdeadbeef) 332 #define BCM_6338_ENET0_BASE (0xfffe2800) 333 #define BCM_6338_ENET1_BASE (0xdeadbeef) 334 #define BCM_6338_ENETDMA_BASE (0xfffe2400) 335 #define BCM_6338_ENETDMAC_BASE (0xfffe2500) 336 #define BCM_6338_ENETDMAS_BASE (0xfffe2600) 337 #define BCM_6338_ENETSW_BASE (0xdeadbeef) 338 #define BCM_6338_EHCI0_BASE (0xdeadbeef) 339 #define BCM_6338_SDRAM_BASE (0xfffe3100) 340 #define BCM_6338_MEMC_BASE (0xdeadbeef) 341 #define BCM_6338_DDR_BASE (0xdeadbeef) 342 #define BCM_6338_M2M_BASE (0xdeadbeef) 343 #define BCM_6338_ATM_BASE (0xfffe2000) 344 #define BCM_6338_XTM_BASE (0xdeadbeef) 345 #define BCM_6338_XTMDMA_BASE (0xdeadbeef) 346 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef) 347 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef) 348 #define BCM_6338_PCM_BASE (0xdeadbeef) 349 #define BCM_6338_PCMDMA_BASE (0xdeadbeef) 350 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 351 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 352 #define BCM_6338_RNG_BASE (0xdeadbeef) 353 #define BCM_6338_MISC_BASE (0xdeadbeef) 354 355 /* 356 * 6345 register sets base address 357 */ 358 #define BCM_6345_DSL_LMEM_BASE (0xfff00000) 359 #define BCM_6345_PERF_BASE (0xfffe0000) 360 #define BCM_6345_BB_BASE (0xfffe0100) 361 #define BCM_6345_TIMER_BASE (0xfffe0200) 362 #define BCM_6345_WDT_BASE (0xfffe021c) 363 #define BCM_6345_UART0_BASE (0xfffe0300) 364 #define BCM_6345_UART1_BASE (0xdeadbeef) 365 #define BCM_6345_GPIO_BASE (0xfffe0400) 366 #define BCM_6345_SPI_BASE (0xdeadbeef) 367 #define BCM_6345_HSSPI_BASE (0xdeadbeef) 368 #define BCM_6345_UDC0_BASE (0xdeadbeef) 369 #define BCM_6345_USBDMA_BASE (0xfffe2800) 370 #define BCM_6345_ENET0_BASE (0xfffe1800) 371 #define BCM_6345_ENETDMA_BASE (0xfffe2800) 372 #define BCM_6345_ENETDMAC_BASE (0xfffe2840) 373 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 374 #define BCM_6345_ENETSW_BASE (0xdeadbeef) 375 #define BCM_6345_PCMCIA_BASE (0xfffe2028) 376 #define BCM_6345_MPI_BASE (0xfffe2000) 377 #define BCM_6345_PCIE_BASE (0xdeadbeef) 378 #define BCM_6345_OHCI0_BASE (0xfffe2100) 379 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 380 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 381 #define BCM_6345_USBD_BASE (0xdeadbeef) 382 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 383 #define BCM_6345_DSL_BASE (0xdeadbeef) 384 #define BCM_6345_UBUS_BASE (0xdeadbeef) 385 #define BCM_6345_ENET1_BASE (0xdeadbeef) 386 #define BCM_6345_EHCI0_BASE (0xdeadbeef) 387 #define BCM_6345_SDRAM_BASE (0xfffe2300) 388 #define BCM_6345_MEMC_BASE (0xdeadbeef) 389 #define BCM_6345_DDR_BASE (0xdeadbeef) 390 #define BCM_6345_M2M_BASE (0xdeadbeef) 391 #define BCM_6345_ATM_BASE (0xfffe4000) 392 #define BCM_6345_XTM_BASE (0xdeadbeef) 393 #define BCM_6345_XTMDMA_BASE (0xdeadbeef) 394 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef) 395 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef) 396 #define BCM_6345_PCM_BASE (0xdeadbeef) 397 #define BCM_6345_PCMDMA_BASE (0xdeadbeef) 398 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 399 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 400 #define BCM_6345_RNG_BASE (0xdeadbeef) 401 #define BCM_6345_MISC_BASE (0xdeadbeef) 402 403 /* 404 * 6348 register sets base address 405 */ 406 #define BCM_6348_DSL_LMEM_BASE (0xfff00000) 407 #define BCM_6348_PERF_BASE (0xfffe0000) 408 #define BCM_6348_TIMER_BASE (0xfffe0200) 409 #define BCM_6348_WDT_BASE (0xfffe021c) 410 #define BCM_6348_UART0_BASE (0xfffe0300) 411 #define BCM_6348_UART1_BASE (0xdeadbeef) 412 #define BCM_6348_GPIO_BASE (0xfffe0400) 413 #define BCM_6348_SPI_BASE (0xfffe0c00) 414 #define BCM_6348_HSSPI_BASE (0xdeadbeef) 415 #define BCM_6348_UDC0_BASE (0xfffe1000) 416 #define BCM_6348_USBDMA_BASE (0xdeadbeef) 417 #define BCM_6348_OHCI0_BASE (0xfffe1b00) 418 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 419 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 420 #define BCM_6348_USBD_BASE (0xdeadbeef) 421 #define BCM_6348_MPI_BASE (0xfffe2000) 422 #define BCM_6348_PCMCIA_BASE (0xfffe2054) 423 #define BCM_6348_PCIE_BASE (0xdeadbeef) 424 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 425 #define BCM_6348_M2M_BASE (0xfffe2800) 426 #define BCM_6348_DSL_BASE (0xfffe3000) 427 #define BCM_6348_ENET0_BASE (0xfffe6000) 428 #define BCM_6348_ENET1_BASE (0xfffe6800) 429 #define BCM_6348_ENETDMA_BASE (0xfffe7000) 430 #define BCM_6348_ENETDMAC_BASE (0xfffe7100) 431 #define BCM_6348_ENETDMAS_BASE (0xfffe7200) 432 #define BCM_6348_ENETSW_BASE (0xdeadbeef) 433 #define BCM_6348_EHCI0_BASE (0xdeadbeef) 434 #define BCM_6348_SDRAM_BASE (0xfffe2300) 435 #define BCM_6348_MEMC_BASE (0xdeadbeef) 436 #define BCM_6348_DDR_BASE (0xdeadbeef) 437 #define BCM_6348_ATM_BASE (0xfffe4000) 438 #define BCM_6348_XTM_BASE (0xdeadbeef) 439 #define BCM_6348_XTMDMA_BASE (0xdeadbeef) 440 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef) 441 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef) 442 #define BCM_6348_PCM_BASE (0xdeadbeef) 443 #define BCM_6348_PCMDMA_BASE (0xdeadbeef) 444 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 445 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 446 #define BCM_6348_RNG_BASE (0xdeadbeef) 447 #define BCM_6348_MISC_BASE (0xdeadbeef) 448 449 /* 450 * 6358 register sets base address 451 */ 452 #define BCM_6358_DSL_LMEM_BASE (0xfff00000) 453 #define BCM_6358_PERF_BASE (0xfffe0000) 454 #define BCM_6358_TIMER_BASE (0xfffe0040) 455 #define BCM_6358_WDT_BASE (0xfffe005c) 456 #define BCM_6358_UART0_BASE (0xfffe0100) 457 #define BCM_6358_UART1_BASE (0xfffe0120) 458 #define BCM_6358_GPIO_BASE (0xfffe0080) 459 #define BCM_6358_SPI_BASE (0xfffe0800) 460 #define BCM_6358_HSSPI_BASE (0xdeadbeef) 461 #define BCM_6358_UDC0_BASE (0xfffe0800) 462 #define BCM_6358_USBDMA_BASE (0xdeadbeef) 463 #define BCM_6358_OHCI0_BASE (0xfffe1400) 464 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 465 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 466 #define BCM_6358_USBD_BASE (0xdeadbeef) 467 #define BCM_6358_MPI_BASE (0xfffe1000) 468 #define BCM_6358_PCMCIA_BASE (0xfffe1054) 469 #define BCM_6358_PCIE_BASE (0xdeadbeef) 470 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 471 #define BCM_6358_M2M_BASE (0xdeadbeef) 472 #define BCM_6358_DSL_BASE (0xfffe3000) 473 #define BCM_6358_ENET0_BASE (0xfffe4000) 474 #define BCM_6358_ENET1_BASE (0xfffe4800) 475 #define BCM_6358_ENETDMA_BASE (0xfffe5000) 476 #define BCM_6358_ENETDMAC_BASE (0xfffe5100) 477 #define BCM_6358_ENETDMAS_BASE (0xfffe5200) 478 #define BCM_6358_ENETSW_BASE (0xdeadbeef) 479 #define BCM_6358_EHCI0_BASE (0xfffe1300) 480 #define BCM_6358_SDRAM_BASE (0xdeadbeef) 481 #define BCM_6358_MEMC_BASE (0xfffe1200) 482 #define BCM_6358_DDR_BASE (0xfffe12a0) 483 #define BCM_6358_ATM_BASE (0xfffe2000) 484 #define BCM_6358_XTM_BASE (0xdeadbeef) 485 #define BCM_6358_XTMDMA_BASE (0xdeadbeef) 486 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef) 487 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef) 488 #define BCM_6358_PCM_BASE (0xfffe1600) 489 #define BCM_6358_PCMDMA_BASE (0xfffe1800) 490 #define BCM_6358_PCMDMAC_BASE (0xfffe1900) 491 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 492 #define BCM_6358_RNG_BASE (0xdeadbeef) 493 #define BCM_6358_MISC_BASE (0xdeadbeef) 494 495 496 /* 497 * 6362 register sets base address 498 */ 499 #define BCM_6362_DSL_LMEM_BASE (0xdeadbeef) 500 #define BCM_6362_PERF_BASE (0xb0000000) 501 #define BCM_6362_TIMER_BASE (0xb0000040) 502 #define BCM_6362_WDT_BASE (0xb000005c) 503 #define BCM_6362_UART0_BASE (0xb0000100) 504 #define BCM_6362_UART1_BASE (0xb0000120) 505 #define BCM_6362_GPIO_BASE (0xb0000080) 506 #define BCM_6362_SPI_BASE (0xb0000800) 507 #define BCM_6362_HSSPI_BASE (0xb0001000) 508 #define BCM_6362_UDC0_BASE (0xdeadbeef) 509 #define BCM_6362_USBDMA_BASE (0xb000c000) 510 #define BCM_6362_OHCI0_BASE (0xb0002600) 511 #define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) 512 #define BCM_6362_USBH_PRIV_BASE (0xb0002700) 513 #define BCM_6362_USBD_BASE (0xb0002400) 514 #define BCM_6362_MPI_BASE (0xdeadbeef) 515 #define BCM_6362_PCMCIA_BASE (0xdeadbeef) 516 #define BCM_6362_PCIE_BASE (0xb0e40000) 517 #define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef) 518 #define BCM_6362_DSL_BASE (0xdeadbeef) 519 #define BCM_6362_UBUS_BASE (0xdeadbeef) 520 #define BCM_6362_ENET0_BASE (0xdeadbeef) 521 #define BCM_6362_ENET1_BASE (0xdeadbeef) 522 #define BCM_6362_ENETDMA_BASE (0xb000d800) 523 #define BCM_6362_ENETDMAC_BASE (0xb000da00) 524 #define BCM_6362_ENETDMAS_BASE (0xb000dc00) 525 #define BCM_6362_ENETSW_BASE (0xb0e00000) 526 #define BCM_6362_EHCI0_BASE (0xb0002500) 527 #define BCM_6362_SDRAM_BASE (0xdeadbeef) 528 #define BCM_6362_MEMC_BASE (0xdeadbeef) 529 #define BCM_6362_DDR_BASE (0xb0003000) 530 #define BCM_6362_M2M_BASE (0xdeadbeef) 531 #define BCM_6362_ATM_BASE (0xdeadbeef) 532 #define BCM_6362_XTM_BASE (0xb0007800) 533 #define BCM_6362_XTMDMA_BASE (0xb000b800) 534 #define BCM_6362_XTMDMAC_BASE (0xdeadbeef) 535 #define BCM_6362_XTMDMAS_BASE (0xdeadbeef) 536 #define BCM_6362_PCM_BASE (0xb000a800) 537 #define BCM_6362_PCMDMA_BASE (0xdeadbeef) 538 #define BCM_6362_PCMDMAC_BASE (0xdeadbeef) 539 #define BCM_6362_PCMDMAS_BASE (0xdeadbeef) 540 #define BCM_6362_RNG_BASE (0xdeadbeef) 541 #define BCM_6362_MISC_BASE (0xb0001800) 542 543 #define BCM_6362_NAND_REG_BASE (0xb0000200) 544 #define BCM_6362_NAND_CACHE_BASE (0xb0000600) 545 #define BCM_6362_LED_BASE (0xb0001900) 546 #define BCM_6362_IPSEC_BASE (0xb0002800) 547 #define BCM_6362_IPSEC_DMA_BASE (0xb000d000) 548 #define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000) 549 #define BCM_6362_WLAN_D11_BASE (0xb0005000) 550 #define BCM_6362_WLAN_SHIM_BASE (0xb0007000) 551 552 /* 553 * 6368 register sets base address 554 */ 555 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) 556 #define BCM_6368_PERF_BASE (0xb0000000) 557 #define BCM_6368_TIMER_BASE (0xb0000040) 558 #define BCM_6368_WDT_BASE (0xb000005c) 559 #define BCM_6368_UART0_BASE (0xb0000100) 560 #define BCM_6368_UART1_BASE (0xb0000120) 561 #define BCM_6368_GPIO_BASE (0xb0000080) 562 #define BCM_6368_SPI_BASE (0xb0000800) 563 #define BCM_6368_HSSPI_BASE (0xdeadbeef) 564 #define BCM_6368_UDC0_BASE (0xdeadbeef) 565 #define BCM_6368_USBDMA_BASE (0xb0004800) 566 #define BCM_6368_OHCI0_BASE (0xb0001600) 567 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 568 #define BCM_6368_USBH_PRIV_BASE (0xb0001700) 569 #define BCM_6368_USBD_BASE (0xb0001400) 570 #define BCM_6368_MPI_BASE (0xb0001000) 571 #define BCM_6368_PCMCIA_BASE (0xb0001054) 572 #define BCM_6368_PCIE_BASE (0xdeadbeef) 573 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 574 #define BCM_6368_M2M_BASE (0xdeadbeef) 575 #define BCM_6368_DSL_BASE (0xdeadbeef) 576 #define BCM_6368_ENET0_BASE (0xdeadbeef) 577 #define BCM_6368_ENET1_BASE (0xdeadbeef) 578 #define BCM_6368_ENETDMA_BASE (0xb0006800) 579 #define BCM_6368_ENETDMAC_BASE (0xb0006a00) 580 #define BCM_6368_ENETDMAS_BASE (0xb0006c00) 581 #define BCM_6368_ENETSW_BASE (0xb0f00000) 582 #define BCM_6368_EHCI0_BASE (0xb0001500) 583 #define BCM_6368_SDRAM_BASE (0xdeadbeef) 584 #define BCM_6368_MEMC_BASE (0xb0001200) 585 #define BCM_6368_DDR_BASE (0xb0001280) 586 #define BCM_6368_ATM_BASE (0xdeadbeef) 587 #define BCM_6368_XTM_BASE (0xb0001800) 588 #define BCM_6368_XTMDMA_BASE (0xb0005000) 589 #define BCM_6368_XTMDMAC_BASE (0xb0005200) 590 #define BCM_6368_XTMDMAS_BASE (0xb0005400) 591 #define BCM_6368_PCM_BASE (0xb0004000) 592 #define BCM_6368_PCMDMA_BASE (0xb0005800) 593 #define BCM_6368_PCMDMAC_BASE (0xb0005a00) 594 #define BCM_6368_PCMDMAS_BASE (0xb0005c00) 595 #define BCM_6368_RNG_BASE (0xb0004180) 596 #define BCM_6368_MISC_BASE (0xdeadbeef) 597 598 599 extern const unsigned long *bcm63xx_regs_base; 600 601 #define __GEN_RSET_BASE(__cpu, __rset) \ 602 case RSET_## __rset : \ 603 return BCM_## __cpu ##_## __rset ##_BASE; 604 605 #define __GEN_RSET(__cpu) \ 606 switch (set) { \ 607 __GEN_RSET_BASE(__cpu, DSL_LMEM) \ 608 __GEN_RSET_BASE(__cpu, PERF) \ 609 __GEN_RSET_BASE(__cpu, TIMER) \ 610 __GEN_RSET_BASE(__cpu, WDT) \ 611 __GEN_RSET_BASE(__cpu, UART0) \ 612 __GEN_RSET_BASE(__cpu, UART1) \ 613 __GEN_RSET_BASE(__cpu, GPIO) \ 614 __GEN_RSET_BASE(__cpu, SPI) \ 615 __GEN_RSET_BASE(__cpu, HSSPI) \ 616 __GEN_RSET_BASE(__cpu, UDC0) \ 617 __GEN_RSET_BASE(__cpu, OHCI0) \ 618 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 619 __GEN_RSET_BASE(__cpu, USBH_PRIV) \ 620 __GEN_RSET_BASE(__cpu, USBD) \ 621 __GEN_RSET_BASE(__cpu, USBDMA) \ 622 __GEN_RSET_BASE(__cpu, MPI) \ 623 __GEN_RSET_BASE(__cpu, PCMCIA) \ 624 __GEN_RSET_BASE(__cpu, PCIE) \ 625 __GEN_RSET_BASE(__cpu, DSL) \ 626 __GEN_RSET_BASE(__cpu, ENET0) \ 627 __GEN_RSET_BASE(__cpu, ENET1) \ 628 __GEN_RSET_BASE(__cpu, ENETDMA) \ 629 __GEN_RSET_BASE(__cpu, ENETDMAC) \ 630 __GEN_RSET_BASE(__cpu, ENETDMAS) \ 631 __GEN_RSET_BASE(__cpu, ENETSW) \ 632 __GEN_RSET_BASE(__cpu, EHCI0) \ 633 __GEN_RSET_BASE(__cpu, SDRAM) \ 634 __GEN_RSET_BASE(__cpu, MEMC) \ 635 __GEN_RSET_BASE(__cpu, DDR) \ 636 __GEN_RSET_BASE(__cpu, M2M) \ 637 __GEN_RSET_BASE(__cpu, ATM) \ 638 __GEN_RSET_BASE(__cpu, XTM) \ 639 __GEN_RSET_BASE(__cpu, XTMDMA) \ 640 __GEN_RSET_BASE(__cpu, XTMDMAC) \ 641 __GEN_RSET_BASE(__cpu, XTMDMAS) \ 642 __GEN_RSET_BASE(__cpu, PCM) \ 643 __GEN_RSET_BASE(__cpu, PCMDMA) \ 644 __GEN_RSET_BASE(__cpu, PCMDMAC) \ 645 __GEN_RSET_BASE(__cpu, PCMDMAS) \ 646 __GEN_RSET_BASE(__cpu, RNG) \ 647 __GEN_RSET_BASE(__cpu, MISC) \ 648 } 649 650 #define __GEN_CPU_REGS_TABLE(__cpu) \ 651 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ 652 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ 653 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ 654 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ 655 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ 656 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 657 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 658 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 659 [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \ 660 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 661 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 662 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 663 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 664 [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ 665 [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ 666 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 667 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 668 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ 669 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 670 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 671 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 672 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ 673 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ 674 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ 675 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ 676 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ 677 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ 678 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ 679 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ 680 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ 681 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ 682 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ 683 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ 684 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ 685 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ 686 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ 687 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 688 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 689 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 690 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ 691 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ 692 693 694 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 695 { 696 #ifdef BCMCPU_RUNTIME_DETECT 697 return bcm63xx_regs_base[set]; 698 #else 699 #ifdef CONFIG_BCM63XX_CPU_3368 700 __GEN_RSET(3368) 701 #endif 702 #ifdef CONFIG_BCM63XX_CPU_6328 703 __GEN_RSET(6328) 704 #endif 705 #ifdef CONFIG_BCM63XX_CPU_6338 706 __GEN_RSET(6338) 707 #endif 708 #ifdef CONFIG_BCM63XX_CPU_6345 709 __GEN_RSET(6345) 710 #endif 711 #ifdef CONFIG_BCM63XX_CPU_6348 712 __GEN_RSET(6348) 713 #endif 714 #ifdef CONFIG_BCM63XX_CPU_6358 715 __GEN_RSET(6358) 716 #endif 717 #ifdef CONFIG_BCM63XX_CPU_6362 718 __GEN_RSET(6362) 719 #endif 720 #ifdef CONFIG_BCM63XX_CPU_6368 721 __GEN_RSET(6368) 722 #endif 723 #endif 724 /* unreached */ 725 return 0; 726 } 727 728 /* 729 * IRQ number changes across CPU too 730 */ 731 enum bcm63xx_irq { 732 IRQ_TIMER = 0, 733 IRQ_SPI, 734 IRQ_UART0, 735 IRQ_UART1, 736 IRQ_DSL, 737 IRQ_ENET0, 738 IRQ_ENET1, 739 IRQ_ENET_PHY, 740 IRQ_HSSPI, 741 IRQ_OHCI0, 742 IRQ_EHCI0, 743 IRQ_USBD, 744 IRQ_USBD_RXDMA0, 745 IRQ_USBD_TXDMA0, 746 IRQ_USBD_RXDMA1, 747 IRQ_USBD_TXDMA1, 748 IRQ_USBD_RXDMA2, 749 IRQ_USBD_TXDMA2, 750 IRQ_ENET0_RXDMA, 751 IRQ_ENET0_TXDMA, 752 IRQ_ENET1_RXDMA, 753 IRQ_ENET1_TXDMA, 754 IRQ_PCI, 755 IRQ_PCMCIA, 756 IRQ_ATM, 757 IRQ_ENETSW_RXDMA0, 758 IRQ_ENETSW_RXDMA1, 759 IRQ_ENETSW_RXDMA2, 760 IRQ_ENETSW_RXDMA3, 761 IRQ_ENETSW_TXDMA0, 762 IRQ_ENETSW_TXDMA1, 763 IRQ_ENETSW_TXDMA2, 764 IRQ_ENETSW_TXDMA3, 765 IRQ_XTM, 766 IRQ_XTM_DMA0, 767 }; 768 769 /* 770 * 3368 irqs 771 */ 772 #define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 773 #define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 774 #define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 775 #define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 776 #define BCM_3368_DSL_IRQ 0 777 #define BCM_3368_UDC0_IRQ 0 778 #define BCM_3368_OHCI0_IRQ 0 779 #define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 780 #define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 781 #define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 782 #define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 783 #define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 784 #define BCM_3368_HSSPI_IRQ 0 785 #define BCM_3368_EHCI0_IRQ 0 786 #define BCM_3368_USBD_IRQ 0 787 #define BCM_3368_USBD_RXDMA0_IRQ 0 788 #define BCM_3368_USBD_TXDMA0_IRQ 0 789 #define BCM_3368_USBD_RXDMA1_IRQ 0 790 #define BCM_3368_USBD_TXDMA1_IRQ 0 791 #define BCM_3368_USBD_RXDMA2_IRQ 0 792 #define BCM_3368_USBD_TXDMA2_IRQ 0 793 #define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 794 #define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 795 #define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 796 #define BCM_3368_PCMCIA_IRQ 0 797 #define BCM_3368_ATM_IRQ 0 798 #define BCM_3368_ENETSW_RXDMA0_IRQ 0 799 #define BCM_3368_ENETSW_RXDMA1_IRQ 0 800 #define BCM_3368_ENETSW_RXDMA2_IRQ 0 801 #define BCM_3368_ENETSW_RXDMA3_IRQ 0 802 #define BCM_3368_ENETSW_TXDMA0_IRQ 0 803 #define BCM_3368_ENETSW_TXDMA1_IRQ 0 804 #define BCM_3368_ENETSW_TXDMA2_IRQ 0 805 #define BCM_3368_ENETSW_TXDMA3_IRQ 0 806 #define BCM_3368_XTM_IRQ 0 807 #define BCM_3368_XTM_DMA0_IRQ 0 808 809 #define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 810 #define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 811 #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 812 #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 813 814 815 /* 816 * 6328 irqs 817 */ 818 #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 819 820 #define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) 821 #define BCM_6328_SPI_IRQ 0 822 #define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28) 823 #define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) 824 #define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 825 #define BCM_6328_UDC0_IRQ 0 826 #define BCM_6328_ENET0_IRQ 0 827 #define BCM_6328_ENET1_IRQ 0 828 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 829 #define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) 830 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 831 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 832 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) 833 #define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) 834 #define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) 835 #define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) 836 #define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) 837 #define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) 838 #define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) 839 #define BCM_6328_PCMCIA_IRQ 0 840 #define BCM_6328_ENET0_RXDMA_IRQ 0 841 #define BCM_6328_ENET0_TXDMA_IRQ 0 842 #define BCM_6328_ENET1_RXDMA_IRQ 0 843 #define BCM_6328_ENET1_TXDMA_IRQ 0 844 #define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23) 845 #define BCM_6328_ATM_IRQ 0 846 #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0) 847 #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) 848 #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) 849 #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) 850 #define BCM_6328_ENETSW_TXDMA0_IRQ 0 851 #define BCM_6328_ENETSW_TXDMA1_IRQ 0 852 #define BCM_6328_ENETSW_TXDMA2_IRQ 0 853 #define BCM_6328_ENETSW_TXDMA3_IRQ 0 854 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) 855 #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) 856 857 #define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) 858 #define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) 859 #define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) 860 #define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) 861 #define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) 862 #define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) 863 864 /* 865 * 6338 irqs 866 */ 867 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 868 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 869 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 870 #define BCM_6338_UART1_IRQ 0 871 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 872 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 873 #define BCM_6338_ENET1_IRQ 0 874 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 875 #define BCM_6338_HSSPI_IRQ 0 876 #define BCM_6338_OHCI0_IRQ 0 877 #define BCM_6338_EHCI0_IRQ 0 878 #define BCM_6338_USBD_IRQ 0 879 #define BCM_6338_USBD_RXDMA0_IRQ 0 880 #define BCM_6338_USBD_TXDMA0_IRQ 0 881 #define BCM_6338_USBD_RXDMA1_IRQ 0 882 #define BCM_6338_USBD_TXDMA1_IRQ 0 883 #define BCM_6338_USBD_RXDMA2_IRQ 0 884 #define BCM_6338_USBD_TXDMA2_IRQ 0 885 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 886 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 887 #define BCM_6338_ENET1_RXDMA_IRQ 0 888 #define BCM_6338_ENET1_TXDMA_IRQ 0 889 #define BCM_6338_PCI_IRQ 0 890 #define BCM_6338_PCMCIA_IRQ 0 891 #define BCM_6338_ATM_IRQ 0 892 #define BCM_6338_ENETSW_RXDMA0_IRQ 0 893 #define BCM_6338_ENETSW_RXDMA1_IRQ 0 894 #define BCM_6338_ENETSW_RXDMA2_IRQ 0 895 #define BCM_6338_ENETSW_RXDMA3_IRQ 0 896 #define BCM_6338_ENETSW_TXDMA0_IRQ 0 897 #define BCM_6338_ENETSW_TXDMA1_IRQ 0 898 #define BCM_6338_ENETSW_TXDMA2_IRQ 0 899 #define BCM_6338_ENETSW_TXDMA3_IRQ 0 900 #define BCM_6338_XTM_IRQ 0 901 #define BCM_6338_XTM_DMA0_IRQ 0 902 903 /* 904 * 6345 irqs 905 */ 906 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 907 #define BCM_6345_SPI_IRQ 0 908 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 909 #define BCM_6345_UART1_IRQ 0 910 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 911 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 912 #define BCM_6345_ENET1_IRQ 0 913 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 914 #define BCM_6345_HSSPI_IRQ 0 915 #define BCM_6345_OHCI0_IRQ 0 916 #define BCM_6345_EHCI0_IRQ 0 917 #define BCM_6345_USBD_IRQ 0 918 #define BCM_6345_USBD_RXDMA0_IRQ 0 919 #define BCM_6345_USBD_TXDMA0_IRQ 0 920 #define BCM_6345_USBD_RXDMA1_IRQ 0 921 #define BCM_6345_USBD_TXDMA1_IRQ 0 922 #define BCM_6345_USBD_RXDMA2_IRQ 0 923 #define BCM_6345_USBD_TXDMA2_IRQ 0 924 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 925 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 926 #define BCM_6345_ENET1_RXDMA_IRQ 0 927 #define BCM_6345_ENET1_TXDMA_IRQ 0 928 #define BCM_6345_PCI_IRQ 0 929 #define BCM_6345_PCMCIA_IRQ 0 930 #define BCM_6345_ATM_IRQ 0 931 #define BCM_6345_ENETSW_RXDMA0_IRQ 0 932 #define BCM_6345_ENETSW_RXDMA1_IRQ 0 933 #define BCM_6345_ENETSW_RXDMA2_IRQ 0 934 #define BCM_6345_ENETSW_RXDMA3_IRQ 0 935 #define BCM_6345_ENETSW_TXDMA0_IRQ 0 936 #define BCM_6345_ENETSW_TXDMA1_IRQ 0 937 #define BCM_6345_ENETSW_TXDMA2_IRQ 0 938 #define BCM_6345_ENETSW_TXDMA3_IRQ 0 939 #define BCM_6345_XTM_IRQ 0 940 #define BCM_6345_XTM_DMA0_IRQ 0 941 942 /* 943 * 6348 irqs 944 */ 945 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 946 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 947 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 948 #define BCM_6348_UART1_IRQ 0 949 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 950 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 951 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 952 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 953 #define BCM_6348_HSSPI_IRQ 0 954 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 955 #define BCM_6348_EHCI0_IRQ 0 956 #define BCM_6348_USBD_IRQ 0 957 #define BCM_6348_USBD_RXDMA0_IRQ 0 958 #define BCM_6348_USBD_TXDMA0_IRQ 0 959 #define BCM_6348_USBD_RXDMA1_IRQ 0 960 #define BCM_6348_USBD_TXDMA1_IRQ 0 961 #define BCM_6348_USBD_RXDMA2_IRQ 0 962 #define BCM_6348_USBD_TXDMA2_IRQ 0 963 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 964 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 965 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 966 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 967 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 968 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 969 #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) 970 #define BCM_6348_ENETSW_RXDMA0_IRQ 0 971 #define BCM_6348_ENETSW_RXDMA1_IRQ 0 972 #define BCM_6348_ENETSW_RXDMA2_IRQ 0 973 #define BCM_6348_ENETSW_RXDMA3_IRQ 0 974 #define BCM_6348_ENETSW_TXDMA0_IRQ 0 975 #define BCM_6348_ENETSW_TXDMA1_IRQ 0 976 #define BCM_6348_ENETSW_TXDMA2_IRQ 0 977 #define BCM_6348_ENETSW_TXDMA3_IRQ 0 978 #define BCM_6348_XTM_IRQ 0 979 #define BCM_6348_XTM_DMA0_IRQ 0 980 981 /* 982 * 6358 irqs 983 */ 984 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 985 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 986 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 987 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 988 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 989 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 990 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 991 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 992 #define BCM_6358_HSSPI_IRQ 0 993 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 994 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 995 #define BCM_6358_USBD_IRQ 0 996 #define BCM_6358_USBD_RXDMA0_IRQ 0 997 #define BCM_6358_USBD_TXDMA0_IRQ 0 998 #define BCM_6358_USBD_RXDMA1_IRQ 0 999 #define BCM_6358_USBD_TXDMA1_IRQ 0 1000 #define BCM_6358_USBD_RXDMA2_IRQ 0 1001 #define BCM_6358_USBD_TXDMA2_IRQ 0 1002 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 1003 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 1004 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 1005 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 1006 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 1007 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 1008 #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) 1009 #define BCM_6358_ENETSW_RXDMA0_IRQ 0 1010 #define BCM_6358_ENETSW_RXDMA1_IRQ 0 1011 #define BCM_6358_ENETSW_RXDMA2_IRQ 0 1012 #define BCM_6358_ENETSW_RXDMA3_IRQ 0 1013 #define BCM_6358_ENETSW_TXDMA0_IRQ 0 1014 #define BCM_6358_ENETSW_TXDMA1_IRQ 0 1015 #define BCM_6358_ENETSW_TXDMA2_IRQ 0 1016 #define BCM_6358_ENETSW_TXDMA3_IRQ 0 1017 #define BCM_6358_XTM_IRQ 0 1018 #define BCM_6358_XTM_DMA0_IRQ 0 1019 1020 #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) 1021 #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) 1022 #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 1023 #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 1024 #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 1025 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 1026 1027 /* 1028 * 6362 irqs 1029 */ 1030 #define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 1031 1032 #define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 1033 #define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2) 1034 #define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) 1035 #define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) 1036 #define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28) 1037 #define BCM_6362_UDC0_IRQ 0 1038 #define BCM_6362_ENET0_IRQ 0 1039 #define BCM_6362_ENET1_IRQ 0 1040 #define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14) 1041 #define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5) 1042 #define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) 1043 #define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 1044 #define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11) 1045 #define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20) 1046 #define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21) 1047 #define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22) 1048 #define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23) 1049 #define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24) 1050 #define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25) 1051 #define BCM_6362_PCMCIA_IRQ 0 1052 #define BCM_6362_ENET0_RXDMA_IRQ 0 1053 #define BCM_6362_ENET0_TXDMA_IRQ 0 1054 #define BCM_6362_ENET1_RXDMA_IRQ 0 1055 #define BCM_6362_ENET1_TXDMA_IRQ 0 1056 #define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30) 1057 #define BCM_6362_ATM_IRQ 0 1058 #define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0) 1059 #define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1) 1060 #define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2) 1061 #define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3) 1062 #define BCM_6362_ENETSW_TXDMA0_IRQ 0 1063 #define BCM_6362_ENETSW_TXDMA1_IRQ 0 1064 #define BCM_6362_ENETSW_TXDMA2_IRQ 0 1065 #define BCM_6362_ENETSW_TXDMA3_IRQ 0 1066 #define BCM_6362_XTM_IRQ 0 1067 #define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12) 1068 1069 #define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1) 1070 #define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6) 1071 #define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) 1072 #define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) 1073 #define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12) 1074 #define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13) 1075 #define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15) 1076 #define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) 1077 #define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) 1078 #define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) 1079 #define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) 1080 #define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) 1081 #define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27) 1082 #define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29) 1083 #define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4) 1084 #define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5) 1085 #define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6) 1086 #define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7) 1087 #define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8) 1088 #define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9) 1089 #define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10) 1090 #define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11) 1091 1092 /* 1093 * 6368 irqs 1094 */ 1095 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 1096 1097 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 1098 #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 1099 #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 1100 #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 1101 #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 1102 #define BCM_6368_ENET0_IRQ 0 1103 #define BCM_6368_ENET1_IRQ 0 1104 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 1105 #define BCM_6368_HSSPI_IRQ 0 1106 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 1107 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 1108 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) 1109 #define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) 1110 #define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) 1111 #define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) 1112 #define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) 1113 #define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) 1114 #define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) 1115 #define BCM_6368_PCMCIA_IRQ 0 1116 #define BCM_6368_ENET0_RXDMA_IRQ 0 1117 #define BCM_6368_ENET0_TXDMA_IRQ 0 1118 #define BCM_6368_ENET1_RXDMA_IRQ 0 1119 #define BCM_6368_ENET1_TXDMA_IRQ 0 1120 #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) 1121 #define BCM_6368_ATM_IRQ 0 1122 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) 1123 #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) 1124 #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) 1125 #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) 1126 #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) 1127 #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) 1128 #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) 1129 #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) 1130 #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) 1131 #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) 1132 1133 #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) 1134 #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) 1135 #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) 1136 #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) 1137 #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) 1138 #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) 1139 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) 1140 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) 1141 1142 extern const int *bcm63xx_irqs; 1143 1144 #define __GEN_CPU_IRQ_TABLE(__cpu) \ 1145 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 1146 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ 1147 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 1148 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 1149 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 1150 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1151 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1152 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1153 [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \ 1154 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1155 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1156 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ 1157 [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ 1158 [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ 1159 [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ 1160 [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ 1161 [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ 1162 [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ 1163 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ 1164 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ 1165 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ 1166 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ 1167 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ 1168 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ 1169 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ 1170 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ 1171 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ 1172 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ 1173 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ 1174 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ 1175 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ 1176 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ 1177 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ 1178 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ 1179 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ 1180 1181 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 1182 { 1183 return bcm63xx_irqs[irq]; 1184 } 1185 1186 /* 1187 * return installed memory size 1188 */ 1189 unsigned int bcm63xx_get_memory_size(void); 1190 1191 void bcm63xx_machine_halt(void); 1192 1193 void bcm63xx_machine_reboot(void); 1194 1195 #endif /* !BCM63XX_CPU_H_ */ 1196