1 #ifndef BCM63XX_CPU_H_ 2 #define BCM63XX_CPU_H_ 3 4 #include <linux/types.h> 5 #include <linux/init.h> 6 7 /* 8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 9 * compile time if only one CPU support is enabled (idea stolen from 10 * arm mach-types) 11 */ 12 #define BCM6338_CPU_ID 0x6338 13 #define BCM6345_CPU_ID 0x6345 14 #define BCM6348_CPU_ID 0x6348 15 #define BCM6358_CPU_ID 0x6358 16 17 void __init bcm63xx_cpu_init(void); 18 u16 __bcm63xx_get_cpu_id(void); 19 u16 bcm63xx_get_cpu_rev(void); 20 unsigned int bcm63xx_get_cpu_freq(void); 21 22 #ifdef CONFIG_BCM63XX_CPU_6338 23 # ifdef bcm63xx_get_cpu_id 24 # undef bcm63xx_get_cpu_id 25 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 26 # define BCMCPU_RUNTIME_DETECT 27 # else 28 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID 29 # endif 30 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 31 #else 32 # define BCMCPU_IS_6338() (0) 33 #endif 34 35 #ifdef CONFIG_BCM63XX_CPU_6345 36 # ifdef bcm63xx_get_cpu_id 37 # undef bcm63xx_get_cpu_id 38 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 39 # define BCMCPU_RUNTIME_DETECT 40 # else 41 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID 42 # endif 43 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 44 #else 45 # define BCMCPU_IS_6345() (0) 46 #endif 47 48 #ifdef CONFIG_BCM63XX_CPU_6348 49 # ifdef bcm63xx_get_cpu_id 50 # undef bcm63xx_get_cpu_id 51 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 52 # define BCMCPU_RUNTIME_DETECT 53 # else 54 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID 55 # endif 56 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 57 #else 58 # define BCMCPU_IS_6348() (0) 59 #endif 60 61 #ifdef CONFIG_BCM63XX_CPU_6358 62 # ifdef bcm63xx_get_cpu_id 63 # undef bcm63xx_get_cpu_id 64 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 65 # define BCMCPU_RUNTIME_DETECT 66 # else 67 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID 68 # endif 69 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 70 #else 71 # define BCMCPU_IS_6358() (0) 72 #endif 73 74 #ifndef bcm63xx_get_cpu_id 75 #error "No CPU support configured" 76 #endif 77 78 /* 79 * While registers sets are (mostly) the same across 63xx CPU, base 80 * address of these sets do change. 81 */ 82 enum bcm63xx_regs_set { 83 RSET_DSL_LMEM = 0, 84 RSET_PERF, 85 RSET_TIMER, 86 RSET_WDT, 87 RSET_UART0, 88 RSET_GPIO, 89 RSET_SPI, 90 RSET_UDC0, 91 RSET_OHCI0, 92 RSET_OHCI_PRIV, 93 RSET_USBH_PRIV, 94 RSET_MPI, 95 RSET_PCMCIA, 96 RSET_DSL, 97 RSET_ENET0, 98 RSET_ENET1, 99 RSET_ENETDMA, 100 RSET_EHCI0, 101 RSET_SDRAM, 102 RSET_MEMC, 103 RSET_DDR, 104 }; 105 106 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 107 #define RSET_DSL_SIZE 4096 108 #define RSET_WDT_SIZE 12 109 #define RSET_ENET_SIZE 2048 110 #define RSET_ENETDMA_SIZE 2048 111 #define RSET_UART_SIZE 24 112 #define RSET_UDC_SIZE 256 113 #define RSET_OHCI_SIZE 256 114 #define RSET_EHCI_SIZE 256 115 #define RSET_PCMCIA_SIZE 12 116 117 /* 118 * 6338 register sets base address 119 */ 120 #define BCM_6338_DSL_LMEM_BASE (0xfff00000) 121 #define BCM_6338_PERF_BASE (0xfffe0000) 122 #define BCM_6338_BB_BASE (0xfffe0100) 123 #define BCM_6338_TIMER_BASE (0xfffe0200) 124 #define BCM_6338_WDT_BASE (0xfffe021c) 125 #define BCM_6338_UART0_BASE (0xfffe0300) 126 #define BCM_6338_GPIO_BASE (0xfffe0400) 127 #define BCM_6338_SPI_BASE (0xfffe0c00) 128 #define BCM_6338_UDC0_BASE (0xdeadbeef) 129 #define BCM_6338_USBDMA_BASE (0xfffe2400) 130 #define BCM_6338_OHCI0_BASE (0xdeadbeef) 131 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 132 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 133 #define BCM_6338_MPI_BASE (0xfffe3160) 134 #define BCM_6338_PCMCIA_BASE (0xdeadbeef) 135 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 136 #define BCM_6338_DSL_BASE (0xfffe1000) 137 #define BCM_6338_SAR_BASE (0xfffe2000) 138 #define BCM_6338_UBUS_BASE (0xdeadbeef) 139 #define BCM_6338_ENET0_BASE (0xfffe2800) 140 #define BCM_6338_ENET1_BASE (0xdeadbeef) 141 #define BCM_6338_ENETDMA_BASE (0xfffe2400) 142 #define BCM_6338_EHCI0_BASE (0xdeadbeef) 143 #define BCM_6338_SDRAM_BASE (0xfffe3100) 144 #define BCM_6338_MEMC_BASE (0xdeadbeef) 145 #define BCM_6338_DDR_BASE (0xdeadbeef) 146 147 /* 148 * 6345 register sets base address 149 */ 150 #define BCM_6345_DSL_LMEM_BASE (0xfff00000) 151 #define BCM_6345_PERF_BASE (0xfffe0000) 152 #define BCM_6345_BB_BASE (0xfffe0100) 153 #define BCM_6345_TIMER_BASE (0xfffe0200) 154 #define BCM_6345_WDT_BASE (0xfffe021c) 155 #define BCM_6345_UART0_BASE (0xfffe0300) 156 #define BCM_6345_GPIO_BASE (0xfffe0400) 157 #define BCM_6345_SPI_BASE (0xdeadbeef) 158 #define BCM_6345_UDC0_BASE (0xdeadbeef) 159 #define BCM_6345_USBDMA_BASE (0xfffe2800) 160 #define BCM_6345_ENET0_BASE (0xfffe1800) 161 #define BCM_6345_ENETDMA_BASE (0xfffe2800) 162 #define BCM_6345_PCMCIA_BASE (0xfffe2028) 163 #define BCM_6345_MPI_BASE (0xdeadbeef) 164 #define BCM_6345_OHCI0_BASE (0xfffe2100) 165 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 166 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 167 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 168 #define BCM_6345_DSL_BASE (0xdeadbeef) 169 #define BCM_6345_SAR_BASE (0xdeadbeef) 170 #define BCM_6345_UBUS_BASE (0xdeadbeef) 171 #define BCM_6345_ENET1_BASE (0xdeadbeef) 172 #define BCM_6345_EHCI0_BASE (0xdeadbeef) 173 #define BCM_6345_SDRAM_BASE (0xfffe2300) 174 #define BCM_6345_MEMC_BASE (0xdeadbeef) 175 #define BCM_6345_DDR_BASE (0xdeadbeef) 176 177 /* 178 * 6348 register sets base address 179 */ 180 #define BCM_6348_DSL_LMEM_BASE (0xfff00000) 181 #define BCM_6348_PERF_BASE (0xfffe0000) 182 #define BCM_6348_TIMER_BASE (0xfffe0200) 183 #define BCM_6348_WDT_BASE (0xfffe021c) 184 #define BCM_6348_UART0_BASE (0xfffe0300) 185 #define BCM_6348_GPIO_BASE (0xfffe0400) 186 #define BCM_6348_SPI_BASE (0xfffe0c00) 187 #define BCM_6348_UDC0_BASE (0xfffe1000) 188 #define BCM_6348_OHCI0_BASE (0xfffe1b00) 189 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 190 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 191 #define BCM_6348_MPI_BASE (0xfffe2000) 192 #define BCM_6348_PCMCIA_BASE (0xfffe2054) 193 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 194 #define BCM_6348_DSL_BASE (0xfffe3000) 195 #define BCM_6348_ENET0_BASE (0xfffe6000) 196 #define BCM_6348_ENET1_BASE (0xfffe6800) 197 #define BCM_6348_ENETDMA_BASE (0xfffe7000) 198 #define BCM_6348_EHCI0_BASE (0xdeadbeef) 199 #define BCM_6348_SDRAM_BASE (0xfffe2300) 200 #define BCM_6348_MEMC_BASE (0xdeadbeef) 201 #define BCM_6348_DDR_BASE (0xdeadbeef) 202 203 /* 204 * 6358 register sets base address 205 */ 206 #define BCM_6358_DSL_LMEM_BASE (0xfff00000) 207 #define BCM_6358_PERF_BASE (0xfffe0000) 208 #define BCM_6358_TIMER_BASE (0xfffe0040) 209 #define BCM_6358_WDT_BASE (0xfffe005c) 210 #define BCM_6358_UART0_BASE (0xfffe0100) 211 #define BCM_6358_GPIO_BASE (0xfffe0080) 212 #define BCM_6358_SPI_BASE (0xdeadbeef) 213 #define BCM_6358_UDC0_BASE (0xfffe0800) 214 #define BCM_6358_OHCI0_BASE (0xfffe1400) 215 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 216 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 217 #define BCM_6358_MPI_BASE (0xfffe1000) 218 #define BCM_6358_PCMCIA_BASE (0xfffe1054) 219 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 220 #define BCM_6358_DSL_BASE (0xfffe3000) 221 #define BCM_6358_ENET0_BASE (0xfffe4000) 222 #define BCM_6358_ENET1_BASE (0xfffe4800) 223 #define BCM_6358_ENETDMA_BASE (0xfffe5000) 224 #define BCM_6358_EHCI0_BASE (0xfffe1300) 225 #define BCM_6358_SDRAM_BASE (0xdeadbeef) 226 #define BCM_6358_MEMC_BASE (0xfffe1200) 227 #define BCM_6358_DDR_BASE (0xfffe12a0) 228 229 230 extern const unsigned long *bcm63xx_regs_base; 231 232 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 233 { 234 #ifdef BCMCPU_RUNTIME_DETECT 235 return bcm63xx_regs_base[set]; 236 #else 237 #ifdef CONFIG_BCM63XX_CPU_6338 238 switch (set) { 239 case RSET_DSL_LMEM: 240 return BCM_6338_DSL_LMEM_BASE; 241 case RSET_PERF: 242 return BCM_6338_PERF_BASE; 243 case RSET_TIMER: 244 return BCM_6338_TIMER_BASE; 245 case RSET_WDT: 246 return BCM_6338_WDT_BASE; 247 case RSET_UART0: 248 return BCM_6338_UART0_BASE; 249 case RSET_GPIO: 250 return BCM_6338_GPIO_BASE; 251 case RSET_SPI: 252 return BCM_6338_SPI_BASE; 253 case RSET_UDC0: 254 return BCM_6338_UDC0_BASE; 255 case RSET_OHCI0: 256 return BCM_6338_OHCI0_BASE; 257 case RSET_OHCI_PRIV: 258 return BCM_6338_OHCI_PRIV_BASE; 259 case RSET_USBH_PRIV: 260 return BCM_6338_USBH_PRIV_BASE; 261 case RSET_MPI: 262 return BCM_6338_MPI_BASE; 263 case RSET_PCMCIA: 264 return BCM_6338_PCMCIA_BASE; 265 case RSET_DSL: 266 return BCM_6338_DSL_BASE; 267 case RSET_ENET0: 268 return BCM_6338_ENET0_BASE; 269 case RSET_ENET1: 270 return BCM_6338_ENET1_BASE; 271 case RSET_ENETDMA: 272 return BCM_6338_ENETDMA_BASE; 273 case RSET_EHCI0: 274 return BCM_6338_EHCI0_BASE; 275 case RSET_SDRAM: 276 return BCM_6338_SDRAM_BASE; 277 case RSET_MEMC: 278 return BCM_6338_MEMC_BASE; 279 case RSET_DDR: 280 return BCM_6338_DDR_BASE; 281 } 282 #endif 283 #ifdef CONFIG_BCM63XX_CPU_6345 284 switch (set) { 285 case RSET_DSL_LMEM: 286 return BCM_6345_DSL_LMEM_BASE; 287 case RSET_PERF: 288 return BCM_6345_PERF_BASE; 289 case RSET_TIMER: 290 return BCM_6345_TIMER_BASE; 291 case RSET_WDT: 292 return BCM_6345_WDT_BASE; 293 case RSET_UART0: 294 return BCM_6345_UART0_BASE; 295 case RSET_GPIO: 296 return BCM_6345_GPIO_BASE; 297 case RSET_SPI: 298 return BCM_6345_SPI_BASE; 299 case RSET_UDC0: 300 return BCM_6345_UDC0_BASE; 301 case RSET_OHCI0: 302 return BCM_6345_OHCI0_BASE; 303 case RSET_OHCI_PRIV: 304 return BCM_6345_OHCI_PRIV_BASE; 305 case RSET_USBH_PRIV: 306 return BCM_6345_USBH_PRIV_BASE; 307 case RSET_MPI: 308 return BCM_6345_MPI_BASE; 309 case RSET_PCMCIA: 310 return BCM_6345_PCMCIA_BASE; 311 case RSET_DSL: 312 return BCM_6345_DSL_BASE; 313 case RSET_ENET0: 314 return BCM_6345_ENET0_BASE; 315 case RSET_ENET1: 316 return BCM_6345_ENET1_BASE; 317 case RSET_ENETDMA: 318 return BCM_6345_ENETDMA_BASE; 319 case RSET_EHCI0: 320 return BCM_6345_EHCI0_BASE; 321 case RSET_SDRAM: 322 return BCM_6345_SDRAM_BASE; 323 case RSET_MEMC: 324 return BCM_6345_MEMC_BASE; 325 case RSET_DDR: 326 return BCM_6345_DDR_BASE; 327 } 328 #endif 329 #ifdef CONFIG_BCM63XX_CPU_6348 330 switch (set) { 331 case RSET_DSL_LMEM: 332 return BCM_6348_DSL_LMEM_BASE; 333 case RSET_PERF: 334 return BCM_6348_PERF_BASE; 335 case RSET_TIMER: 336 return BCM_6348_TIMER_BASE; 337 case RSET_WDT: 338 return BCM_6348_WDT_BASE; 339 case RSET_UART0: 340 return BCM_6348_UART0_BASE; 341 case RSET_GPIO: 342 return BCM_6348_GPIO_BASE; 343 case RSET_SPI: 344 return BCM_6348_SPI_BASE; 345 case RSET_UDC0: 346 return BCM_6348_UDC0_BASE; 347 case RSET_OHCI0: 348 return BCM_6348_OHCI0_BASE; 349 case RSET_OHCI_PRIV: 350 return BCM_6348_OHCI_PRIV_BASE; 351 case RSET_USBH_PRIV: 352 return BCM_6348_USBH_PRIV_BASE; 353 case RSET_MPI: 354 return BCM_6348_MPI_BASE; 355 case RSET_PCMCIA: 356 return BCM_6348_PCMCIA_BASE; 357 case RSET_DSL: 358 return BCM_6348_DSL_BASE; 359 case RSET_ENET0: 360 return BCM_6348_ENET0_BASE; 361 case RSET_ENET1: 362 return BCM_6348_ENET1_BASE; 363 case RSET_ENETDMA: 364 return BCM_6348_ENETDMA_BASE; 365 case RSET_EHCI0: 366 return BCM_6348_EHCI0_BASE; 367 case RSET_SDRAM: 368 return BCM_6348_SDRAM_BASE; 369 case RSET_MEMC: 370 return BCM_6348_MEMC_BASE; 371 case RSET_DDR: 372 return BCM_6348_DDR_BASE; 373 } 374 #endif 375 #ifdef CONFIG_BCM63XX_CPU_6358 376 switch (set) { 377 case RSET_DSL_LMEM: 378 return BCM_6358_DSL_LMEM_BASE; 379 case RSET_PERF: 380 return BCM_6358_PERF_BASE; 381 case RSET_TIMER: 382 return BCM_6358_TIMER_BASE; 383 case RSET_WDT: 384 return BCM_6358_WDT_BASE; 385 case RSET_UART0: 386 return BCM_6358_UART0_BASE; 387 case RSET_GPIO: 388 return BCM_6358_GPIO_BASE; 389 case RSET_SPI: 390 return BCM_6358_SPI_BASE; 391 case RSET_UDC0: 392 return BCM_6358_UDC0_BASE; 393 case RSET_OHCI0: 394 return BCM_6358_OHCI0_BASE; 395 case RSET_OHCI_PRIV: 396 return BCM_6358_OHCI_PRIV_BASE; 397 case RSET_USBH_PRIV: 398 return BCM_6358_USBH_PRIV_BASE; 399 case RSET_MPI: 400 return BCM_6358_MPI_BASE; 401 case RSET_PCMCIA: 402 return BCM_6358_PCMCIA_BASE; 403 case RSET_ENET0: 404 return BCM_6358_ENET0_BASE; 405 case RSET_ENET1: 406 return BCM_6358_ENET1_BASE; 407 case RSET_ENETDMA: 408 return BCM_6358_ENETDMA_BASE; 409 case RSET_DSL: 410 return BCM_6358_DSL_BASE; 411 case RSET_EHCI0: 412 return BCM_6358_EHCI0_BASE; 413 case RSET_SDRAM: 414 return BCM_6358_SDRAM_BASE; 415 case RSET_MEMC: 416 return BCM_6358_MEMC_BASE; 417 case RSET_DDR: 418 return BCM_6358_DDR_BASE; 419 } 420 #endif 421 #endif 422 /* unreached */ 423 return 0; 424 } 425 426 /* 427 * IRQ number changes across CPU too 428 */ 429 enum bcm63xx_irq { 430 IRQ_TIMER = 0, 431 IRQ_UART0, 432 IRQ_DSL, 433 IRQ_ENET0, 434 IRQ_ENET1, 435 IRQ_ENET_PHY, 436 IRQ_OHCI0, 437 IRQ_EHCI0, 438 IRQ_PCMCIA0, 439 IRQ_ENET0_RXDMA, 440 IRQ_ENET0_TXDMA, 441 IRQ_ENET1_RXDMA, 442 IRQ_ENET1_TXDMA, 443 IRQ_PCI, 444 IRQ_PCMCIA, 445 }; 446 447 /* 448 * 6338 irqs 449 */ 450 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 451 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 452 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 453 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 454 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 455 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6) 456 #define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7) 457 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 458 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 459 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 460 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 461 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12) 462 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13) 463 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) 464 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 465 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 466 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 467 468 /* 469 * 6345 irqs 470 */ 471 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 472 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 473 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 474 #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) 475 #define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) 476 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 477 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 478 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 479 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 480 #define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 481 #define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 482 #define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 483 #define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 484 #define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 485 #define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 486 #define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 487 #define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 488 #define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 489 #define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 490 491 /* 492 * 6348 irqs 493 */ 494 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 495 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 496 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 497 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 498 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 499 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 500 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 501 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 502 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 503 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 504 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 505 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 506 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 507 508 /* 509 * 6358 irqs 510 */ 511 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 512 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 513 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 514 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 515 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 516 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 517 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 518 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 519 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 520 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 521 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 522 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 523 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 524 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 525 526 extern const int *bcm63xx_irqs; 527 528 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 529 { 530 return bcm63xx_irqs[irq]; 531 } 532 533 /* 534 * return installed memory size 535 */ 536 unsigned int bcm63xx_get_memory_size(void); 537 538 #endif /* !BCM63XX_CPU_H_ */ 539