1 #ifndef BCM63XX_CPU_H_ 2 #define BCM63XX_CPU_H_ 3 4 #include <linux/types.h> 5 #include <linux/init.h> 6 7 /* 8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 9 * compile time if only one CPU support is enabled (idea stolen from 10 * arm mach-types) 11 */ 12 #define BCM6328_CPU_ID 0x6328 13 #define BCM6338_CPU_ID 0x6338 14 #define BCM6345_CPU_ID 0x6345 15 #define BCM6348_CPU_ID 0x6348 16 #define BCM6358_CPU_ID 0x6358 17 #define BCM6362_CPU_ID 0x6362 18 #define BCM6368_CPU_ID 0x6368 19 20 void __init bcm63xx_cpu_init(void); 21 u16 __bcm63xx_get_cpu_id(void); 22 u8 bcm63xx_get_cpu_rev(void); 23 unsigned int bcm63xx_get_cpu_freq(void); 24 25 #ifdef CONFIG_BCM63XX_CPU_6328 26 # ifdef bcm63xx_get_cpu_id 27 # undef bcm63xx_get_cpu_id 28 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 29 # define BCMCPU_RUNTIME_DETECT 30 # else 31 # define bcm63xx_get_cpu_id() BCM6328_CPU_ID 32 # endif 33 # define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) 34 #else 35 # define BCMCPU_IS_6328() (0) 36 #endif 37 38 #ifdef CONFIG_BCM63XX_CPU_6338 39 # ifdef bcm63xx_get_cpu_id 40 # undef bcm63xx_get_cpu_id 41 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 42 # define BCMCPU_RUNTIME_DETECT 43 # else 44 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID 45 # endif 46 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 47 #else 48 # define BCMCPU_IS_6338() (0) 49 #endif 50 51 #ifdef CONFIG_BCM63XX_CPU_6345 52 # ifdef bcm63xx_get_cpu_id 53 # undef bcm63xx_get_cpu_id 54 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 55 # define BCMCPU_RUNTIME_DETECT 56 # else 57 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID 58 # endif 59 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 60 #else 61 # define BCMCPU_IS_6345() (0) 62 #endif 63 64 #ifdef CONFIG_BCM63XX_CPU_6348 65 # ifdef bcm63xx_get_cpu_id 66 # undef bcm63xx_get_cpu_id 67 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 68 # define BCMCPU_RUNTIME_DETECT 69 # else 70 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID 71 # endif 72 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 73 #else 74 # define BCMCPU_IS_6348() (0) 75 #endif 76 77 #ifdef CONFIG_BCM63XX_CPU_6358 78 # ifdef bcm63xx_get_cpu_id 79 # undef bcm63xx_get_cpu_id 80 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 81 # define BCMCPU_RUNTIME_DETECT 82 # else 83 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID 84 # endif 85 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 86 #else 87 # define BCMCPU_IS_6358() (0) 88 #endif 89 90 #ifdef CONFIG_BCM63XX_CPU_6362 91 # ifdef bcm63xx_get_cpu_id 92 # undef bcm63xx_get_cpu_id 93 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 94 # define BCMCPU_RUNTIME_DETECT 95 # else 96 # define bcm63xx_get_cpu_id() BCM6362_CPU_ID 97 # endif 98 # define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) 99 #else 100 # define BCMCPU_IS_6362() (0) 101 #endif 102 103 104 #ifdef CONFIG_BCM63XX_CPU_6368 105 # ifdef bcm63xx_get_cpu_id 106 # undef bcm63xx_get_cpu_id 107 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 108 # define BCMCPU_RUNTIME_DETECT 109 # else 110 # define bcm63xx_get_cpu_id() BCM6368_CPU_ID 111 # endif 112 # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) 113 #else 114 # define BCMCPU_IS_6368() (0) 115 #endif 116 117 #ifndef bcm63xx_get_cpu_id 118 #error "No CPU support configured" 119 #endif 120 121 /* 122 * While registers sets are (mostly) the same across 63xx CPU, base 123 * address of these sets do change. 124 */ 125 enum bcm63xx_regs_set { 126 RSET_DSL_LMEM = 0, 127 RSET_PERF, 128 RSET_TIMER, 129 RSET_WDT, 130 RSET_UART0, 131 RSET_UART1, 132 RSET_GPIO, 133 RSET_SPI, 134 RSET_UDC0, 135 RSET_OHCI0, 136 RSET_OHCI_PRIV, 137 RSET_USBH_PRIV, 138 RSET_USBD, 139 RSET_USBDMA, 140 RSET_MPI, 141 RSET_PCMCIA, 142 RSET_PCIE, 143 RSET_DSL, 144 RSET_ENET0, 145 RSET_ENET1, 146 RSET_ENETDMA, 147 RSET_ENETDMAC, 148 RSET_ENETDMAS, 149 RSET_ENETSW, 150 RSET_EHCI0, 151 RSET_SDRAM, 152 RSET_MEMC, 153 RSET_DDR, 154 RSET_M2M, 155 RSET_ATM, 156 RSET_XTM, 157 RSET_XTMDMA, 158 RSET_XTMDMAC, 159 RSET_XTMDMAS, 160 RSET_PCM, 161 RSET_PCMDMA, 162 RSET_PCMDMAC, 163 RSET_PCMDMAS, 164 RSET_RNG, 165 RSET_MISC 166 }; 167 168 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 169 #define RSET_DSL_SIZE 4096 170 #define RSET_WDT_SIZE 12 171 #define BCM_6338_RSET_SPI_SIZE 64 172 #define BCM_6348_RSET_SPI_SIZE 64 173 #define BCM_6358_RSET_SPI_SIZE 1804 174 #define BCM_6368_RSET_SPI_SIZE 1804 175 #define RSET_ENET_SIZE 2048 176 #define RSET_ENETDMA_SIZE 2048 177 #define RSET_ENETSW_SIZE 65536 178 #define RSET_UART_SIZE 24 179 #define RSET_UDC_SIZE 256 180 #define RSET_OHCI_SIZE 256 181 #define RSET_EHCI_SIZE 256 182 #define RSET_USBD_SIZE 256 183 #define RSET_USBDMA_SIZE 1280 184 #define RSET_PCMCIA_SIZE 12 185 #define RSET_M2M_SIZE 256 186 #define RSET_ATM_SIZE 4096 187 #define RSET_XTM_SIZE 10240 188 #define RSET_XTMDMA_SIZE 256 189 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 190 #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 191 #define RSET_RNG_SIZE 20 192 193 /* 194 * 6328 register sets base address 195 */ 196 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 197 #define BCM_6328_PERF_BASE (0xb0000000) 198 #define BCM_6328_TIMER_BASE (0xb0000040) 199 #define BCM_6328_WDT_BASE (0xb000005c) 200 #define BCM_6328_UART0_BASE (0xb0000100) 201 #define BCM_6328_UART1_BASE (0xb0000120) 202 #define BCM_6328_GPIO_BASE (0xb0000080) 203 #define BCM_6328_SPI_BASE (0xdeadbeef) 204 #define BCM_6328_UDC0_BASE (0xdeadbeef) 205 #define BCM_6328_USBDMA_BASE (0xb000c000) 206 #define BCM_6328_OHCI0_BASE (0xb0002600) 207 #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) 208 #define BCM_6328_USBH_PRIV_BASE (0xb0002700) 209 #define BCM_6328_USBD_BASE (0xb0002400) 210 #define BCM_6328_MPI_BASE (0xdeadbeef) 211 #define BCM_6328_PCMCIA_BASE (0xdeadbeef) 212 #define BCM_6328_PCIE_BASE (0xb0e40000) 213 #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) 214 #define BCM_6328_DSL_BASE (0xb0001900) 215 #define BCM_6328_UBUS_BASE (0xdeadbeef) 216 #define BCM_6328_ENET0_BASE (0xdeadbeef) 217 #define BCM_6328_ENET1_BASE (0xdeadbeef) 218 #define BCM_6328_ENETDMA_BASE (0xb000d800) 219 #define BCM_6328_ENETDMAC_BASE (0xb000da00) 220 #define BCM_6328_ENETDMAS_BASE (0xb000dc00) 221 #define BCM_6328_ENETSW_BASE (0xb0e00000) 222 #define BCM_6328_EHCI0_BASE (0xb0002500) 223 #define BCM_6328_SDRAM_BASE (0xdeadbeef) 224 #define BCM_6328_MEMC_BASE (0xdeadbeef) 225 #define BCM_6328_DDR_BASE (0xb0003000) 226 #define BCM_6328_M2M_BASE (0xdeadbeef) 227 #define BCM_6328_ATM_BASE (0xdeadbeef) 228 #define BCM_6328_XTM_BASE (0xdeadbeef) 229 #define BCM_6328_XTMDMA_BASE (0xb000b800) 230 #define BCM_6328_XTMDMAC_BASE (0xdeadbeef) 231 #define BCM_6328_XTMDMAS_BASE (0xdeadbeef) 232 #define BCM_6328_PCM_BASE (0xb000a800) 233 #define BCM_6328_PCMDMA_BASE (0xdeadbeef) 234 #define BCM_6328_PCMDMAC_BASE (0xdeadbeef) 235 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 236 #define BCM_6328_RNG_BASE (0xdeadbeef) 237 #define BCM_6328_MISC_BASE (0xb0001800) 238 /* 239 * 6338 register sets base address 240 */ 241 #define BCM_6338_DSL_LMEM_BASE (0xfff00000) 242 #define BCM_6338_PERF_BASE (0xfffe0000) 243 #define BCM_6338_BB_BASE (0xfffe0100) 244 #define BCM_6338_TIMER_BASE (0xfffe0200) 245 #define BCM_6338_WDT_BASE (0xfffe021c) 246 #define BCM_6338_UART0_BASE (0xfffe0300) 247 #define BCM_6338_UART1_BASE (0xdeadbeef) 248 #define BCM_6338_GPIO_BASE (0xfffe0400) 249 #define BCM_6338_SPI_BASE (0xfffe0c00) 250 #define BCM_6338_UDC0_BASE (0xdeadbeef) 251 #define BCM_6338_USBDMA_BASE (0xfffe2400) 252 #define BCM_6338_OHCI0_BASE (0xdeadbeef) 253 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 254 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 255 #define BCM_6338_USBD_BASE (0xdeadbeef) 256 #define BCM_6338_MPI_BASE (0xfffe3160) 257 #define BCM_6338_PCMCIA_BASE (0xdeadbeef) 258 #define BCM_6338_PCIE_BASE (0xdeadbeef) 259 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 260 #define BCM_6338_DSL_BASE (0xfffe1000) 261 #define BCM_6338_UBUS_BASE (0xdeadbeef) 262 #define BCM_6338_ENET0_BASE (0xfffe2800) 263 #define BCM_6338_ENET1_BASE (0xdeadbeef) 264 #define BCM_6338_ENETDMA_BASE (0xfffe2400) 265 #define BCM_6338_ENETDMAC_BASE (0xfffe2500) 266 #define BCM_6338_ENETDMAS_BASE (0xfffe2600) 267 #define BCM_6338_ENETSW_BASE (0xdeadbeef) 268 #define BCM_6338_EHCI0_BASE (0xdeadbeef) 269 #define BCM_6338_SDRAM_BASE (0xfffe3100) 270 #define BCM_6338_MEMC_BASE (0xdeadbeef) 271 #define BCM_6338_DDR_BASE (0xdeadbeef) 272 #define BCM_6338_M2M_BASE (0xdeadbeef) 273 #define BCM_6338_ATM_BASE (0xfffe2000) 274 #define BCM_6338_XTM_BASE (0xdeadbeef) 275 #define BCM_6338_XTMDMA_BASE (0xdeadbeef) 276 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef) 277 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef) 278 #define BCM_6338_PCM_BASE (0xdeadbeef) 279 #define BCM_6338_PCMDMA_BASE (0xdeadbeef) 280 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 281 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 282 #define BCM_6338_RNG_BASE (0xdeadbeef) 283 #define BCM_6338_MISC_BASE (0xdeadbeef) 284 285 /* 286 * 6345 register sets base address 287 */ 288 #define BCM_6345_DSL_LMEM_BASE (0xfff00000) 289 #define BCM_6345_PERF_BASE (0xfffe0000) 290 #define BCM_6345_BB_BASE (0xfffe0100) 291 #define BCM_6345_TIMER_BASE (0xfffe0200) 292 #define BCM_6345_WDT_BASE (0xfffe021c) 293 #define BCM_6345_UART0_BASE (0xfffe0300) 294 #define BCM_6345_UART1_BASE (0xdeadbeef) 295 #define BCM_6345_GPIO_BASE (0xfffe0400) 296 #define BCM_6345_SPI_BASE (0xdeadbeef) 297 #define BCM_6345_UDC0_BASE (0xdeadbeef) 298 #define BCM_6345_USBDMA_BASE (0xfffe2800) 299 #define BCM_6345_ENET0_BASE (0xfffe1800) 300 #define BCM_6345_ENETDMA_BASE (0xfffe2800) 301 #define BCM_6345_ENETDMAC_BASE (0xfffe2900) 302 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 303 #define BCM_6345_ENETSW_BASE (0xdeadbeef) 304 #define BCM_6345_PCMCIA_BASE (0xfffe2028) 305 #define BCM_6345_MPI_BASE (0xfffe2000) 306 #define BCM_6345_PCIE_BASE (0xdeadbeef) 307 #define BCM_6345_OHCI0_BASE (0xfffe2100) 308 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 309 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 310 #define BCM_6345_USBD_BASE (0xdeadbeef) 311 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 312 #define BCM_6345_DSL_BASE (0xdeadbeef) 313 #define BCM_6345_UBUS_BASE (0xdeadbeef) 314 #define BCM_6345_ENET1_BASE (0xdeadbeef) 315 #define BCM_6345_EHCI0_BASE (0xdeadbeef) 316 #define BCM_6345_SDRAM_BASE (0xfffe2300) 317 #define BCM_6345_MEMC_BASE (0xdeadbeef) 318 #define BCM_6345_DDR_BASE (0xdeadbeef) 319 #define BCM_6345_M2M_BASE (0xdeadbeef) 320 #define BCM_6345_ATM_BASE (0xfffe4000) 321 #define BCM_6345_XTM_BASE (0xdeadbeef) 322 #define BCM_6345_XTMDMA_BASE (0xdeadbeef) 323 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef) 324 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef) 325 #define BCM_6345_PCM_BASE (0xdeadbeef) 326 #define BCM_6345_PCMDMA_BASE (0xdeadbeef) 327 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 328 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 329 #define BCM_6345_RNG_BASE (0xdeadbeef) 330 #define BCM_6345_MISC_BASE (0xdeadbeef) 331 332 /* 333 * 6348 register sets base address 334 */ 335 #define BCM_6348_DSL_LMEM_BASE (0xfff00000) 336 #define BCM_6348_PERF_BASE (0xfffe0000) 337 #define BCM_6348_TIMER_BASE (0xfffe0200) 338 #define BCM_6348_WDT_BASE (0xfffe021c) 339 #define BCM_6348_UART0_BASE (0xfffe0300) 340 #define BCM_6348_UART1_BASE (0xdeadbeef) 341 #define BCM_6348_GPIO_BASE (0xfffe0400) 342 #define BCM_6348_SPI_BASE (0xfffe0c00) 343 #define BCM_6348_UDC0_BASE (0xfffe1000) 344 #define BCM_6348_USBDMA_BASE (0xdeadbeef) 345 #define BCM_6348_OHCI0_BASE (0xfffe1b00) 346 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 347 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 348 #define BCM_6348_USBD_BASE (0xdeadbeef) 349 #define BCM_6348_MPI_BASE (0xfffe2000) 350 #define BCM_6348_PCMCIA_BASE (0xfffe2054) 351 #define BCM_6348_PCIE_BASE (0xdeadbeef) 352 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 353 #define BCM_6348_M2M_BASE (0xfffe2800) 354 #define BCM_6348_DSL_BASE (0xfffe3000) 355 #define BCM_6348_ENET0_BASE (0xfffe6000) 356 #define BCM_6348_ENET1_BASE (0xfffe6800) 357 #define BCM_6348_ENETDMA_BASE (0xfffe7000) 358 #define BCM_6348_ENETDMAC_BASE (0xfffe7100) 359 #define BCM_6348_ENETDMAS_BASE (0xfffe7200) 360 #define BCM_6348_ENETSW_BASE (0xdeadbeef) 361 #define BCM_6348_EHCI0_BASE (0xdeadbeef) 362 #define BCM_6348_SDRAM_BASE (0xfffe2300) 363 #define BCM_6348_MEMC_BASE (0xdeadbeef) 364 #define BCM_6348_DDR_BASE (0xdeadbeef) 365 #define BCM_6348_ATM_BASE (0xfffe4000) 366 #define BCM_6348_XTM_BASE (0xdeadbeef) 367 #define BCM_6348_XTMDMA_BASE (0xdeadbeef) 368 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef) 369 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef) 370 #define BCM_6348_PCM_BASE (0xdeadbeef) 371 #define BCM_6348_PCMDMA_BASE (0xdeadbeef) 372 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 373 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 374 #define BCM_6348_RNG_BASE (0xdeadbeef) 375 #define BCM_6348_MISC_BASE (0xdeadbeef) 376 377 /* 378 * 6358 register sets base address 379 */ 380 #define BCM_6358_DSL_LMEM_BASE (0xfff00000) 381 #define BCM_6358_PERF_BASE (0xfffe0000) 382 #define BCM_6358_TIMER_BASE (0xfffe0040) 383 #define BCM_6358_WDT_BASE (0xfffe005c) 384 #define BCM_6358_UART0_BASE (0xfffe0100) 385 #define BCM_6358_UART1_BASE (0xfffe0120) 386 #define BCM_6358_GPIO_BASE (0xfffe0080) 387 #define BCM_6358_SPI_BASE (0xfffe0800) 388 #define BCM_6358_UDC0_BASE (0xfffe0800) 389 #define BCM_6358_USBDMA_BASE (0xdeadbeef) 390 #define BCM_6358_OHCI0_BASE (0xfffe1400) 391 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 392 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 393 #define BCM_6358_USBD_BASE (0xdeadbeef) 394 #define BCM_6358_MPI_BASE (0xfffe1000) 395 #define BCM_6358_PCMCIA_BASE (0xfffe1054) 396 #define BCM_6358_PCIE_BASE (0xdeadbeef) 397 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 398 #define BCM_6358_M2M_BASE (0xdeadbeef) 399 #define BCM_6358_DSL_BASE (0xfffe3000) 400 #define BCM_6358_ENET0_BASE (0xfffe4000) 401 #define BCM_6358_ENET1_BASE (0xfffe4800) 402 #define BCM_6358_ENETDMA_BASE (0xfffe5000) 403 #define BCM_6358_ENETDMAC_BASE (0xfffe5100) 404 #define BCM_6358_ENETDMAS_BASE (0xfffe5200) 405 #define BCM_6358_ENETSW_BASE (0xdeadbeef) 406 #define BCM_6358_EHCI0_BASE (0xfffe1300) 407 #define BCM_6358_SDRAM_BASE (0xdeadbeef) 408 #define BCM_6358_MEMC_BASE (0xfffe1200) 409 #define BCM_6358_DDR_BASE (0xfffe12a0) 410 #define BCM_6358_ATM_BASE (0xfffe2000) 411 #define BCM_6358_XTM_BASE (0xdeadbeef) 412 #define BCM_6358_XTMDMA_BASE (0xdeadbeef) 413 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef) 414 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef) 415 #define BCM_6358_PCM_BASE (0xfffe1600) 416 #define BCM_6358_PCMDMA_BASE (0xfffe1800) 417 #define BCM_6358_PCMDMAC_BASE (0xfffe1900) 418 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 419 #define BCM_6358_RNG_BASE (0xdeadbeef) 420 #define BCM_6358_MISC_BASE (0xdeadbeef) 421 422 423 /* 424 * 6362 register sets base address 425 */ 426 #define BCM_6362_DSL_LMEM_BASE (0xdeadbeef) 427 #define BCM_6362_PERF_BASE (0xb0000000) 428 #define BCM_6362_TIMER_BASE (0xb0000040) 429 #define BCM_6362_WDT_BASE (0xb000005c) 430 #define BCM_6362_UART0_BASE (0xb0000100) 431 #define BCM_6362_UART1_BASE (0xb0000120) 432 #define BCM_6362_GPIO_BASE (0xb0000080) 433 #define BCM_6362_SPI_BASE (0xb0000800) 434 #define BCM_6362_HSSPI_BASE (0xb0001000) 435 #define BCM_6362_UDC0_BASE (0xdeadbeef) 436 #define BCM_6362_USBDMA_BASE (0xb000c000) 437 #define BCM_6362_OHCI0_BASE (0xb0002600) 438 #define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) 439 #define BCM_6362_USBH_PRIV_BASE (0xb0002700) 440 #define BCM_6362_USBD_BASE (0xb0002400) 441 #define BCM_6362_MPI_BASE (0xdeadbeef) 442 #define BCM_6362_PCMCIA_BASE (0xdeadbeef) 443 #define BCM_6362_PCIE_BASE (0xb0e40000) 444 #define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef) 445 #define BCM_6362_DSL_BASE (0xdeadbeef) 446 #define BCM_6362_UBUS_BASE (0xdeadbeef) 447 #define BCM_6362_ENET0_BASE (0xdeadbeef) 448 #define BCM_6362_ENET1_BASE (0xdeadbeef) 449 #define BCM_6362_ENETDMA_BASE (0xb000d800) 450 #define BCM_6362_ENETDMAC_BASE (0xb000da00) 451 #define BCM_6362_ENETDMAS_BASE (0xb000dc00) 452 #define BCM_6362_ENETSW_BASE (0xb0e00000) 453 #define BCM_6362_EHCI0_BASE (0xb0002500) 454 #define BCM_6362_SDRAM_BASE (0xdeadbeef) 455 #define BCM_6362_MEMC_BASE (0xdeadbeef) 456 #define BCM_6362_DDR_BASE (0xb0003000) 457 #define BCM_6362_M2M_BASE (0xdeadbeef) 458 #define BCM_6362_ATM_BASE (0xdeadbeef) 459 #define BCM_6362_XTM_BASE (0xb0007800) 460 #define BCM_6362_XTMDMA_BASE (0xb000b800) 461 #define BCM_6362_XTMDMAC_BASE (0xdeadbeef) 462 #define BCM_6362_XTMDMAS_BASE (0xdeadbeef) 463 #define BCM_6362_PCM_BASE (0xb000a800) 464 #define BCM_6362_PCMDMA_BASE (0xdeadbeef) 465 #define BCM_6362_PCMDMAC_BASE (0xdeadbeef) 466 #define BCM_6362_PCMDMAS_BASE (0xdeadbeef) 467 #define BCM_6362_RNG_BASE (0xdeadbeef) 468 #define BCM_6362_MISC_BASE (0xb0001800) 469 470 #define BCM_6362_NAND_REG_BASE (0xb0000200) 471 #define BCM_6362_NAND_CACHE_BASE (0xb0000600) 472 #define BCM_6362_LED_BASE (0xb0001900) 473 #define BCM_6362_IPSEC_BASE (0xb0002800) 474 #define BCM_6362_IPSEC_DMA_BASE (0xb000d000) 475 #define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000) 476 #define BCM_6362_WLAN_D11_BASE (0xb0005000) 477 #define BCM_6362_WLAN_SHIM_BASE (0xb0007000) 478 479 /* 480 * 6368 register sets base address 481 */ 482 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) 483 #define BCM_6368_PERF_BASE (0xb0000000) 484 #define BCM_6368_TIMER_BASE (0xb0000040) 485 #define BCM_6368_WDT_BASE (0xb000005c) 486 #define BCM_6368_UART0_BASE (0xb0000100) 487 #define BCM_6368_UART1_BASE (0xb0000120) 488 #define BCM_6368_GPIO_BASE (0xb0000080) 489 #define BCM_6368_SPI_BASE (0xb0000800) 490 #define BCM_6368_UDC0_BASE (0xdeadbeef) 491 #define BCM_6368_USBDMA_BASE (0xb0004800) 492 #define BCM_6368_OHCI0_BASE (0xb0001600) 493 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 494 #define BCM_6368_USBH_PRIV_BASE (0xb0001700) 495 #define BCM_6368_USBD_BASE (0xb0001400) 496 #define BCM_6368_MPI_BASE (0xb0001000) 497 #define BCM_6368_PCMCIA_BASE (0xb0001054) 498 #define BCM_6368_PCIE_BASE (0xdeadbeef) 499 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 500 #define BCM_6368_M2M_BASE (0xdeadbeef) 501 #define BCM_6368_DSL_BASE (0xdeadbeef) 502 #define BCM_6368_ENET0_BASE (0xdeadbeef) 503 #define BCM_6368_ENET1_BASE (0xdeadbeef) 504 #define BCM_6368_ENETDMA_BASE (0xb0006800) 505 #define BCM_6368_ENETDMAC_BASE (0xb0006a00) 506 #define BCM_6368_ENETDMAS_BASE (0xb0006c00) 507 #define BCM_6368_ENETSW_BASE (0xb0f00000) 508 #define BCM_6368_EHCI0_BASE (0xb0001500) 509 #define BCM_6368_SDRAM_BASE (0xdeadbeef) 510 #define BCM_6368_MEMC_BASE (0xb0001200) 511 #define BCM_6368_DDR_BASE (0xb0001280) 512 #define BCM_6368_ATM_BASE (0xdeadbeef) 513 #define BCM_6368_XTM_BASE (0xb0001800) 514 #define BCM_6368_XTMDMA_BASE (0xb0005000) 515 #define BCM_6368_XTMDMAC_BASE (0xb0005200) 516 #define BCM_6368_XTMDMAS_BASE (0xb0005400) 517 #define BCM_6368_PCM_BASE (0xb0004000) 518 #define BCM_6368_PCMDMA_BASE (0xb0005800) 519 #define BCM_6368_PCMDMAC_BASE (0xb0005a00) 520 #define BCM_6368_PCMDMAS_BASE (0xb0005c00) 521 #define BCM_6368_RNG_BASE (0xb0004180) 522 #define BCM_6368_MISC_BASE (0xdeadbeef) 523 524 525 extern const unsigned long *bcm63xx_regs_base; 526 527 #define __GEN_RSET_BASE(__cpu, __rset) \ 528 case RSET_## __rset : \ 529 return BCM_## __cpu ##_## __rset ##_BASE; 530 531 #define __GEN_RSET(__cpu) \ 532 switch (set) { \ 533 __GEN_RSET_BASE(__cpu, DSL_LMEM) \ 534 __GEN_RSET_BASE(__cpu, PERF) \ 535 __GEN_RSET_BASE(__cpu, TIMER) \ 536 __GEN_RSET_BASE(__cpu, WDT) \ 537 __GEN_RSET_BASE(__cpu, UART0) \ 538 __GEN_RSET_BASE(__cpu, UART1) \ 539 __GEN_RSET_BASE(__cpu, GPIO) \ 540 __GEN_RSET_BASE(__cpu, SPI) \ 541 __GEN_RSET_BASE(__cpu, UDC0) \ 542 __GEN_RSET_BASE(__cpu, OHCI0) \ 543 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 544 __GEN_RSET_BASE(__cpu, USBH_PRIV) \ 545 __GEN_RSET_BASE(__cpu, USBD) \ 546 __GEN_RSET_BASE(__cpu, USBDMA) \ 547 __GEN_RSET_BASE(__cpu, MPI) \ 548 __GEN_RSET_BASE(__cpu, PCMCIA) \ 549 __GEN_RSET_BASE(__cpu, PCIE) \ 550 __GEN_RSET_BASE(__cpu, DSL) \ 551 __GEN_RSET_BASE(__cpu, ENET0) \ 552 __GEN_RSET_BASE(__cpu, ENET1) \ 553 __GEN_RSET_BASE(__cpu, ENETDMA) \ 554 __GEN_RSET_BASE(__cpu, ENETDMAC) \ 555 __GEN_RSET_BASE(__cpu, ENETDMAS) \ 556 __GEN_RSET_BASE(__cpu, ENETSW) \ 557 __GEN_RSET_BASE(__cpu, EHCI0) \ 558 __GEN_RSET_BASE(__cpu, SDRAM) \ 559 __GEN_RSET_BASE(__cpu, MEMC) \ 560 __GEN_RSET_BASE(__cpu, DDR) \ 561 __GEN_RSET_BASE(__cpu, M2M) \ 562 __GEN_RSET_BASE(__cpu, ATM) \ 563 __GEN_RSET_BASE(__cpu, XTM) \ 564 __GEN_RSET_BASE(__cpu, XTMDMA) \ 565 __GEN_RSET_BASE(__cpu, XTMDMAC) \ 566 __GEN_RSET_BASE(__cpu, XTMDMAS) \ 567 __GEN_RSET_BASE(__cpu, PCM) \ 568 __GEN_RSET_BASE(__cpu, PCMDMA) \ 569 __GEN_RSET_BASE(__cpu, PCMDMAC) \ 570 __GEN_RSET_BASE(__cpu, PCMDMAS) \ 571 __GEN_RSET_BASE(__cpu, RNG) \ 572 __GEN_RSET_BASE(__cpu, MISC) \ 573 } 574 575 #define __GEN_CPU_REGS_TABLE(__cpu) \ 576 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ 577 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ 578 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ 579 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ 580 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ 581 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 582 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 583 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 584 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 585 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 586 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 587 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 588 [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ 589 [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ 590 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 591 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 592 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ 593 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 594 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 595 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 596 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ 597 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ 598 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ 599 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ 600 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ 601 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ 602 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ 603 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ 604 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ 605 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ 606 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ 607 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ 608 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ 609 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ 610 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ 611 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 612 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 613 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 614 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ 615 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ 616 617 618 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 619 { 620 #ifdef BCMCPU_RUNTIME_DETECT 621 return bcm63xx_regs_base[set]; 622 #else 623 #ifdef CONFIG_BCM63XX_CPU_6328 624 __GEN_RSET(6328) 625 #endif 626 #ifdef CONFIG_BCM63XX_CPU_6338 627 __GEN_RSET(6338) 628 #endif 629 #ifdef CONFIG_BCM63XX_CPU_6345 630 __GEN_RSET(6345) 631 #endif 632 #ifdef CONFIG_BCM63XX_CPU_6348 633 __GEN_RSET(6348) 634 #endif 635 #ifdef CONFIG_BCM63XX_CPU_6358 636 __GEN_RSET(6358) 637 #endif 638 #ifdef CONFIG_BCM63XX_CPU_6362 639 __GEN_RSET(6362) 640 #endif 641 #ifdef CONFIG_BCM63XX_CPU_6368 642 __GEN_RSET(6368) 643 #endif 644 #endif 645 /* unreached */ 646 return 0; 647 } 648 649 /* 650 * IRQ number changes across CPU too 651 */ 652 enum bcm63xx_irq { 653 IRQ_TIMER = 0, 654 IRQ_SPI, 655 IRQ_UART0, 656 IRQ_UART1, 657 IRQ_DSL, 658 IRQ_ENET0, 659 IRQ_ENET1, 660 IRQ_ENET_PHY, 661 IRQ_OHCI0, 662 IRQ_EHCI0, 663 IRQ_USBD, 664 IRQ_USBD_RXDMA0, 665 IRQ_USBD_TXDMA0, 666 IRQ_USBD_RXDMA1, 667 IRQ_USBD_TXDMA1, 668 IRQ_USBD_RXDMA2, 669 IRQ_USBD_TXDMA2, 670 IRQ_ENET0_RXDMA, 671 IRQ_ENET0_TXDMA, 672 IRQ_ENET1_RXDMA, 673 IRQ_ENET1_TXDMA, 674 IRQ_PCI, 675 IRQ_PCMCIA, 676 IRQ_ATM, 677 IRQ_ENETSW_RXDMA0, 678 IRQ_ENETSW_RXDMA1, 679 IRQ_ENETSW_RXDMA2, 680 IRQ_ENETSW_RXDMA3, 681 IRQ_ENETSW_TXDMA0, 682 IRQ_ENETSW_TXDMA1, 683 IRQ_ENETSW_TXDMA2, 684 IRQ_ENETSW_TXDMA3, 685 IRQ_XTM, 686 IRQ_XTM_DMA0, 687 }; 688 689 /* 690 * 6328 irqs 691 */ 692 #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 693 694 #define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) 695 #define BCM_6328_SPI_IRQ 0 696 #define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28) 697 #define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) 698 #define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 699 #define BCM_6328_UDC0_IRQ 0 700 #define BCM_6328_ENET0_IRQ 0 701 #define BCM_6328_ENET1_IRQ 0 702 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 703 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 704 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 705 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) 706 #define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) 707 #define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) 708 #define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) 709 #define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) 710 #define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) 711 #define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) 712 #define BCM_6328_PCMCIA_IRQ 0 713 #define BCM_6328_ENET0_RXDMA_IRQ 0 714 #define BCM_6328_ENET0_TXDMA_IRQ 0 715 #define BCM_6328_ENET1_RXDMA_IRQ 0 716 #define BCM_6328_ENET1_TXDMA_IRQ 0 717 #define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23) 718 #define BCM_6328_ATM_IRQ 0 719 #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0) 720 #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) 721 #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) 722 #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) 723 #define BCM_6328_ENETSW_TXDMA0_IRQ 0 724 #define BCM_6328_ENETSW_TXDMA1_IRQ 0 725 #define BCM_6328_ENETSW_TXDMA2_IRQ 0 726 #define BCM_6328_ENETSW_TXDMA3_IRQ 0 727 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) 728 #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) 729 730 #define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) 731 #define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) 732 #define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) 733 #define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) 734 #define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) 735 #define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) 736 737 /* 738 * 6338 irqs 739 */ 740 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 741 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 742 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 743 #define BCM_6338_UART1_IRQ 0 744 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 745 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 746 #define BCM_6338_ENET1_IRQ 0 747 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 748 #define BCM_6338_OHCI0_IRQ 0 749 #define BCM_6338_EHCI0_IRQ 0 750 #define BCM_6338_USBD_IRQ 0 751 #define BCM_6338_USBD_RXDMA0_IRQ 0 752 #define BCM_6338_USBD_TXDMA0_IRQ 0 753 #define BCM_6338_USBD_RXDMA1_IRQ 0 754 #define BCM_6338_USBD_TXDMA1_IRQ 0 755 #define BCM_6338_USBD_RXDMA2_IRQ 0 756 #define BCM_6338_USBD_TXDMA2_IRQ 0 757 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 758 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 759 #define BCM_6338_ENET1_RXDMA_IRQ 0 760 #define BCM_6338_ENET1_TXDMA_IRQ 0 761 #define BCM_6338_PCI_IRQ 0 762 #define BCM_6338_PCMCIA_IRQ 0 763 #define BCM_6338_ATM_IRQ 0 764 #define BCM_6338_ENETSW_RXDMA0_IRQ 0 765 #define BCM_6338_ENETSW_RXDMA1_IRQ 0 766 #define BCM_6338_ENETSW_RXDMA2_IRQ 0 767 #define BCM_6338_ENETSW_RXDMA3_IRQ 0 768 #define BCM_6338_ENETSW_TXDMA0_IRQ 0 769 #define BCM_6338_ENETSW_TXDMA1_IRQ 0 770 #define BCM_6338_ENETSW_TXDMA2_IRQ 0 771 #define BCM_6338_ENETSW_TXDMA3_IRQ 0 772 #define BCM_6338_XTM_IRQ 0 773 #define BCM_6338_XTM_DMA0_IRQ 0 774 775 /* 776 * 6345 irqs 777 */ 778 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 779 #define BCM_6345_SPI_IRQ 0 780 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 781 #define BCM_6345_UART1_IRQ 0 782 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 783 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 784 #define BCM_6345_ENET1_IRQ 0 785 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 786 #define BCM_6345_OHCI0_IRQ 0 787 #define BCM_6345_EHCI0_IRQ 0 788 #define BCM_6345_USBD_IRQ 0 789 #define BCM_6345_USBD_RXDMA0_IRQ 0 790 #define BCM_6345_USBD_TXDMA0_IRQ 0 791 #define BCM_6345_USBD_RXDMA1_IRQ 0 792 #define BCM_6345_USBD_TXDMA1_IRQ 0 793 #define BCM_6345_USBD_RXDMA2_IRQ 0 794 #define BCM_6345_USBD_TXDMA2_IRQ 0 795 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 796 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 797 #define BCM_6345_ENET1_RXDMA_IRQ 0 798 #define BCM_6345_ENET1_TXDMA_IRQ 0 799 #define BCM_6345_PCI_IRQ 0 800 #define BCM_6345_PCMCIA_IRQ 0 801 #define BCM_6345_ATM_IRQ 0 802 #define BCM_6345_ENETSW_RXDMA0_IRQ 0 803 #define BCM_6345_ENETSW_RXDMA1_IRQ 0 804 #define BCM_6345_ENETSW_RXDMA2_IRQ 0 805 #define BCM_6345_ENETSW_RXDMA3_IRQ 0 806 #define BCM_6345_ENETSW_TXDMA0_IRQ 0 807 #define BCM_6345_ENETSW_TXDMA1_IRQ 0 808 #define BCM_6345_ENETSW_TXDMA2_IRQ 0 809 #define BCM_6345_ENETSW_TXDMA3_IRQ 0 810 #define BCM_6345_XTM_IRQ 0 811 #define BCM_6345_XTM_DMA0_IRQ 0 812 813 /* 814 * 6348 irqs 815 */ 816 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 817 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 818 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 819 #define BCM_6348_UART1_IRQ 0 820 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 821 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 822 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 823 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 824 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 825 #define BCM_6348_EHCI0_IRQ 0 826 #define BCM_6348_USBD_IRQ 0 827 #define BCM_6348_USBD_RXDMA0_IRQ 0 828 #define BCM_6348_USBD_TXDMA0_IRQ 0 829 #define BCM_6348_USBD_RXDMA1_IRQ 0 830 #define BCM_6348_USBD_TXDMA1_IRQ 0 831 #define BCM_6348_USBD_RXDMA2_IRQ 0 832 #define BCM_6348_USBD_TXDMA2_IRQ 0 833 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 834 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 835 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 836 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 837 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 838 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 839 #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) 840 #define BCM_6348_ENETSW_RXDMA0_IRQ 0 841 #define BCM_6348_ENETSW_RXDMA1_IRQ 0 842 #define BCM_6348_ENETSW_RXDMA2_IRQ 0 843 #define BCM_6348_ENETSW_RXDMA3_IRQ 0 844 #define BCM_6348_ENETSW_TXDMA0_IRQ 0 845 #define BCM_6348_ENETSW_TXDMA1_IRQ 0 846 #define BCM_6348_ENETSW_TXDMA2_IRQ 0 847 #define BCM_6348_ENETSW_TXDMA3_IRQ 0 848 #define BCM_6348_XTM_IRQ 0 849 #define BCM_6348_XTM_DMA0_IRQ 0 850 851 /* 852 * 6358 irqs 853 */ 854 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 855 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 856 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 857 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 858 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 859 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 860 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 861 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 862 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 863 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 864 #define BCM_6358_USBD_IRQ 0 865 #define BCM_6358_USBD_RXDMA0_IRQ 0 866 #define BCM_6358_USBD_TXDMA0_IRQ 0 867 #define BCM_6358_USBD_RXDMA1_IRQ 0 868 #define BCM_6358_USBD_TXDMA1_IRQ 0 869 #define BCM_6358_USBD_RXDMA2_IRQ 0 870 #define BCM_6358_USBD_TXDMA2_IRQ 0 871 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 872 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 873 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 874 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 875 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 876 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 877 #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) 878 #define BCM_6358_ENETSW_RXDMA0_IRQ 0 879 #define BCM_6358_ENETSW_RXDMA1_IRQ 0 880 #define BCM_6358_ENETSW_RXDMA2_IRQ 0 881 #define BCM_6358_ENETSW_RXDMA3_IRQ 0 882 #define BCM_6358_ENETSW_TXDMA0_IRQ 0 883 #define BCM_6358_ENETSW_TXDMA1_IRQ 0 884 #define BCM_6358_ENETSW_TXDMA2_IRQ 0 885 #define BCM_6358_ENETSW_TXDMA3_IRQ 0 886 #define BCM_6358_XTM_IRQ 0 887 #define BCM_6358_XTM_DMA0_IRQ 0 888 889 #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) 890 #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) 891 #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 892 #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 893 #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 894 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 895 896 /* 897 * 6362 irqs 898 */ 899 #define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 900 901 #define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 902 #define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2) 903 #define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) 904 #define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) 905 #define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28) 906 #define BCM_6362_UDC0_IRQ 0 907 #define BCM_6362_ENET0_IRQ 0 908 #define BCM_6362_ENET1_IRQ 0 909 #define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14) 910 #define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5) 911 #define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) 912 #define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 913 #define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11) 914 #define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20) 915 #define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21) 916 #define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22) 917 #define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23) 918 #define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24) 919 #define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25) 920 #define BCM_6362_PCMCIA_IRQ 0 921 #define BCM_6362_ENET0_RXDMA_IRQ 0 922 #define BCM_6362_ENET0_TXDMA_IRQ 0 923 #define BCM_6362_ENET1_RXDMA_IRQ 0 924 #define BCM_6362_ENET1_TXDMA_IRQ 0 925 #define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30) 926 #define BCM_6362_ATM_IRQ 0 927 #define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0) 928 #define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1) 929 #define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2) 930 #define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3) 931 #define BCM_6362_ENETSW_TXDMA0_IRQ 0 932 #define BCM_6362_ENETSW_TXDMA1_IRQ 0 933 #define BCM_6362_ENETSW_TXDMA2_IRQ 0 934 #define BCM_6362_ENETSW_TXDMA3_IRQ 0 935 #define BCM_6362_XTM_IRQ 0 936 #define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12) 937 938 #define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1) 939 #define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6) 940 #define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) 941 #define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) 942 #define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12) 943 #define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13) 944 #define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15) 945 #define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) 946 #define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) 947 #define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) 948 #define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) 949 #define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) 950 #define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27) 951 #define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29) 952 #define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4) 953 #define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5) 954 #define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6) 955 #define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7) 956 #define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8) 957 #define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9) 958 #define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10) 959 #define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11) 960 961 /* 962 * 6368 irqs 963 */ 964 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 965 966 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 967 #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 968 #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 969 #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 970 #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 971 #define BCM_6368_ENET0_IRQ 0 972 #define BCM_6368_ENET1_IRQ 0 973 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 974 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 975 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 976 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) 977 #define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) 978 #define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) 979 #define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) 980 #define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) 981 #define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) 982 #define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) 983 #define BCM_6368_PCMCIA_IRQ 0 984 #define BCM_6368_ENET0_RXDMA_IRQ 0 985 #define BCM_6368_ENET0_TXDMA_IRQ 0 986 #define BCM_6368_ENET1_RXDMA_IRQ 0 987 #define BCM_6368_ENET1_TXDMA_IRQ 0 988 #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) 989 #define BCM_6368_ATM_IRQ 0 990 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) 991 #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) 992 #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) 993 #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) 994 #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) 995 #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) 996 #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) 997 #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) 998 #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) 999 #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) 1000 1001 #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) 1002 #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) 1003 #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) 1004 #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) 1005 #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) 1006 #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) 1007 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) 1008 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) 1009 1010 extern const int *bcm63xx_irqs; 1011 1012 #define __GEN_CPU_IRQ_TABLE(__cpu) \ 1013 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 1014 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ 1015 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 1016 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 1017 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 1018 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1019 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1020 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1021 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1022 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1023 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ 1024 [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ 1025 [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ 1026 [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ 1027 [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ 1028 [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ 1029 [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ 1030 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ 1031 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ 1032 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ 1033 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ 1034 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ 1035 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ 1036 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ 1037 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ 1038 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ 1039 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ 1040 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ 1041 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ 1042 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ 1043 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ 1044 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ 1045 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ 1046 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ 1047 1048 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 1049 { 1050 return bcm63xx_irqs[irq]; 1051 } 1052 1053 /* 1054 * return installed memory size 1055 */ 1056 unsigned int bcm63xx_get_memory_size(void); 1057 1058 void bcm63xx_machine_halt(void); 1059 1060 void bcm63xx_machine_reboot(void); 1061 1062 #endif /* !BCM63XX_CPU_H_ */ 1063