1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * 3384740dcSRalf Baechle * BRIEF MODULE DESCRIPTION 4384740dcSRalf Baechle * Include file for Alchemy Semiconductor's Au1k CPU. 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * Copyright 2004 Embedded Edge, LLC 7384740dcSRalf Baechle * dan@embeddededge.com 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * This program is free software; you can redistribute it and/or modify it 10384740dcSRalf Baechle * under the terms of the GNU General Public License as published by the 11384740dcSRalf Baechle * Free Software Foundation; either version 2 of the License, or (at your 12384740dcSRalf Baechle * option) any later version. 13384740dcSRalf Baechle * 14384740dcSRalf Baechle * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15384740dcSRalf Baechle * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16384740dcSRalf Baechle * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17384740dcSRalf Baechle * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18384740dcSRalf Baechle * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19384740dcSRalf Baechle * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20384740dcSRalf Baechle * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21384740dcSRalf Baechle * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22384740dcSRalf Baechle * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23384740dcSRalf Baechle * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24384740dcSRalf Baechle * 25384740dcSRalf Baechle * You should have received a copy of the GNU General Public License along 26384740dcSRalf Baechle * with this program; if not, write to the Free Software Foundation, Inc., 27384740dcSRalf Baechle * 675 Mass Ave, Cambridge, MA 02139, USA. 28384740dcSRalf Baechle */ 29384740dcSRalf Baechle 30384740dcSRalf Baechle /* Specifics for the Au1xxx Programmable Serial Controllers, first 31384740dcSRalf Baechle * seen in the AU1550 part. 32384740dcSRalf Baechle */ 33384740dcSRalf Baechle #ifndef _AU1000_PSC_H_ 34384740dcSRalf Baechle #define _AU1000_PSC_H_ 35384740dcSRalf Baechle 36384740dcSRalf Baechle /* The PSC base addresses. */ 37384740dcSRalf Baechle #ifdef CONFIG_SOC_AU1550 38384740dcSRalf Baechle #define PSC0_BASE_ADDR 0xb1a00000 39384740dcSRalf Baechle #define PSC1_BASE_ADDR 0xb1b00000 40384740dcSRalf Baechle #define PSC2_BASE_ADDR 0xb0a00000 41384740dcSRalf Baechle #define PSC3_BASE_ADDR 0xb0b00000 42384740dcSRalf Baechle #endif 43384740dcSRalf Baechle 44384740dcSRalf Baechle #ifdef CONFIG_SOC_AU1200 45384740dcSRalf Baechle #define PSC0_BASE_ADDR 0xb1a00000 46384740dcSRalf Baechle #define PSC1_BASE_ADDR 0xb1b00000 47384740dcSRalf Baechle #endif 48384740dcSRalf Baechle 49384740dcSRalf Baechle /* 50384740dcSRalf Baechle * The PSC select and control registers are common to all protocols. 51384740dcSRalf Baechle */ 52384740dcSRalf Baechle #define PSC_SEL_OFFSET 0x00000000 53384740dcSRalf Baechle #define PSC_CTRL_OFFSET 0x00000004 54384740dcSRalf Baechle 55384740dcSRalf Baechle #define PSC_SEL_CLK_MASK (3 << 4) 56384740dcSRalf Baechle #define PSC_SEL_CLK_INTCLK (0 << 4) 57384740dcSRalf Baechle #define PSC_SEL_CLK_EXTCLK (1 << 4) 58384740dcSRalf Baechle #define PSC_SEL_CLK_SERCLK (2 << 4) 59384740dcSRalf Baechle 60384740dcSRalf Baechle #define PSC_SEL_PS_MASK 0x00000007 61384740dcSRalf Baechle #define PSC_SEL_PS_DISABLED 0 62384740dcSRalf Baechle #define PSC_SEL_PS_SPIMODE 2 63384740dcSRalf Baechle #define PSC_SEL_PS_I2SMODE 3 64384740dcSRalf Baechle #define PSC_SEL_PS_AC97MODE 4 65384740dcSRalf Baechle #define PSC_SEL_PS_SMBUSMODE 5 66384740dcSRalf Baechle 67384740dcSRalf Baechle #define PSC_CTRL_DISABLE 0 68384740dcSRalf Baechle #define PSC_CTRL_SUSPEND 2 69384740dcSRalf Baechle #define PSC_CTRL_ENABLE 3 70384740dcSRalf Baechle 71384740dcSRalf Baechle /* AC97 Registers. */ 72384740dcSRalf Baechle #define PSC_AC97CFG_OFFSET 0x00000008 73384740dcSRalf Baechle #define PSC_AC97MSK_OFFSET 0x0000000c 74384740dcSRalf Baechle #define PSC_AC97PCR_OFFSET 0x00000010 75384740dcSRalf Baechle #define PSC_AC97STAT_OFFSET 0x00000014 76384740dcSRalf Baechle #define PSC_AC97EVNT_OFFSET 0x00000018 77384740dcSRalf Baechle #define PSC_AC97TXRX_OFFSET 0x0000001c 78384740dcSRalf Baechle #define PSC_AC97CDC_OFFSET 0x00000020 79384740dcSRalf Baechle #define PSC_AC97RST_OFFSET 0x00000024 80384740dcSRalf Baechle #define PSC_AC97GPO_OFFSET 0x00000028 81384740dcSRalf Baechle #define PSC_AC97GPI_OFFSET 0x0000002c 82384740dcSRalf Baechle 83384740dcSRalf Baechle #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) 84384740dcSRalf Baechle #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) 85384740dcSRalf Baechle #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) 86384740dcSRalf Baechle #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) 87384740dcSRalf Baechle #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) 88384740dcSRalf Baechle #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) 89384740dcSRalf Baechle #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) 90384740dcSRalf Baechle #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) 91384740dcSRalf Baechle #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) 92384740dcSRalf Baechle #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) 93384740dcSRalf Baechle #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) 94384740dcSRalf Baechle #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) 95384740dcSRalf Baechle 96384740dcSRalf Baechle /* AC97 Config Register. */ 97384740dcSRalf Baechle #define PSC_AC97CFG_RT_MASK (3 << 30) 98384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO1 (0 << 30) 99384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO2 (1 << 30) 100384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO4 (2 << 30) 101384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO8 (3 << 30) 102384740dcSRalf Baechle 103384740dcSRalf Baechle #define PSC_AC97CFG_TT_MASK (3 << 28) 104384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO1 (0 << 28) 105384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO2 (1 << 28) 106384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO4 (2 << 28) 107384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO8 (3 << 28) 108384740dcSRalf Baechle 109384740dcSRalf Baechle #define PSC_AC97CFG_DD_DISABLE (1 << 27) 110384740dcSRalf Baechle #define PSC_AC97CFG_DE_ENABLE (1 << 26) 111384740dcSRalf Baechle #define PSC_AC97CFG_SE_ENABLE (1 << 25) 112384740dcSRalf Baechle 113384740dcSRalf Baechle #define PSC_AC97CFG_LEN_MASK (0xf << 21) 114384740dcSRalf Baechle #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) 115384740dcSRalf Baechle #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) 116384740dcSRalf Baechle #define PSC_AC97CFG_GE_ENABLE (1) 117384740dcSRalf Baechle 118384740dcSRalf Baechle /* Enable slots 3-12. */ 119384740dcSRalf Baechle #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) 120384740dcSRalf Baechle #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) 121384740dcSRalf Baechle 122384740dcSRalf Baechle /* 123384740dcSRalf Baechle * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. 124384740dcSRalf Baechle * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the 125384740dcSRalf Baechle * arithmetic in the macro. 126384740dcSRalf Baechle */ 127384740dcSRalf Baechle #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) 128384740dcSRalf Baechle #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) 129384740dcSRalf Baechle 130384740dcSRalf Baechle /* AC97 Mask Register. */ 131384740dcSRalf Baechle #define PSC_AC97MSK_GR (1 << 25) 132384740dcSRalf Baechle #define PSC_AC97MSK_CD (1 << 24) 133384740dcSRalf Baechle #define PSC_AC97MSK_RR (1 << 13) 134384740dcSRalf Baechle #define PSC_AC97MSK_RO (1 << 12) 135384740dcSRalf Baechle #define PSC_AC97MSK_RU (1 << 11) 136384740dcSRalf Baechle #define PSC_AC97MSK_TR (1 << 10) 137384740dcSRalf Baechle #define PSC_AC97MSK_TO (1 << 9) 138384740dcSRalf Baechle #define PSC_AC97MSK_TU (1 << 8) 139384740dcSRalf Baechle #define PSC_AC97MSK_RD (1 << 5) 140384740dcSRalf Baechle #define PSC_AC97MSK_TD (1 << 4) 141384740dcSRalf Baechle #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ 142384740dcSRalf Baechle PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ 143384740dcSRalf Baechle PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ 144384740dcSRalf Baechle PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ 145384740dcSRalf Baechle PSC_AC97MSK_RD | PSC_AC97MSK_TD) 146384740dcSRalf Baechle 147384740dcSRalf Baechle /* AC97 Protocol Control Register. */ 148384740dcSRalf Baechle #define PSC_AC97PCR_RC (1 << 6) 149384740dcSRalf Baechle #define PSC_AC97PCR_RP (1 << 5) 150384740dcSRalf Baechle #define PSC_AC97PCR_RS (1 << 4) 151384740dcSRalf Baechle #define PSC_AC97PCR_TC (1 << 2) 152384740dcSRalf Baechle #define PSC_AC97PCR_TP (1 << 1) 153384740dcSRalf Baechle #define PSC_AC97PCR_TS (1 << 0) 154384740dcSRalf Baechle 155384740dcSRalf Baechle /* AC97 Status register (read only). */ 156384740dcSRalf Baechle #define PSC_AC97STAT_CB (1 << 26) 157384740dcSRalf Baechle #define PSC_AC97STAT_CP (1 << 25) 158384740dcSRalf Baechle #define PSC_AC97STAT_CR (1 << 24) 159384740dcSRalf Baechle #define PSC_AC97STAT_RF (1 << 13) 160384740dcSRalf Baechle #define PSC_AC97STAT_RE (1 << 12) 161384740dcSRalf Baechle #define PSC_AC97STAT_RR (1 << 11) 162384740dcSRalf Baechle #define PSC_AC97STAT_TF (1 << 10) 163384740dcSRalf Baechle #define PSC_AC97STAT_TE (1 << 9) 164384740dcSRalf Baechle #define PSC_AC97STAT_TR (1 << 8) 165384740dcSRalf Baechle #define PSC_AC97STAT_RB (1 << 5) 166384740dcSRalf Baechle #define PSC_AC97STAT_TB (1 << 4) 167384740dcSRalf Baechle #define PSC_AC97STAT_DI (1 << 2) 168384740dcSRalf Baechle #define PSC_AC97STAT_DR (1 << 1) 169384740dcSRalf Baechle #define PSC_AC97STAT_SR (1 << 0) 170384740dcSRalf Baechle 171384740dcSRalf Baechle /* AC97 Event Register. */ 172384740dcSRalf Baechle #define PSC_AC97EVNT_GR (1 << 25) 173384740dcSRalf Baechle #define PSC_AC97EVNT_CD (1 << 24) 174384740dcSRalf Baechle #define PSC_AC97EVNT_RR (1 << 13) 175384740dcSRalf Baechle #define PSC_AC97EVNT_RO (1 << 12) 176384740dcSRalf Baechle #define PSC_AC97EVNT_RU (1 << 11) 177384740dcSRalf Baechle #define PSC_AC97EVNT_TR (1 << 10) 178384740dcSRalf Baechle #define PSC_AC97EVNT_TO (1 << 9) 179384740dcSRalf Baechle #define PSC_AC97EVNT_TU (1 << 8) 180384740dcSRalf Baechle #define PSC_AC97EVNT_RD (1 << 5) 181384740dcSRalf Baechle #define PSC_AC97EVNT_TD (1 << 4) 182384740dcSRalf Baechle 183384740dcSRalf Baechle /* CODEC Command Register. */ 184384740dcSRalf Baechle #define PSC_AC97CDC_RD (1 << 25) 185384740dcSRalf Baechle #define PSC_AC97CDC_ID_MASK (3 << 23) 186384740dcSRalf Baechle #define PSC_AC97CDC_INDX_MASK (0x7f << 16) 187384740dcSRalf Baechle #define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) 188384740dcSRalf Baechle #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) 189384740dcSRalf Baechle 190384740dcSRalf Baechle /* AC97 Reset Control Register. */ 191384740dcSRalf Baechle #define PSC_AC97RST_RST (1 << 1) 192384740dcSRalf Baechle #define PSC_AC97RST_SNC (1 << 0) 193384740dcSRalf Baechle 194384740dcSRalf Baechle /* PSC in I2S Mode. */ 195384740dcSRalf Baechle typedef struct psc_i2s { 196384740dcSRalf Baechle u32 psc_sel; 197384740dcSRalf Baechle u32 psc_ctrl; 198384740dcSRalf Baechle u32 psc_i2scfg; 199384740dcSRalf Baechle u32 psc_i2smsk; 200384740dcSRalf Baechle u32 psc_i2spcr; 201384740dcSRalf Baechle u32 psc_i2sstat; 202384740dcSRalf Baechle u32 psc_i2sevent; 203384740dcSRalf Baechle u32 psc_i2stxrx; 204384740dcSRalf Baechle u32 psc_i2sudf; 205384740dcSRalf Baechle } psc_i2s_t; 206384740dcSRalf Baechle 207384740dcSRalf Baechle #define PSC_I2SCFG_OFFSET 0x08 208384740dcSRalf Baechle #define PSC_I2SMASK_OFFSET 0x0C 209384740dcSRalf Baechle #define PSC_I2SPCR_OFFSET 0x10 210384740dcSRalf Baechle #define PSC_I2SSTAT_OFFSET 0x14 211384740dcSRalf Baechle #define PSC_I2SEVENT_OFFSET 0x18 212384740dcSRalf Baechle #define PSC_I2SRXTX_OFFSET 0x1C 213384740dcSRalf Baechle #define PSC_I2SUDF_OFFSET 0x20 214384740dcSRalf Baechle 215384740dcSRalf Baechle /* I2S Config Register. */ 216384740dcSRalf Baechle #define PSC_I2SCFG_RT_MASK (3 << 30) 217384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO1 (0 << 30) 218384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO2 (1 << 30) 219384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO4 (2 << 30) 220384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO8 (3 << 30) 221384740dcSRalf Baechle 222384740dcSRalf Baechle #define PSC_I2SCFG_TT_MASK (3 << 28) 223384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO1 (0 << 28) 224384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO2 (1 << 28) 225384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO4 (2 << 28) 226384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO8 (3 << 28) 227384740dcSRalf Baechle 228384740dcSRalf Baechle #define PSC_I2SCFG_DD_DISABLE (1 << 27) 229384740dcSRalf Baechle #define PSC_I2SCFG_DE_ENABLE (1 << 26) 230384740dcSRalf Baechle #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) 231384740dcSRalf Baechle #define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) 232384740dcSRalf Baechle #define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) 233384740dcSRalf Baechle #define PSC_I2SCFG_WI (1 << 15) 234384740dcSRalf Baechle 235384740dcSRalf Baechle #define PSC_I2SCFG_DIV_MASK (3 << 13) 236384740dcSRalf Baechle #define PSC_I2SCFG_DIV2 (0 << 13) 237384740dcSRalf Baechle #define PSC_I2SCFG_DIV4 (1 << 13) 238384740dcSRalf Baechle #define PSC_I2SCFG_DIV8 (2 << 13) 239384740dcSRalf Baechle #define PSC_I2SCFG_DIV16 (3 << 13) 240384740dcSRalf Baechle 241384740dcSRalf Baechle #define PSC_I2SCFG_BI (1 << 12) 242384740dcSRalf Baechle #define PSC_I2SCFG_BUF (1 << 11) 243384740dcSRalf Baechle #define PSC_I2SCFG_MLJ (1 << 10) 244384740dcSRalf Baechle #define PSC_I2SCFG_XM (1 << 9) 245384740dcSRalf Baechle 246384740dcSRalf Baechle /* The word length equation is simply LEN+1. */ 247384740dcSRalf Baechle #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) 248384740dcSRalf Baechle #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) 249384740dcSRalf Baechle 250384740dcSRalf Baechle #define PSC_I2SCFG_LB (1 << 2) 251384740dcSRalf Baechle #define PSC_I2SCFG_MLF (1 << 1) 252384740dcSRalf Baechle #define PSC_I2SCFG_MS (1 << 0) 253384740dcSRalf Baechle 254384740dcSRalf Baechle /* I2S Mask Register. */ 255384740dcSRalf Baechle #define PSC_I2SMSK_RR (1 << 13) 256384740dcSRalf Baechle #define PSC_I2SMSK_RO (1 << 12) 257384740dcSRalf Baechle #define PSC_I2SMSK_RU (1 << 11) 258384740dcSRalf Baechle #define PSC_I2SMSK_TR (1 << 10) 259384740dcSRalf Baechle #define PSC_I2SMSK_TO (1 << 9) 260384740dcSRalf Baechle #define PSC_I2SMSK_TU (1 << 8) 261384740dcSRalf Baechle #define PSC_I2SMSK_RD (1 << 5) 262384740dcSRalf Baechle #define PSC_I2SMSK_TD (1 << 4) 263384740dcSRalf Baechle #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \ 264384740dcSRalf Baechle PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ 265384740dcSRalf Baechle PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ 266384740dcSRalf Baechle PSC_I2SMSK_RD | PSC_I2SMSK_TD) 267384740dcSRalf Baechle 268384740dcSRalf Baechle /* I2S Protocol Control Register. */ 269384740dcSRalf Baechle #define PSC_I2SPCR_RC (1 << 6) 270384740dcSRalf Baechle #define PSC_I2SPCR_RP (1 << 5) 271384740dcSRalf Baechle #define PSC_I2SPCR_RS (1 << 4) 272384740dcSRalf Baechle #define PSC_I2SPCR_TC (1 << 2) 273384740dcSRalf Baechle #define PSC_I2SPCR_TP (1 << 1) 274384740dcSRalf Baechle #define PSC_I2SPCR_TS (1 << 0) 275384740dcSRalf Baechle 276384740dcSRalf Baechle /* I2S Status register (read only). */ 277384740dcSRalf Baechle #define PSC_I2SSTAT_RF (1 << 13) 278384740dcSRalf Baechle #define PSC_I2SSTAT_RE (1 << 12) 279384740dcSRalf Baechle #define PSC_I2SSTAT_RR (1 << 11) 280384740dcSRalf Baechle #define PSC_I2SSTAT_TF (1 << 10) 281384740dcSRalf Baechle #define PSC_I2SSTAT_TE (1 << 9) 282384740dcSRalf Baechle #define PSC_I2SSTAT_TR (1 << 8) 283384740dcSRalf Baechle #define PSC_I2SSTAT_RB (1 << 5) 284384740dcSRalf Baechle #define PSC_I2SSTAT_TB (1 << 4) 285384740dcSRalf Baechle #define PSC_I2SSTAT_DI (1 << 2) 286384740dcSRalf Baechle #define PSC_I2SSTAT_DR (1 << 1) 287384740dcSRalf Baechle #define PSC_I2SSTAT_SR (1 << 0) 288384740dcSRalf Baechle 289384740dcSRalf Baechle /* I2S Event Register. */ 290384740dcSRalf Baechle #define PSC_I2SEVNT_RR (1 << 13) 291384740dcSRalf Baechle #define PSC_I2SEVNT_RO (1 << 12) 292384740dcSRalf Baechle #define PSC_I2SEVNT_RU (1 << 11) 293384740dcSRalf Baechle #define PSC_I2SEVNT_TR (1 << 10) 294384740dcSRalf Baechle #define PSC_I2SEVNT_TO (1 << 9) 295384740dcSRalf Baechle #define PSC_I2SEVNT_TU (1 << 8) 296384740dcSRalf Baechle #define PSC_I2SEVNT_RD (1 << 5) 297384740dcSRalf Baechle #define PSC_I2SEVNT_TD (1 << 4) 298384740dcSRalf Baechle 299384740dcSRalf Baechle /* PSC in SPI Mode. */ 300384740dcSRalf Baechle typedef struct psc_spi { 301384740dcSRalf Baechle u32 psc_sel; 302384740dcSRalf Baechle u32 psc_ctrl; 303384740dcSRalf Baechle u32 psc_spicfg; 304384740dcSRalf Baechle u32 psc_spimsk; 305384740dcSRalf Baechle u32 psc_spipcr; 306384740dcSRalf Baechle u32 psc_spistat; 307384740dcSRalf Baechle u32 psc_spievent; 308384740dcSRalf Baechle u32 psc_spitxrx; 309384740dcSRalf Baechle } psc_spi_t; 310384740dcSRalf Baechle 311384740dcSRalf Baechle /* SPI Config Register. */ 312384740dcSRalf Baechle #define PSC_SPICFG_RT_MASK (3 << 30) 313384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO1 (0 << 30) 314384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO2 (1 << 30) 315384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO4 (2 << 30) 316384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO8 (3 << 30) 317384740dcSRalf Baechle 318384740dcSRalf Baechle #define PSC_SPICFG_TT_MASK (3 << 28) 319384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO1 (0 << 28) 320384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO2 (1 << 28) 321384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO4 (2 << 28) 322384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO8 (3 << 28) 323384740dcSRalf Baechle 324384740dcSRalf Baechle #define PSC_SPICFG_DD_DISABLE (1 << 27) 325384740dcSRalf Baechle #define PSC_SPICFG_DE_ENABLE (1 << 26) 326384740dcSRalf Baechle #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) 327384740dcSRalf Baechle #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) 328384740dcSRalf Baechle 329384740dcSRalf Baechle #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) 330384740dcSRalf Baechle #define PSC_SPICFG_DIV2 0 331384740dcSRalf Baechle #define PSC_SPICFG_DIV4 1 332384740dcSRalf Baechle #define PSC_SPICFG_DIV8 2 333384740dcSRalf Baechle #define PSC_SPICFG_DIV16 3 334384740dcSRalf Baechle 335384740dcSRalf Baechle #define PSC_SPICFG_BI (1 << 12) 336384740dcSRalf Baechle #define PSC_SPICFG_PSE (1 << 11) 337384740dcSRalf Baechle #define PSC_SPICFG_CGE (1 << 10) 338384740dcSRalf Baechle #define PSC_SPICFG_CDE (1 << 9) 339384740dcSRalf Baechle 340384740dcSRalf Baechle #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) 341384740dcSRalf Baechle #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) 342384740dcSRalf Baechle 343384740dcSRalf Baechle #define PSC_SPICFG_LB (1 << 3) 344384740dcSRalf Baechle #define PSC_SPICFG_MLF (1 << 1) 345384740dcSRalf Baechle #define PSC_SPICFG_MO (1 << 0) 346384740dcSRalf Baechle 347384740dcSRalf Baechle /* SPI Mask Register. */ 348384740dcSRalf Baechle #define PSC_SPIMSK_MM (1 << 16) 349384740dcSRalf Baechle #define PSC_SPIMSK_RR (1 << 13) 350384740dcSRalf Baechle #define PSC_SPIMSK_RO (1 << 12) 351384740dcSRalf Baechle #define PSC_SPIMSK_RU (1 << 11) 352384740dcSRalf Baechle #define PSC_SPIMSK_TR (1 << 10) 353384740dcSRalf Baechle #define PSC_SPIMSK_TO (1 << 9) 354384740dcSRalf Baechle #define PSC_SPIMSK_TU (1 << 8) 355384740dcSRalf Baechle #define PSC_SPIMSK_SD (1 << 5) 356384740dcSRalf Baechle #define PSC_SPIMSK_MD (1 << 4) 357384740dcSRalf Baechle #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ 358384740dcSRalf Baechle PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ 359384740dcSRalf Baechle PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ 360384740dcSRalf Baechle PSC_SPIMSK_MD) 361384740dcSRalf Baechle 362384740dcSRalf Baechle /* SPI Protocol Control Register. */ 363384740dcSRalf Baechle #define PSC_SPIPCR_RC (1 << 6) 364384740dcSRalf Baechle #define PSC_SPIPCR_SP (1 << 5) 365384740dcSRalf Baechle #define PSC_SPIPCR_SS (1 << 4) 366384740dcSRalf Baechle #define PSC_SPIPCR_TC (1 << 2) 367384740dcSRalf Baechle #define PSC_SPIPCR_MS (1 << 0) 368384740dcSRalf Baechle 369384740dcSRalf Baechle /* SPI Status register (read only). */ 370384740dcSRalf Baechle #define PSC_SPISTAT_RF (1 << 13) 371384740dcSRalf Baechle #define PSC_SPISTAT_RE (1 << 12) 372384740dcSRalf Baechle #define PSC_SPISTAT_RR (1 << 11) 373384740dcSRalf Baechle #define PSC_SPISTAT_TF (1 << 10) 374384740dcSRalf Baechle #define PSC_SPISTAT_TE (1 << 9) 375384740dcSRalf Baechle #define PSC_SPISTAT_TR (1 << 8) 376384740dcSRalf Baechle #define PSC_SPISTAT_SB (1 << 5) 377384740dcSRalf Baechle #define PSC_SPISTAT_MB (1 << 4) 378384740dcSRalf Baechle #define PSC_SPISTAT_DI (1 << 2) 379384740dcSRalf Baechle #define PSC_SPISTAT_DR (1 << 1) 380384740dcSRalf Baechle #define PSC_SPISTAT_SR (1 << 0) 381384740dcSRalf Baechle 382384740dcSRalf Baechle /* SPI Event Register. */ 383384740dcSRalf Baechle #define PSC_SPIEVNT_MM (1 << 16) 384384740dcSRalf Baechle #define PSC_SPIEVNT_RR (1 << 13) 385384740dcSRalf Baechle #define PSC_SPIEVNT_RO (1 << 12) 386384740dcSRalf Baechle #define PSC_SPIEVNT_RU (1 << 11) 387384740dcSRalf Baechle #define PSC_SPIEVNT_TR (1 << 10) 388384740dcSRalf Baechle #define PSC_SPIEVNT_TO (1 << 9) 389384740dcSRalf Baechle #define PSC_SPIEVNT_TU (1 << 8) 390384740dcSRalf Baechle #define PSC_SPIEVNT_SD (1 << 5) 391384740dcSRalf Baechle #define PSC_SPIEVNT_MD (1 << 4) 392384740dcSRalf Baechle 393384740dcSRalf Baechle /* Transmit register control. */ 394384740dcSRalf Baechle #define PSC_SPITXRX_LC (1 << 29) 395384740dcSRalf Baechle #define PSC_SPITXRX_SR (1 << 28) 396384740dcSRalf Baechle 397384740dcSRalf Baechle /* PSC in SMBus (I2C) Mode. */ 398384740dcSRalf Baechle typedef struct psc_smb { 399384740dcSRalf Baechle u32 psc_sel; 400384740dcSRalf Baechle u32 psc_ctrl; 401384740dcSRalf Baechle u32 psc_smbcfg; 402384740dcSRalf Baechle u32 psc_smbmsk; 403384740dcSRalf Baechle u32 psc_smbpcr; 404384740dcSRalf Baechle u32 psc_smbstat; 405384740dcSRalf Baechle u32 psc_smbevnt; 406384740dcSRalf Baechle u32 psc_smbtxrx; 407384740dcSRalf Baechle u32 psc_smbtmr; 408384740dcSRalf Baechle } psc_smb_t; 409384740dcSRalf Baechle 410384740dcSRalf Baechle /* SMBus Config Register. */ 411384740dcSRalf Baechle #define PSC_SMBCFG_RT_MASK (3 << 30) 412384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO1 (0 << 30) 413384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO2 (1 << 30) 414384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO4 (2 << 30) 415384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO8 (3 << 30) 416384740dcSRalf Baechle 417384740dcSRalf Baechle #define PSC_SMBCFG_TT_MASK (3 << 28) 418384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO1 (0 << 28) 419384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO2 (1 << 28) 420384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO4 (2 << 28) 421384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO8 (3 << 28) 422384740dcSRalf Baechle 423384740dcSRalf Baechle #define PSC_SMBCFG_DD_DISABLE (1 << 27) 424384740dcSRalf Baechle #define PSC_SMBCFG_DE_ENABLE (1 << 26) 425384740dcSRalf Baechle 426384740dcSRalf Baechle #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) 427384740dcSRalf Baechle #define PSC_SMBCFG_DIV2 0 428384740dcSRalf Baechle #define PSC_SMBCFG_DIV4 1 429384740dcSRalf Baechle #define PSC_SMBCFG_DIV8 2 430384740dcSRalf Baechle #define PSC_SMBCFG_DIV16 3 431384740dcSRalf Baechle 432384740dcSRalf Baechle #define PSC_SMBCFG_GCE (1 << 9) 433384740dcSRalf Baechle #define PSC_SMBCFG_SFM (1 << 8) 434384740dcSRalf Baechle 435384740dcSRalf Baechle #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) 436384740dcSRalf Baechle 437384740dcSRalf Baechle /* SMBus Mask Register. */ 438384740dcSRalf Baechle #define PSC_SMBMSK_DN (1 << 30) 439384740dcSRalf Baechle #define PSC_SMBMSK_AN (1 << 29) 440384740dcSRalf Baechle #define PSC_SMBMSK_AL (1 << 28) 441384740dcSRalf Baechle #define PSC_SMBMSK_RR (1 << 13) 442384740dcSRalf Baechle #define PSC_SMBMSK_RO (1 << 12) 443384740dcSRalf Baechle #define PSC_SMBMSK_RU (1 << 11) 444384740dcSRalf Baechle #define PSC_SMBMSK_TR (1 << 10) 445384740dcSRalf Baechle #define PSC_SMBMSK_TO (1 << 9) 446384740dcSRalf Baechle #define PSC_SMBMSK_TU (1 << 8) 447384740dcSRalf Baechle #define PSC_SMBMSK_SD (1 << 5) 448384740dcSRalf Baechle #define PSC_SMBMSK_MD (1 << 4) 449384740dcSRalf Baechle #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ 450384740dcSRalf Baechle PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ 451384740dcSRalf Baechle PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ 452384740dcSRalf Baechle PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ 453384740dcSRalf Baechle PSC_SMBMSK_MD) 454384740dcSRalf Baechle 455384740dcSRalf Baechle /* SMBus Protocol Control Register. */ 456384740dcSRalf Baechle #define PSC_SMBPCR_DC (1 << 2) 457384740dcSRalf Baechle #define PSC_SMBPCR_MS (1 << 0) 458384740dcSRalf Baechle 459384740dcSRalf Baechle /* SMBus Status register (read only). */ 460384740dcSRalf Baechle #define PSC_SMBSTAT_BB (1 << 28) 461384740dcSRalf Baechle #define PSC_SMBSTAT_RF (1 << 13) 462384740dcSRalf Baechle #define PSC_SMBSTAT_RE (1 << 12) 463384740dcSRalf Baechle #define PSC_SMBSTAT_RR (1 << 11) 464384740dcSRalf Baechle #define PSC_SMBSTAT_TF (1 << 10) 465384740dcSRalf Baechle #define PSC_SMBSTAT_TE (1 << 9) 466384740dcSRalf Baechle #define PSC_SMBSTAT_TR (1 << 8) 467384740dcSRalf Baechle #define PSC_SMBSTAT_SB (1 << 5) 468384740dcSRalf Baechle #define PSC_SMBSTAT_MB (1 << 4) 469384740dcSRalf Baechle #define PSC_SMBSTAT_DI (1 << 2) 470384740dcSRalf Baechle #define PSC_SMBSTAT_DR (1 << 1) 471384740dcSRalf Baechle #define PSC_SMBSTAT_SR (1 << 0) 472384740dcSRalf Baechle 473384740dcSRalf Baechle /* SMBus Event Register. */ 474384740dcSRalf Baechle #define PSC_SMBEVNT_DN (1 << 30) 475384740dcSRalf Baechle #define PSC_SMBEVNT_AN (1 << 29) 476384740dcSRalf Baechle #define PSC_SMBEVNT_AL (1 << 28) 477384740dcSRalf Baechle #define PSC_SMBEVNT_RR (1 << 13) 478384740dcSRalf Baechle #define PSC_SMBEVNT_RO (1 << 12) 479384740dcSRalf Baechle #define PSC_SMBEVNT_RU (1 << 11) 480384740dcSRalf Baechle #define PSC_SMBEVNT_TR (1 << 10) 481384740dcSRalf Baechle #define PSC_SMBEVNT_TO (1 << 9) 482384740dcSRalf Baechle #define PSC_SMBEVNT_TU (1 << 8) 483384740dcSRalf Baechle #define PSC_SMBEVNT_SD (1 << 5) 484384740dcSRalf Baechle #define PSC_SMBEVNT_MD (1 << 4) 485384740dcSRalf Baechle #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ 486384740dcSRalf Baechle PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ 487384740dcSRalf Baechle PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ 488384740dcSRalf Baechle PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ 489384740dcSRalf Baechle PSC_SMBEVNT_MD) 490384740dcSRalf Baechle 491384740dcSRalf Baechle /* Transmit register control. */ 492384740dcSRalf Baechle #define PSC_SMBTXRX_RSR (1 << 28) 493384740dcSRalf Baechle #define PSC_SMBTXRX_STP (1 << 29) 494384740dcSRalf Baechle #define PSC_SMBTXRX_DATAMASK 0xff 495384740dcSRalf Baechle 496384740dcSRalf Baechle /* SMBus protocol timers register. */ 497384740dcSRalf Baechle #define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) 498384740dcSRalf Baechle #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) 499384740dcSRalf Baechle #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) 500384740dcSRalf Baechle #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) 501384740dcSRalf Baechle #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) 502384740dcSRalf Baechle #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) 503384740dcSRalf Baechle #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) 504384740dcSRalf Baechle 505384740dcSRalf Baechle #endif /* _AU1000_PSC_H_ */ 506