1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * 3384740dcSRalf Baechle * BRIEF MODULE DESCRIPTION 4384740dcSRalf Baechle * Include file for Alchemy Semiconductor's Au1k CPU. 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * Copyright 2004 Embedded Edge, LLC 7384740dcSRalf Baechle * dan@embeddededge.com 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * This program is free software; you can redistribute it and/or modify it 10384740dcSRalf Baechle * under the terms of the GNU General Public License as published by the 11384740dcSRalf Baechle * Free Software Foundation; either version 2 of the License, or (at your 12384740dcSRalf Baechle * option) any later version. 13384740dcSRalf Baechle * 14384740dcSRalf Baechle * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15384740dcSRalf Baechle * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16384740dcSRalf Baechle * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17384740dcSRalf Baechle * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18384740dcSRalf Baechle * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19384740dcSRalf Baechle * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20384740dcSRalf Baechle * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21384740dcSRalf Baechle * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22384740dcSRalf Baechle * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23384740dcSRalf Baechle * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24384740dcSRalf Baechle * 25384740dcSRalf Baechle * You should have received a copy of the GNU General Public License along 26384740dcSRalf Baechle * with this program; if not, write to the Free Software Foundation, Inc., 27384740dcSRalf Baechle * 675 Mass Ave, Cambridge, MA 02139, USA. 28384740dcSRalf Baechle */ 29384740dcSRalf Baechle 30384740dcSRalf Baechle /* Specifics for the Au1xxx Programmable Serial Controllers, first 31384740dcSRalf Baechle * seen in the AU1550 part. 32384740dcSRalf Baechle */ 33384740dcSRalf Baechle #ifndef _AU1000_PSC_H_ 34384740dcSRalf Baechle #define _AU1000_PSC_H_ 35384740dcSRalf Baechle 36384740dcSRalf Baechle /* 37384740dcSRalf Baechle * The PSC select and control registers are common to all protocols. 38384740dcSRalf Baechle */ 39384740dcSRalf Baechle #define PSC_SEL_OFFSET 0x00000000 40384740dcSRalf Baechle #define PSC_CTRL_OFFSET 0x00000004 41384740dcSRalf Baechle 42384740dcSRalf Baechle #define PSC_SEL_CLK_MASK (3 << 4) 43384740dcSRalf Baechle #define PSC_SEL_CLK_INTCLK (0 << 4) 44384740dcSRalf Baechle #define PSC_SEL_CLK_EXTCLK (1 << 4) 45384740dcSRalf Baechle #define PSC_SEL_CLK_SERCLK (2 << 4) 46384740dcSRalf Baechle 47384740dcSRalf Baechle #define PSC_SEL_PS_MASK 0x00000007 48384740dcSRalf Baechle #define PSC_SEL_PS_DISABLED 0 49384740dcSRalf Baechle #define PSC_SEL_PS_SPIMODE 2 50384740dcSRalf Baechle #define PSC_SEL_PS_I2SMODE 3 51384740dcSRalf Baechle #define PSC_SEL_PS_AC97MODE 4 52384740dcSRalf Baechle #define PSC_SEL_PS_SMBUSMODE 5 53384740dcSRalf Baechle 54384740dcSRalf Baechle #define PSC_CTRL_DISABLE 0 55384740dcSRalf Baechle #define PSC_CTRL_SUSPEND 2 56384740dcSRalf Baechle #define PSC_CTRL_ENABLE 3 57384740dcSRalf Baechle 58384740dcSRalf Baechle /* AC97 Registers. */ 59384740dcSRalf Baechle #define PSC_AC97CFG_OFFSET 0x00000008 60384740dcSRalf Baechle #define PSC_AC97MSK_OFFSET 0x0000000c 61384740dcSRalf Baechle #define PSC_AC97PCR_OFFSET 0x00000010 62384740dcSRalf Baechle #define PSC_AC97STAT_OFFSET 0x00000014 63384740dcSRalf Baechle #define PSC_AC97EVNT_OFFSET 0x00000018 64384740dcSRalf Baechle #define PSC_AC97TXRX_OFFSET 0x0000001c 65384740dcSRalf Baechle #define PSC_AC97CDC_OFFSET 0x00000020 66384740dcSRalf Baechle #define PSC_AC97RST_OFFSET 0x00000024 67384740dcSRalf Baechle #define PSC_AC97GPO_OFFSET 0x00000028 68384740dcSRalf Baechle #define PSC_AC97GPI_OFFSET 0x0000002c 69384740dcSRalf Baechle 70384740dcSRalf Baechle /* AC97 Config Register. */ 71384740dcSRalf Baechle #define PSC_AC97CFG_RT_MASK (3 << 30) 72384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO1 (0 << 30) 73384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO2 (1 << 30) 74384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO4 (2 << 30) 75384740dcSRalf Baechle #define PSC_AC97CFG_RT_FIFO8 (3 << 30) 76384740dcSRalf Baechle 77384740dcSRalf Baechle #define PSC_AC97CFG_TT_MASK (3 << 28) 78384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO1 (0 << 28) 79384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO2 (1 << 28) 80384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO4 (2 << 28) 81384740dcSRalf Baechle #define PSC_AC97CFG_TT_FIFO8 (3 << 28) 82384740dcSRalf Baechle 83384740dcSRalf Baechle #define PSC_AC97CFG_DD_DISABLE (1 << 27) 84384740dcSRalf Baechle #define PSC_AC97CFG_DE_ENABLE (1 << 26) 85384740dcSRalf Baechle #define PSC_AC97CFG_SE_ENABLE (1 << 25) 86384740dcSRalf Baechle 87384740dcSRalf Baechle #define PSC_AC97CFG_LEN_MASK (0xf << 21) 88384740dcSRalf Baechle #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) 89384740dcSRalf Baechle #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) 90384740dcSRalf Baechle #define PSC_AC97CFG_GE_ENABLE (1) 91384740dcSRalf Baechle 92384740dcSRalf Baechle /* Enable slots 3-12. */ 93384740dcSRalf Baechle #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) 94384740dcSRalf Baechle #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) 95384740dcSRalf Baechle 96384740dcSRalf Baechle /* 97384740dcSRalf Baechle * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. 98384740dcSRalf Baechle * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the 99384740dcSRalf Baechle * arithmetic in the macro. 100384740dcSRalf Baechle */ 101384740dcSRalf Baechle #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) 102384740dcSRalf Baechle #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) 103384740dcSRalf Baechle 104384740dcSRalf Baechle /* AC97 Mask Register. */ 105384740dcSRalf Baechle #define PSC_AC97MSK_GR (1 << 25) 106384740dcSRalf Baechle #define PSC_AC97MSK_CD (1 << 24) 107384740dcSRalf Baechle #define PSC_AC97MSK_RR (1 << 13) 108384740dcSRalf Baechle #define PSC_AC97MSK_RO (1 << 12) 109384740dcSRalf Baechle #define PSC_AC97MSK_RU (1 << 11) 110384740dcSRalf Baechle #define PSC_AC97MSK_TR (1 << 10) 111384740dcSRalf Baechle #define PSC_AC97MSK_TO (1 << 9) 112384740dcSRalf Baechle #define PSC_AC97MSK_TU (1 << 8) 113384740dcSRalf Baechle #define PSC_AC97MSK_RD (1 << 5) 114384740dcSRalf Baechle #define PSC_AC97MSK_TD (1 << 4) 115384740dcSRalf Baechle #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ 116384740dcSRalf Baechle PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ 117384740dcSRalf Baechle PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ 118384740dcSRalf Baechle PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ 119384740dcSRalf Baechle PSC_AC97MSK_RD | PSC_AC97MSK_TD) 120384740dcSRalf Baechle 121384740dcSRalf Baechle /* AC97 Protocol Control Register. */ 122384740dcSRalf Baechle #define PSC_AC97PCR_RC (1 << 6) 123384740dcSRalf Baechle #define PSC_AC97PCR_RP (1 << 5) 124384740dcSRalf Baechle #define PSC_AC97PCR_RS (1 << 4) 125384740dcSRalf Baechle #define PSC_AC97PCR_TC (1 << 2) 126384740dcSRalf Baechle #define PSC_AC97PCR_TP (1 << 1) 127384740dcSRalf Baechle #define PSC_AC97PCR_TS (1 << 0) 128384740dcSRalf Baechle 129384740dcSRalf Baechle /* AC97 Status register (read only). */ 130384740dcSRalf Baechle #define PSC_AC97STAT_CB (1 << 26) 131384740dcSRalf Baechle #define PSC_AC97STAT_CP (1 << 25) 132384740dcSRalf Baechle #define PSC_AC97STAT_CR (1 << 24) 133384740dcSRalf Baechle #define PSC_AC97STAT_RF (1 << 13) 134384740dcSRalf Baechle #define PSC_AC97STAT_RE (1 << 12) 135384740dcSRalf Baechle #define PSC_AC97STAT_RR (1 << 11) 136384740dcSRalf Baechle #define PSC_AC97STAT_TF (1 << 10) 137384740dcSRalf Baechle #define PSC_AC97STAT_TE (1 << 9) 138384740dcSRalf Baechle #define PSC_AC97STAT_TR (1 << 8) 139384740dcSRalf Baechle #define PSC_AC97STAT_RB (1 << 5) 140384740dcSRalf Baechle #define PSC_AC97STAT_TB (1 << 4) 141384740dcSRalf Baechle #define PSC_AC97STAT_DI (1 << 2) 142384740dcSRalf Baechle #define PSC_AC97STAT_DR (1 << 1) 143384740dcSRalf Baechle #define PSC_AC97STAT_SR (1 << 0) 144384740dcSRalf Baechle 145384740dcSRalf Baechle /* AC97 Event Register. */ 146384740dcSRalf Baechle #define PSC_AC97EVNT_GR (1 << 25) 147384740dcSRalf Baechle #define PSC_AC97EVNT_CD (1 << 24) 148384740dcSRalf Baechle #define PSC_AC97EVNT_RR (1 << 13) 149384740dcSRalf Baechle #define PSC_AC97EVNT_RO (1 << 12) 150384740dcSRalf Baechle #define PSC_AC97EVNT_RU (1 << 11) 151384740dcSRalf Baechle #define PSC_AC97EVNT_TR (1 << 10) 152384740dcSRalf Baechle #define PSC_AC97EVNT_TO (1 << 9) 153384740dcSRalf Baechle #define PSC_AC97EVNT_TU (1 << 8) 154384740dcSRalf Baechle #define PSC_AC97EVNT_RD (1 << 5) 155384740dcSRalf Baechle #define PSC_AC97EVNT_TD (1 << 4) 156384740dcSRalf Baechle 157384740dcSRalf Baechle /* CODEC Command Register. */ 158384740dcSRalf Baechle #define PSC_AC97CDC_RD (1 << 25) 159384740dcSRalf Baechle #define PSC_AC97CDC_ID_MASK (3 << 23) 160384740dcSRalf Baechle #define PSC_AC97CDC_INDX_MASK (0x7f << 16) 161384740dcSRalf Baechle #define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) 162384740dcSRalf Baechle #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) 163384740dcSRalf Baechle 164384740dcSRalf Baechle /* AC97 Reset Control Register. */ 165384740dcSRalf Baechle #define PSC_AC97RST_RST (1 << 1) 166384740dcSRalf Baechle #define PSC_AC97RST_SNC (1 << 0) 167384740dcSRalf Baechle 168384740dcSRalf Baechle /* PSC in I2S Mode. */ 169384740dcSRalf Baechle typedef struct psc_i2s { 170384740dcSRalf Baechle u32 psc_sel; 171384740dcSRalf Baechle u32 psc_ctrl; 172384740dcSRalf Baechle u32 psc_i2scfg; 173384740dcSRalf Baechle u32 psc_i2smsk; 174384740dcSRalf Baechle u32 psc_i2spcr; 175384740dcSRalf Baechle u32 psc_i2sstat; 176384740dcSRalf Baechle u32 psc_i2sevent; 177384740dcSRalf Baechle u32 psc_i2stxrx; 178384740dcSRalf Baechle u32 psc_i2sudf; 179384740dcSRalf Baechle } psc_i2s_t; 180384740dcSRalf Baechle 181384740dcSRalf Baechle #define PSC_I2SCFG_OFFSET 0x08 182384740dcSRalf Baechle #define PSC_I2SMASK_OFFSET 0x0C 183384740dcSRalf Baechle #define PSC_I2SPCR_OFFSET 0x10 184384740dcSRalf Baechle #define PSC_I2SSTAT_OFFSET 0x14 185384740dcSRalf Baechle #define PSC_I2SEVENT_OFFSET 0x18 186384740dcSRalf Baechle #define PSC_I2SRXTX_OFFSET 0x1C 187384740dcSRalf Baechle #define PSC_I2SUDF_OFFSET 0x20 188384740dcSRalf Baechle 189384740dcSRalf Baechle /* I2S Config Register. */ 190384740dcSRalf Baechle #define PSC_I2SCFG_RT_MASK (3 << 30) 191384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO1 (0 << 30) 192384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO2 (1 << 30) 193384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO4 (2 << 30) 194384740dcSRalf Baechle #define PSC_I2SCFG_RT_FIFO8 (3 << 30) 195384740dcSRalf Baechle 196384740dcSRalf Baechle #define PSC_I2SCFG_TT_MASK (3 << 28) 197384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO1 (0 << 28) 198384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO2 (1 << 28) 199384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO4 (2 << 28) 200384740dcSRalf Baechle #define PSC_I2SCFG_TT_FIFO8 (3 << 28) 201384740dcSRalf Baechle 202384740dcSRalf Baechle #define PSC_I2SCFG_DD_DISABLE (1 << 27) 203384740dcSRalf Baechle #define PSC_I2SCFG_DE_ENABLE (1 << 26) 204384740dcSRalf Baechle #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) 205384740dcSRalf Baechle #define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) 206384740dcSRalf Baechle #define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) 207384740dcSRalf Baechle #define PSC_I2SCFG_WI (1 << 15) 208384740dcSRalf Baechle 209384740dcSRalf Baechle #define PSC_I2SCFG_DIV_MASK (3 << 13) 210384740dcSRalf Baechle #define PSC_I2SCFG_DIV2 (0 << 13) 211384740dcSRalf Baechle #define PSC_I2SCFG_DIV4 (1 << 13) 212384740dcSRalf Baechle #define PSC_I2SCFG_DIV8 (2 << 13) 213384740dcSRalf Baechle #define PSC_I2SCFG_DIV16 (3 << 13) 214384740dcSRalf Baechle 215384740dcSRalf Baechle #define PSC_I2SCFG_BI (1 << 12) 216384740dcSRalf Baechle #define PSC_I2SCFG_BUF (1 << 11) 217384740dcSRalf Baechle #define PSC_I2SCFG_MLJ (1 << 10) 218384740dcSRalf Baechle #define PSC_I2SCFG_XM (1 << 9) 219384740dcSRalf Baechle 220384740dcSRalf Baechle /* The word length equation is simply LEN+1. */ 221384740dcSRalf Baechle #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) 222384740dcSRalf Baechle #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) 223384740dcSRalf Baechle 224384740dcSRalf Baechle #define PSC_I2SCFG_LB (1 << 2) 225384740dcSRalf Baechle #define PSC_I2SCFG_MLF (1 << 1) 226384740dcSRalf Baechle #define PSC_I2SCFG_MS (1 << 0) 227384740dcSRalf Baechle 228384740dcSRalf Baechle /* I2S Mask Register. */ 229384740dcSRalf Baechle #define PSC_I2SMSK_RR (1 << 13) 230384740dcSRalf Baechle #define PSC_I2SMSK_RO (1 << 12) 231384740dcSRalf Baechle #define PSC_I2SMSK_RU (1 << 11) 232384740dcSRalf Baechle #define PSC_I2SMSK_TR (1 << 10) 233384740dcSRalf Baechle #define PSC_I2SMSK_TO (1 << 9) 234384740dcSRalf Baechle #define PSC_I2SMSK_TU (1 << 8) 235384740dcSRalf Baechle #define PSC_I2SMSK_RD (1 << 5) 236384740dcSRalf Baechle #define PSC_I2SMSK_TD (1 << 4) 237384740dcSRalf Baechle #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \ 238384740dcSRalf Baechle PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ 239384740dcSRalf Baechle PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ 240384740dcSRalf Baechle PSC_I2SMSK_RD | PSC_I2SMSK_TD) 241384740dcSRalf Baechle 242384740dcSRalf Baechle /* I2S Protocol Control Register. */ 243384740dcSRalf Baechle #define PSC_I2SPCR_RC (1 << 6) 244384740dcSRalf Baechle #define PSC_I2SPCR_RP (1 << 5) 245384740dcSRalf Baechle #define PSC_I2SPCR_RS (1 << 4) 246384740dcSRalf Baechle #define PSC_I2SPCR_TC (1 << 2) 247384740dcSRalf Baechle #define PSC_I2SPCR_TP (1 << 1) 248384740dcSRalf Baechle #define PSC_I2SPCR_TS (1 << 0) 249384740dcSRalf Baechle 250384740dcSRalf Baechle /* I2S Status register (read only). */ 251384740dcSRalf Baechle #define PSC_I2SSTAT_RF (1 << 13) 252384740dcSRalf Baechle #define PSC_I2SSTAT_RE (1 << 12) 253384740dcSRalf Baechle #define PSC_I2SSTAT_RR (1 << 11) 254384740dcSRalf Baechle #define PSC_I2SSTAT_TF (1 << 10) 255384740dcSRalf Baechle #define PSC_I2SSTAT_TE (1 << 9) 256384740dcSRalf Baechle #define PSC_I2SSTAT_TR (1 << 8) 257384740dcSRalf Baechle #define PSC_I2SSTAT_RB (1 << 5) 258384740dcSRalf Baechle #define PSC_I2SSTAT_TB (1 << 4) 259384740dcSRalf Baechle #define PSC_I2SSTAT_DI (1 << 2) 260384740dcSRalf Baechle #define PSC_I2SSTAT_DR (1 << 1) 261384740dcSRalf Baechle #define PSC_I2SSTAT_SR (1 << 0) 262384740dcSRalf Baechle 263384740dcSRalf Baechle /* I2S Event Register. */ 264384740dcSRalf Baechle #define PSC_I2SEVNT_RR (1 << 13) 265384740dcSRalf Baechle #define PSC_I2SEVNT_RO (1 << 12) 266384740dcSRalf Baechle #define PSC_I2SEVNT_RU (1 << 11) 267384740dcSRalf Baechle #define PSC_I2SEVNT_TR (1 << 10) 268384740dcSRalf Baechle #define PSC_I2SEVNT_TO (1 << 9) 269384740dcSRalf Baechle #define PSC_I2SEVNT_TU (1 << 8) 270384740dcSRalf Baechle #define PSC_I2SEVNT_RD (1 << 5) 271384740dcSRalf Baechle #define PSC_I2SEVNT_TD (1 << 4) 272384740dcSRalf Baechle 273384740dcSRalf Baechle /* PSC in SPI Mode. */ 274384740dcSRalf Baechle typedef struct psc_spi { 275384740dcSRalf Baechle u32 psc_sel; 276384740dcSRalf Baechle u32 psc_ctrl; 277384740dcSRalf Baechle u32 psc_spicfg; 278384740dcSRalf Baechle u32 psc_spimsk; 279384740dcSRalf Baechle u32 psc_spipcr; 280384740dcSRalf Baechle u32 psc_spistat; 281384740dcSRalf Baechle u32 psc_spievent; 282384740dcSRalf Baechle u32 psc_spitxrx; 283384740dcSRalf Baechle } psc_spi_t; 284384740dcSRalf Baechle 285384740dcSRalf Baechle /* SPI Config Register. */ 286384740dcSRalf Baechle #define PSC_SPICFG_RT_MASK (3 << 30) 287384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO1 (0 << 30) 288384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO2 (1 << 30) 289384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO4 (2 << 30) 290384740dcSRalf Baechle #define PSC_SPICFG_RT_FIFO8 (3 << 30) 291384740dcSRalf Baechle 292384740dcSRalf Baechle #define PSC_SPICFG_TT_MASK (3 << 28) 293384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO1 (0 << 28) 294384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO2 (1 << 28) 295384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO4 (2 << 28) 296384740dcSRalf Baechle #define PSC_SPICFG_TT_FIFO8 (3 << 28) 297384740dcSRalf Baechle 298384740dcSRalf Baechle #define PSC_SPICFG_DD_DISABLE (1 << 27) 299384740dcSRalf Baechle #define PSC_SPICFG_DE_ENABLE (1 << 26) 300384740dcSRalf Baechle #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) 301384740dcSRalf Baechle #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) 302384740dcSRalf Baechle 303384740dcSRalf Baechle #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) 304384740dcSRalf Baechle #define PSC_SPICFG_DIV2 0 305384740dcSRalf Baechle #define PSC_SPICFG_DIV4 1 306384740dcSRalf Baechle #define PSC_SPICFG_DIV8 2 307384740dcSRalf Baechle #define PSC_SPICFG_DIV16 3 308384740dcSRalf Baechle 309384740dcSRalf Baechle #define PSC_SPICFG_BI (1 << 12) 310384740dcSRalf Baechle #define PSC_SPICFG_PSE (1 << 11) 311384740dcSRalf Baechle #define PSC_SPICFG_CGE (1 << 10) 312384740dcSRalf Baechle #define PSC_SPICFG_CDE (1 << 9) 313384740dcSRalf Baechle 314384740dcSRalf Baechle #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) 315384740dcSRalf Baechle #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) 316384740dcSRalf Baechle 317384740dcSRalf Baechle #define PSC_SPICFG_LB (1 << 3) 318384740dcSRalf Baechle #define PSC_SPICFG_MLF (1 << 1) 319384740dcSRalf Baechle #define PSC_SPICFG_MO (1 << 0) 320384740dcSRalf Baechle 321384740dcSRalf Baechle /* SPI Mask Register. */ 322384740dcSRalf Baechle #define PSC_SPIMSK_MM (1 << 16) 323384740dcSRalf Baechle #define PSC_SPIMSK_RR (1 << 13) 324384740dcSRalf Baechle #define PSC_SPIMSK_RO (1 << 12) 325384740dcSRalf Baechle #define PSC_SPIMSK_RU (1 << 11) 326384740dcSRalf Baechle #define PSC_SPIMSK_TR (1 << 10) 327384740dcSRalf Baechle #define PSC_SPIMSK_TO (1 << 9) 328384740dcSRalf Baechle #define PSC_SPIMSK_TU (1 << 8) 329384740dcSRalf Baechle #define PSC_SPIMSK_SD (1 << 5) 330384740dcSRalf Baechle #define PSC_SPIMSK_MD (1 << 4) 331384740dcSRalf Baechle #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ 332384740dcSRalf Baechle PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ 333384740dcSRalf Baechle PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ 334384740dcSRalf Baechle PSC_SPIMSK_MD) 335384740dcSRalf Baechle 336384740dcSRalf Baechle /* SPI Protocol Control Register. */ 337384740dcSRalf Baechle #define PSC_SPIPCR_RC (1 << 6) 338384740dcSRalf Baechle #define PSC_SPIPCR_SP (1 << 5) 339384740dcSRalf Baechle #define PSC_SPIPCR_SS (1 << 4) 340384740dcSRalf Baechle #define PSC_SPIPCR_TC (1 << 2) 341384740dcSRalf Baechle #define PSC_SPIPCR_MS (1 << 0) 342384740dcSRalf Baechle 343384740dcSRalf Baechle /* SPI Status register (read only). */ 344384740dcSRalf Baechle #define PSC_SPISTAT_RF (1 << 13) 345384740dcSRalf Baechle #define PSC_SPISTAT_RE (1 << 12) 346384740dcSRalf Baechle #define PSC_SPISTAT_RR (1 << 11) 347384740dcSRalf Baechle #define PSC_SPISTAT_TF (1 << 10) 348384740dcSRalf Baechle #define PSC_SPISTAT_TE (1 << 9) 349384740dcSRalf Baechle #define PSC_SPISTAT_TR (1 << 8) 350384740dcSRalf Baechle #define PSC_SPISTAT_SB (1 << 5) 351384740dcSRalf Baechle #define PSC_SPISTAT_MB (1 << 4) 352384740dcSRalf Baechle #define PSC_SPISTAT_DI (1 << 2) 353384740dcSRalf Baechle #define PSC_SPISTAT_DR (1 << 1) 354384740dcSRalf Baechle #define PSC_SPISTAT_SR (1 << 0) 355384740dcSRalf Baechle 356384740dcSRalf Baechle /* SPI Event Register. */ 357384740dcSRalf Baechle #define PSC_SPIEVNT_MM (1 << 16) 358384740dcSRalf Baechle #define PSC_SPIEVNT_RR (1 << 13) 359384740dcSRalf Baechle #define PSC_SPIEVNT_RO (1 << 12) 360384740dcSRalf Baechle #define PSC_SPIEVNT_RU (1 << 11) 361384740dcSRalf Baechle #define PSC_SPIEVNT_TR (1 << 10) 362384740dcSRalf Baechle #define PSC_SPIEVNT_TO (1 << 9) 363384740dcSRalf Baechle #define PSC_SPIEVNT_TU (1 << 8) 364384740dcSRalf Baechle #define PSC_SPIEVNT_SD (1 << 5) 365384740dcSRalf Baechle #define PSC_SPIEVNT_MD (1 << 4) 366384740dcSRalf Baechle 367384740dcSRalf Baechle /* Transmit register control. */ 368384740dcSRalf Baechle #define PSC_SPITXRX_LC (1 << 29) 369384740dcSRalf Baechle #define PSC_SPITXRX_SR (1 << 28) 370384740dcSRalf Baechle 371384740dcSRalf Baechle /* SMBus Config Register. */ 372384740dcSRalf Baechle #define PSC_SMBCFG_RT_MASK (3 << 30) 373384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO1 (0 << 30) 374384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO2 (1 << 30) 375384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO4 (2 << 30) 376384740dcSRalf Baechle #define PSC_SMBCFG_RT_FIFO8 (3 << 30) 377384740dcSRalf Baechle 378384740dcSRalf Baechle #define PSC_SMBCFG_TT_MASK (3 << 28) 379384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO1 (0 << 28) 380384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO2 (1 << 28) 381384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO4 (2 << 28) 382384740dcSRalf Baechle #define PSC_SMBCFG_TT_FIFO8 (3 << 28) 383384740dcSRalf Baechle 384384740dcSRalf Baechle #define PSC_SMBCFG_DD_DISABLE (1 << 27) 385384740dcSRalf Baechle #define PSC_SMBCFG_DE_ENABLE (1 << 26) 386384740dcSRalf Baechle 387384740dcSRalf Baechle #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) 388384740dcSRalf Baechle #define PSC_SMBCFG_DIV2 0 389384740dcSRalf Baechle #define PSC_SMBCFG_DIV4 1 390384740dcSRalf Baechle #define PSC_SMBCFG_DIV8 2 391384740dcSRalf Baechle #define PSC_SMBCFG_DIV16 3 392384740dcSRalf Baechle 393384740dcSRalf Baechle #define PSC_SMBCFG_GCE (1 << 9) 394384740dcSRalf Baechle #define PSC_SMBCFG_SFM (1 << 8) 395384740dcSRalf Baechle 396384740dcSRalf Baechle #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) 397384740dcSRalf Baechle 398384740dcSRalf Baechle /* SMBus Mask Register. */ 399384740dcSRalf Baechle #define PSC_SMBMSK_DN (1 << 30) 400384740dcSRalf Baechle #define PSC_SMBMSK_AN (1 << 29) 401384740dcSRalf Baechle #define PSC_SMBMSK_AL (1 << 28) 402384740dcSRalf Baechle #define PSC_SMBMSK_RR (1 << 13) 403384740dcSRalf Baechle #define PSC_SMBMSK_RO (1 << 12) 404384740dcSRalf Baechle #define PSC_SMBMSK_RU (1 << 11) 405384740dcSRalf Baechle #define PSC_SMBMSK_TR (1 << 10) 406384740dcSRalf Baechle #define PSC_SMBMSK_TO (1 << 9) 407384740dcSRalf Baechle #define PSC_SMBMSK_TU (1 << 8) 408384740dcSRalf Baechle #define PSC_SMBMSK_SD (1 << 5) 409384740dcSRalf Baechle #define PSC_SMBMSK_MD (1 << 4) 410384740dcSRalf Baechle #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ 411384740dcSRalf Baechle PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ 412384740dcSRalf Baechle PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ 413384740dcSRalf Baechle PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ 414384740dcSRalf Baechle PSC_SMBMSK_MD) 415384740dcSRalf Baechle 416384740dcSRalf Baechle /* SMBus Protocol Control Register. */ 417384740dcSRalf Baechle #define PSC_SMBPCR_DC (1 << 2) 418384740dcSRalf Baechle #define PSC_SMBPCR_MS (1 << 0) 419384740dcSRalf Baechle 420384740dcSRalf Baechle /* SMBus Status register (read only). */ 421384740dcSRalf Baechle #define PSC_SMBSTAT_BB (1 << 28) 422384740dcSRalf Baechle #define PSC_SMBSTAT_RF (1 << 13) 423384740dcSRalf Baechle #define PSC_SMBSTAT_RE (1 << 12) 424384740dcSRalf Baechle #define PSC_SMBSTAT_RR (1 << 11) 425384740dcSRalf Baechle #define PSC_SMBSTAT_TF (1 << 10) 426384740dcSRalf Baechle #define PSC_SMBSTAT_TE (1 << 9) 427384740dcSRalf Baechle #define PSC_SMBSTAT_TR (1 << 8) 428384740dcSRalf Baechle #define PSC_SMBSTAT_SB (1 << 5) 429384740dcSRalf Baechle #define PSC_SMBSTAT_MB (1 << 4) 430384740dcSRalf Baechle #define PSC_SMBSTAT_DI (1 << 2) 431384740dcSRalf Baechle #define PSC_SMBSTAT_DR (1 << 1) 432384740dcSRalf Baechle #define PSC_SMBSTAT_SR (1 << 0) 433384740dcSRalf Baechle 434384740dcSRalf Baechle /* SMBus Event Register. */ 435384740dcSRalf Baechle #define PSC_SMBEVNT_DN (1 << 30) 436384740dcSRalf Baechle #define PSC_SMBEVNT_AN (1 << 29) 437384740dcSRalf Baechle #define PSC_SMBEVNT_AL (1 << 28) 438384740dcSRalf Baechle #define PSC_SMBEVNT_RR (1 << 13) 439384740dcSRalf Baechle #define PSC_SMBEVNT_RO (1 << 12) 440384740dcSRalf Baechle #define PSC_SMBEVNT_RU (1 << 11) 441384740dcSRalf Baechle #define PSC_SMBEVNT_TR (1 << 10) 442384740dcSRalf Baechle #define PSC_SMBEVNT_TO (1 << 9) 443384740dcSRalf Baechle #define PSC_SMBEVNT_TU (1 << 8) 444384740dcSRalf Baechle #define PSC_SMBEVNT_SD (1 << 5) 445384740dcSRalf Baechle #define PSC_SMBEVNT_MD (1 << 4) 446384740dcSRalf Baechle #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ 447384740dcSRalf Baechle PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ 448384740dcSRalf Baechle PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ 449384740dcSRalf Baechle PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ 450384740dcSRalf Baechle PSC_SMBEVNT_MD) 451384740dcSRalf Baechle 452384740dcSRalf Baechle /* Transmit register control. */ 453384740dcSRalf Baechle #define PSC_SMBTXRX_RSR (1 << 28) 454384740dcSRalf Baechle #define PSC_SMBTXRX_STP (1 << 29) 455384740dcSRalf Baechle #define PSC_SMBTXRX_DATAMASK 0xff 456384740dcSRalf Baechle 457384740dcSRalf Baechle /* SMBus protocol timers register. */ 458384740dcSRalf Baechle #define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) 459384740dcSRalf Baechle #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) 460384740dcSRalf Baechle #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) 461384740dcSRalf Baechle #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) 462384740dcSRalf Baechle #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) 463384740dcSRalf Baechle #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) 464384740dcSRalf Baechle #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) 465384740dcSRalf Baechle 466384740dcSRalf Baechle #endif /* _AU1000_PSC_H_ */ 467