1384740dcSRalf Baechle /*
2384740dcSRalf Baechle * BRIEF MODULE DESCRIPTION
3384740dcSRalf Baechle * Defines for using and allocating DMA channels on the Alchemy
4384740dcSRalf Baechle * Au1x00 MIPS processors.
5384740dcSRalf Baechle *
6384740dcSRalf Baechle * Copyright 2000, 2008 MontaVista Software Inc.
7384740dcSRalf Baechle * Author: MontaVista Software, Inc. <source@mvista.com>
8384740dcSRalf Baechle *
9384740dcSRalf Baechle * This program is free software; you can redistribute it and/or modify it
10384740dcSRalf Baechle * under the terms of the GNU General Public License as published by the
11384740dcSRalf Baechle * Free Software Foundation; either version 2 of the License, or (at your
12384740dcSRalf Baechle * option) any later version.
13384740dcSRalf Baechle *
14384740dcSRalf Baechle * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15384740dcSRalf Baechle * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16384740dcSRalf Baechle * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17384740dcSRalf Baechle * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18384740dcSRalf Baechle * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19384740dcSRalf Baechle * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20384740dcSRalf Baechle * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21384740dcSRalf Baechle * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22384740dcSRalf Baechle * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23384740dcSRalf Baechle * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24384740dcSRalf Baechle *
25384740dcSRalf Baechle * You should have received a copy of the GNU General Public License along
26384740dcSRalf Baechle * with this program; if not, write to the Free Software Foundation, Inc.,
27384740dcSRalf Baechle * 675 Mass Ave, Cambridge, MA 02139, USA.
28384740dcSRalf Baechle *
29384740dcSRalf Baechle */
30384740dcSRalf Baechle #ifndef __ASM_AU1000_DMA_H
31384740dcSRalf Baechle #define __ASM_AU1000_DMA_H
32384740dcSRalf Baechle
33384740dcSRalf Baechle #include <linux/io.h> /* need byte IO */
34384740dcSRalf Baechle #include <linux/spinlock.h> /* And spinlocks */
35384740dcSRalf Baechle #include <linux/delay.h>
36384740dcSRalf Baechle
37384740dcSRalf Baechle #define NUM_AU1000_DMA_CHANNELS 8
38384740dcSRalf Baechle
39384740dcSRalf Baechle /* DMA Channel Register Offsets */
40384740dcSRalf Baechle #define DMA_MODE_SET 0x00000000
41384740dcSRalf Baechle #define DMA_MODE_READ DMA_MODE_SET
42384740dcSRalf Baechle #define DMA_MODE_CLEAR 0x00000004
43384740dcSRalf Baechle /* DMA Mode register bits follow */
44384740dcSRalf Baechle #define DMA_DAH_MASK (0x0f << 20)
45384740dcSRalf Baechle #define DMA_DID_BIT 16
46384740dcSRalf Baechle #define DMA_DID_MASK (0x0f << DMA_DID_BIT)
47384740dcSRalf Baechle #define DMA_DS (1 << 15)
48384740dcSRalf Baechle #define DMA_BE (1 << 13)
49384740dcSRalf Baechle #define DMA_DR (1 << 12)
50384740dcSRalf Baechle #define DMA_TS8 (1 << 11)
51384740dcSRalf Baechle #define DMA_DW_BIT 9
52384740dcSRalf Baechle #define DMA_DW_MASK (0x03 << DMA_DW_BIT)
53384740dcSRalf Baechle #define DMA_DW8 (0 << DMA_DW_BIT)
54384740dcSRalf Baechle #define DMA_DW16 (1 << DMA_DW_BIT)
55384740dcSRalf Baechle #define DMA_DW32 (2 << DMA_DW_BIT)
56384740dcSRalf Baechle #define DMA_NC (1 << 8)
57384740dcSRalf Baechle #define DMA_IE (1 << 7)
58384740dcSRalf Baechle #define DMA_HALT (1 << 6)
59384740dcSRalf Baechle #define DMA_GO (1 << 5)
60384740dcSRalf Baechle #define DMA_AB (1 << 4)
61384740dcSRalf Baechle #define DMA_D1 (1 << 3)
62384740dcSRalf Baechle #define DMA_BE1 (1 << 2)
63384740dcSRalf Baechle #define DMA_D0 (1 << 1)
64384740dcSRalf Baechle #define DMA_BE0 (1 << 0)
65384740dcSRalf Baechle
66384740dcSRalf Baechle #define DMA_PERIPHERAL_ADDR 0x00000008
67384740dcSRalf Baechle #define DMA_BUFFER0_START 0x0000000C
68384740dcSRalf Baechle #define DMA_BUFFER1_START 0x00000014
69384740dcSRalf Baechle #define DMA_BUFFER0_COUNT 0x00000010
70384740dcSRalf Baechle #define DMA_BUFFER1_COUNT 0x00000018
71384740dcSRalf Baechle #define DMA_BAH_BIT 16
72384740dcSRalf Baechle #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
73384740dcSRalf Baechle #define DMA_COUNT_BIT 0
74384740dcSRalf Baechle #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
75384740dcSRalf Baechle
76384740dcSRalf Baechle /* DMA Device IDs follow */
77384740dcSRalf Baechle enum {
78384740dcSRalf Baechle DMA_ID_UART0_TX = 0,
79384740dcSRalf Baechle DMA_ID_UART0_RX,
80384740dcSRalf Baechle DMA_ID_GP04,
81384740dcSRalf Baechle DMA_ID_GP05,
82384740dcSRalf Baechle DMA_ID_AC97C_TX,
83384740dcSRalf Baechle DMA_ID_AC97C_RX,
84384740dcSRalf Baechle DMA_ID_UART3_TX,
85384740dcSRalf Baechle DMA_ID_UART3_RX,
86384740dcSRalf Baechle DMA_ID_USBDEV_EP0_RX,
87384740dcSRalf Baechle DMA_ID_USBDEV_EP0_TX,
88384740dcSRalf Baechle DMA_ID_USBDEV_EP2_TX,
89384740dcSRalf Baechle DMA_ID_USBDEV_EP3_TX,
90384740dcSRalf Baechle DMA_ID_USBDEV_EP4_RX,
91384740dcSRalf Baechle DMA_ID_USBDEV_EP5_RX,
92384740dcSRalf Baechle DMA_ID_I2S_TX,
93384740dcSRalf Baechle DMA_ID_I2S_RX,
94384740dcSRalf Baechle DMA_NUM_DEV
95384740dcSRalf Baechle };
96384740dcSRalf Baechle
97384740dcSRalf Baechle /* DMA Device ID's for 2nd bank (AU1100) follow */
98384740dcSRalf Baechle enum {
99384740dcSRalf Baechle DMA_ID_SD0_TX = 0,
100384740dcSRalf Baechle DMA_ID_SD0_RX,
101384740dcSRalf Baechle DMA_ID_SD1_TX,
102384740dcSRalf Baechle DMA_ID_SD1_RX,
103384740dcSRalf Baechle DMA_NUM_DEV_BANK2
104384740dcSRalf Baechle };
105384740dcSRalf Baechle
106384740dcSRalf Baechle struct dma_chan {
107384740dcSRalf Baechle int dev_id; /* this channel is allocated if >= 0, */
108384740dcSRalf Baechle /* free otherwise */
1092f73bfbeSManuel Lauss void __iomem *io;
110384740dcSRalf Baechle const char *dev_str;
111384740dcSRalf Baechle int irq;
112384740dcSRalf Baechle void *irq_dev;
113384740dcSRalf Baechle unsigned int fifo_addr;
114384740dcSRalf Baechle unsigned int mode;
115384740dcSRalf Baechle };
116384740dcSRalf Baechle
117384740dcSRalf Baechle /* These are in arch/mips/au1000/common/dma.c */
118384740dcSRalf Baechle extern struct dma_chan au1000_dma_table[];
119384740dcSRalf Baechle extern int request_au1000_dma(int dev_id,
120384740dcSRalf Baechle const char *dev_str,
121384740dcSRalf Baechle irq_handler_t irqhandler,
122384740dcSRalf Baechle unsigned long irqflags,
123384740dcSRalf Baechle void *irq_dev_id);
124384740dcSRalf Baechle extern void free_au1000_dma(unsigned int dmanr);
125384740dcSRalf Baechle extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
126384740dcSRalf Baechle int length, int *eof, void *data);
127384740dcSRalf Baechle extern void dump_au1000_dma_channel(unsigned int dmanr);
128384740dcSRalf Baechle extern spinlock_t au1000_dma_spin_lock;
129384740dcSRalf Baechle
get_dma_chan(unsigned int dmanr)130384740dcSRalf Baechle static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
131384740dcSRalf Baechle {
132384740dcSRalf Baechle if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
133384740dcSRalf Baechle au1000_dma_table[dmanr].dev_id < 0)
134384740dcSRalf Baechle return NULL;
135384740dcSRalf Baechle return &au1000_dma_table[dmanr];
136384740dcSRalf Baechle }
137384740dcSRalf Baechle
claim_dma_lock(void)138384740dcSRalf Baechle static inline unsigned long claim_dma_lock(void)
139384740dcSRalf Baechle {
140384740dcSRalf Baechle unsigned long flags;
141384740dcSRalf Baechle
142384740dcSRalf Baechle spin_lock_irqsave(&au1000_dma_spin_lock, flags);
143384740dcSRalf Baechle return flags;
144384740dcSRalf Baechle }
145384740dcSRalf Baechle
release_dma_lock(unsigned long flags)146384740dcSRalf Baechle static inline void release_dma_lock(unsigned long flags)
147384740dcSRalf Baechle {
148384740dcSRalf Baechle spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
149384740dcSRalf Baechle }
150384740dcSRalf Baechle
151384740dcSRalf Baechle /*
152384740dcSRalf Baechle * Set the DMA buffer enable bits in the mode register.
153384740dcSRalf Baechle */
enable_dma_buffer0(unsigned int dmanr)154384740dcSRalf Baechle static inline void enable_dma_buffer0(unsigned int dmanr)
155384740dcSRalf Baechle {
156384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
157384740dcSRalf Baechle
158384740dcSRalf Baechle if (!chan)
159384740dcSRalf Baechle return;
1602f73bfbeSManuel Lauss __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
161384740dcSRalf Baechle }
162384740dcSRalf Baechle
enable_dma_buffer1(unsigned int dmanr)163384740dcSRalf Baechle static inline void enable_dma_buffer1(unsigned int dmanr)
164384740dcSRalf Baechle {
165384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
166384740dcSRalf Baechle
167384740dcSRalf Baechle if (!chan)
168384740dcSRalf Baechle return;
1692f73bfbeSManuel Lauss __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
170384740dcSRalf Baechle }
enable_dma_buffers(unsigned int dmanr)171384740dcSRalf Baechle static inline void enable_dma_buffers(unsigned int dmanr)
172384740dcSRalf Baechle {
173384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
174384740dcSRalf Baechle
175384740dcSRalf Baechle if (!chan)
176384740dcSRalf Baechle return;
1772f73bfbeSManuel Lauss __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
178384740dcSRalf Baechle }
179384740dcSRalf Baechle
start_dma(unsigned int dmanr)180384740dcSRalf Baechle static inline void start_dma(unsigned int dmanr)
181384740dcSRalf Baechle {
182384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
183384740dcSRalf Baechle
184384740dcSRalf Baechle if (!chan)
185384740dcSRalf Baechle return;
1862f73bfbeSManuel Lauss __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
187384740dcSRalf Baechle }
188384740dcSRalf Baechle
189384740dcSRalf Baechle #define DMA_HALT_POLL 0x5000
190384740dcSRalf Baechle
halt_dma(unsigned int dmanr)191384740dcSRalf Baechle static inline void halt_dma(unsigned int dmanr)
192384740dcSRalf Baechle {
193384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
194384740dcSRalf Baechle int i;
195384740dcSRalf Baechle
196384740dcSRalf Baechle if (!chan)
197384740dcSRalf Baechle return;
1982f73bfbeSManuel Lauss __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
199384740dcSRalf Baechle
200384740dcSRalf Baechle /* Poll the halt bit */
201384740dcSRalf Baechle for (i = 0; i < DMA_HALT_POLL; i++)
2022f73bfbeSManuel Lauss if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
203384740dcSRalf Baechle break;
204384740dcSRalf Baechle if (i == DMA_HALT_POLL)
205384740dcSRalf Baechle printk(KERN_INFO "halt_dma: HALT poll expired!\n");
206384740dcSRalf Baechle }
207384740dcSRalf Baechle
disable_dma(unsigned int dmanr)208384740dcSRalf Baechle static inline void disable_dma(unsigned int dmanr)
209384740dcSRalf Baechle {
210384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
211384740dcSRalf Baechle
212384740dcSRalf Baechle if (!chan)
213384740dcSRalf Baechle return;
214384740dcSRalf Baechle
215384740dcSRalf Baechle halt_dma(dmanr);
216384740dcSRalf Baechle
217384740dcSRalf Baechle /* Now we can disable the buffers */
2182f73bfbeSManuel Lauss __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
219384740dcSRalf Baechle }
220384740dcSRalf Baechle
dma_halted(unsigned int dmanr)221384740dcSRalf Baechle static inline int dma_halted(unsigned int dmanr)
222384740dcSRalf Baechle {
223384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
224384740dcSRalf Baechle
225384740dcSRalf Baechle if (!chan)
226384740dcSRalf Baechle return 1;
2272f73bfbeSManuel Lauss return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
228384740dcSRalf Baechle }
229384740dcSRalf Baechle
230384740dcSRalf Baechle /* Initialize a DMA channel. */
init_dma(unsigned int dmanr)231384740dcSRalf Baechle static inline void init_dma(unsigned int dmanr)
232384740dcSRalf Baechle {
233384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
234384740dcSRalf Baechle u32 mode;
235384740dcSRalf Baechle
236384740dcSRalf Baechle if (!chan)
237384740dcSRalf Baechle return;
238384740dcSRalf Baechle
239384740dcSRalf Baechle disable_dma(dmanr);
240384740dcSRalf Baechle
241384740dcSRalf Baechle /* Set device FIFO address */
2422f73bfbeSManuel Lauss __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
243384740dcSRalf Baechle
244384740dcSRalf Baechle mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
245384740dcSRalf Baechle if (chan->irq)
246384740dcSRalf Baechle mode |= DMA_IE;
247384740dcSRalf Baechle
2482f73bfbeSManuel Lauss __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
2492f73bfbeSManuel Lauss __raw_writel(mode, chan->io + DMA_MODE_SET);
250384740dcSRalf Baechle }
251384740dcSRalf Baechle
252384740dcSRalf Baechle /*
253384740dcSRalf Baechle * Set mode for a specific DMA channel
254384740dcSRalf Baechle */
set_dma_mode(unsigned int dmanr,unsigned int mode)255384740dcSRalf Baechle static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
256384740dcSRalf Baechle {
257384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
258384740dcSRalf Baechle
259384740dcSRalf Baechle if (!chan)
260384740dcSRalf Baechle return;
261384740dcSRalf Baechle /*
262384740dcSRalf Baechle * set_dma_mode is only allowed to change endianess, direction,
263384740dcSRalf Baechle * transfer size, device FIFO width, and coherency settings.
264384740dcSRalf Baechle * Make sure anything else is masked off.
265384740dcSRalf Baechle */
266384740dcSRalf Baechle mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
267384740dcSRalf Baechle chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
268384740dcSRalf Baechle chan->mode |= mode;
269384740dcSRalf Baechle }
270384740dcSRalf Baechle
get_dma_mode(unsigned int dmanr)271384740dcSRalf Baechle static inline unsigned int get_dma_mode(unsigned int dmanr)
272384740dcSRalf Baechle {
273384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
274384740dcSRalf Baechle
275384740dcSRalf Baechle if (!chan)
276384740dcSRalf Baechle return 0;
277384740dcSRalf Baechle return chan->mode;
278384740dcSRalf Baechle }
279384740dcSRalf Baechle
get_dma_active_buffer(unsigned int dmanr)280384740dcSRalf Baechle static inline int get_dma_active_buffer(unsigned int dmanr)
281384740dcSRalf Baechle {
282384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
283384740dcSRalf Baechle
284384740dcSRalf Baechle if (!chan)
285384740dcSRalf Baechle return -1;
2862f73bfbeSManuel Lauss return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
287384740dcSRalf Baechle }
288384740dcSRalf Baechle
289384740dcSRalf Baechle /*
290384740dcSRalf Baechle * Set the device FIFO address for a specific DMA channel - only
291384740dcSRalf Baechle * applicable to GPO4 and GPO5. All the other devices have fixed
292384740dcSRalf Baechle * FIFO addresses.
293384740dcSRalf Baechle */
set_dma_fifo_addr(unsigned int dmanr,unsigned int a)294384740dcSRalf Baechle static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
295384740dcSRalf Baechle {
296384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
297384740dcSRalf Baechle
298384740dcSRalf Baechle if (!chan)
299384740dcSRalf Baechle return;
300384740dcSRalf Baechle
301384740dcSRalf Baechle if (chan->mode & DMA_DS) /* second bank of device IDs */
302384740dcSRalf Baechle return;
303384740dcSRalf Baechle
304384740dcSRalf Baechle if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
305384740dcSRalf Baechle return;
306384740dcSRalf Baechle
3072f73bfbeSManuel Lauss __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
308384740dcSRalf Baechle }
309384740dcSRalf Baechle
310384740dcSRalf Baechle /*
311384740dcSRalf Baechle * Clear the DMA buffer done bits in the mode register.
312384740dcSRalf Baechle */
clear_dma_done0(unsigned int dmanr)313384740dcSRalf Baechle static inline void clear_dma_done0(unsigned int dmanr)
314384740dcSRalf Baechle {
315384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
316384740dcSRalf Baechle
317384740dcSRalf Baechle if (!chan)
318384740dcSRalf Baechle return;
3192f73bfbeSManuel Lauss __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
320384740dcSRalf Baechle }
321384740dcSRalf Baechle
clear_dma_done1(unsigned int dmanr)322384740dcSRalf Baechle static inline void clear_dma_done1(unsigned int dmanr)
323384740dcSRalf Baechle {
324384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
325384740dcSRalf Baechle
326384740dcSRalf Baechle if (!chan)
327384740dcSRalf Baechle return;
3282f73bfbeSManuel Lauss __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
329384740dcSRalf Baechle }
330384740dcSRalf Baechle
331384740dcSRalf Baechle /*
332384740dcSRalf Baechle * This does nothing - not applicable to Au1000 DMA.
333384740dcSRalf Baechle */
set_dma_page(unsigned int dmanr,char pagenr)334384740dcSRalf Baechle static inline void set_dma_page(unsigned int dmanr, char pagenr)
335384740dcSRalf Baechle {
336384740dcSRalf Baechle }
337384740dcSRalf Baechle
338384740dcSRalf Baechle /*
339384740dcSRalf Baechle * Set Buffer 0 transfer address for specific DMA channel.
340384740dcSRalf Baechle */
set_dma_addr0(unsigned int dmanr,unsigned int a)341384740dcSRalf Baechle static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
342384740dcSRalf Baechle {
343384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
344384740dcSRalf Baechle
345384740dcSRalf Baechle if (!chan)
346384740dcSRalf Baechle return;
3472f73bfbeSManuel Lauss __raw_writel(a, chan->io + DMA_BUFFER0_START);
348384740dcSRalf Baechle }
349384740dcSRalf Baechle
350384740dcSRalf Baechle /*
351384740dcSRalf Baechle * Set Buffer 1 transfer address for specific DMA channel.
352384740dcSRalf Baechle */
set_dma_addr1(unsigned int dmanr,unsigned int a)353384740dcSRalf Baechle static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
354384740dcSRalf Baechle {
355384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
356384740dcSRalf Baechle
357384740dcSRalf Baechle if (!chan)
358384740dcSRalf Baechle return;
3592f73bfbeSManuel Lauss __raw_writel(a, chan->io + DMA_BUFFER1_START);
360384740dcSRalf Baechle }
361384740dcSRalf Baechle
362384740dcSRalf Baechle
363384740dcSRalf Baechle /*
364384740dcSRalf Baechle * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
365384740dcSRalf Baechle */
set_dma_count0(unsigned int dmanr,unsigned int count)366384740dcSRalf Baechle static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
367384740dcSRalf Baechle {
368384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
369384740dcSRalf Baechle
370384740dcSRalf Baechle if (!chan)
371384740dcSRalf Baechle return;
372384740dcSRalf Baechle count &= DMA_COUNT_MASK;
3732f73bfbeSManuel Lauss __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
374384740dcSRalf Baechle }
375384740dcSRalf Baechle
376384740dcSRalf Baechle /*
377384740dcSRalf Baechle * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
378384740dcSRalf Baechle */
set_dma_count1(unsigned int dmanr,unsigned int count)379384740dcSRalf Baechle static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
380384740dcSRalf Baechle {
381384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
382384740dcSRalf Baechle
383384740dcSRalf Baechle if (!chan)
384384740dcSRalf Baechle return;
385384740dcSRalf Baechle count &= DMA_COUNT_MASK;
3862f73bfbeSManuel Lauss __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
387384740dcSRalf Baechle }
388384740dcSRalf Baechle
389384740dcSRalf Baechle /*
390384740dcSRalf Baechle * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
391384740dcSRalf Baechle */
set_dma_count(unsigned int dmanr,unsigned int count)392384740dcSRalf Baechle static inline void set_dma_count(unsigned int dmanr, unsigned int count)
393384740dcSRalf Baechle {
394384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
395384740dcSRalf Baechle
396384740dcSRalf Baechle if (!chan)
397384740dcSRalf Baechle return;
398384740dcSRalf Baechle count &= DMA_COUNT_MASK;
3992f73bfbeSManuel Lauss __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
4002f73bfbeSManuel Lauss __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
401384740dcSRalf Baechle }
402384740dcSRalf Baechle
403384740dcSRalf Baechle /*
404384740dcSRalf Baechle * Returns which buffer has its done bit set in the mode register.
405384740dcSRalf Baechle * Returns -1 if neither or both done bits set.
406384740dcSRalf Baechle */
get_dma_buffer_done(unsigned int dmanr)407384740dcSRalf Baechle static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
408384740dcSRalf Baechle {
409384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
410384740dcSRalf Baechle
411384740dcSRalf Baechle if (!chan)
412384740dcSRalf Baechle return 0;
4132f73bfbeSManuel Lauss return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
414384740dcSRalf Baechle }
415384740dcSRalf Baechle
416384740dcSRalf Baechle
417384740dcSRalf Baechle /*
418384740dcSRalf Baechle * Returns the DMA channel's Buffer Done IRQ number.
419384740dcSRalf Baechle */
get_dma_done_irq(unsigned int dmanr)420384740dcSRalf Baechle static inline int get_dma_done_irq(unsigned int dmanr)
421384740dcSRalf Baechle {
422384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
423384740dcSRalf Baechle
424384740dcSRalf Baechle if (!chan)
425384740dcSRalf Baechle return -1;
426384740dcSRalf Baechle return chan->irq;
427384740dcSRalf Baechle }
428384740dcSRalf Baechle
429384740dcSRalf Baechle /*
430384740dcSRalf Baechle * Get DMA residue count. Returns the number of _bytes_ left to transfer.
431384740dcSRalf Baechle */
get_dma_residue(unsigned int dmanr)432384740dcSRalf Baechle static inline int get_dma_residue(unsigned int dmanr)
433384740dcSRalf Baechle {
434384740dcSRalf Baechle int curBufCntReg, count;
435384740dcSRalf Baechle struct dma_chan *chan = get_dma_chan(dmanr);
436384740dcSRalf Baechle
437384740dcSRalf Baechle if (!chan)
438384740dcSRalf Baechle return 0;
439384740dcSRalf Baechle
4402f73bfbeSManuel Lauss curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
441384740dcSRalf Baechle DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
442384740dcSRalf Baechle
4432f73bfbeSManuel Lauss count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
444384740dcSRalf Baechle
445384740dcSRalf Baechle if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
446384740dcSRalf Baechle count <<= 1;
447384740dcSRalf Baechle else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
448384740dcSRalf Baechle count <<= 2;
449384740dcSRalf Baechle
450384740dcSRalf Baechle return count;
451384740dcSRalf Baechle }
452384740dcSRalf Baechle
453384740dcSRalf Baechle #endif /* __ASM_AU1000_DMA_H */
454