1 /*
2  *  Atheros AR71XX/AR724X/AR913X SoC register definitions
3  *
4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7  *
8  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9  *
10  *  This program is free software; you can redistribute it and/or modify it
11  *  under the terms of the GNU General Public License version 2 as published
12  *  by the Free Software Foundation.
13  */
14 
15 #ifndef __ASM_MACH_AR71XX_REGS_H
16 #define __ASM_MACH_AR71XX_REGS_H
17 
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21 
22 #define AR71XX_APB_BASE		0x18000000
23 #define AR71XX_GE0_BASE		0x19000000
24 #define AR71XX_GE0_SIZE		0x10000
25 #define AR71XX_GE1_BASE		0x1a000000
26 #define AR71XX_GE1_SIZE		0x10000
27 #define AR71XX_EHCI_BASE	0x1b000000
28 #define AR71XX_EHCI_SIZE	0x1000
29 #define AR71XX_OHCI_BASE	0x1c000000
30 #define AR71XX_OHCI_SIZE	0x1000
31 #define AR71XX_SPI_BASE		0x1f000000
32 #define AR71XX_SPI_SIZE		0x01000000
33 
34 #define AR71XX_DDR_CTRL_BASE	(AR71XX_APB_BASE + 0x00000000)
35 #define AR71XX_DDR_CTRL_SIZE	0x100
36 #define AR71XX_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
37 #define AR71XX_UART_SIZE	0x100
38 #define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
39 #define AR71XX_USB_CTRL_SIZE	0x100
40 #define AR71XX_GPIO_BASE	(AR71XX_APB_BASE + 0x00040000)
41 #define AR71XX_GPIO_SIZE	0x100
42 #define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
43 #define AR71XX_PLL_SIZE		0x100
44 #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
45 #define AR71XX_RESET_SIZE	0x100
46 #define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
47 #define AR71XX_MII_SIZE		0x100
48 
49 #define AR71XX_PCI_MEM_BASE	0x10000000
50 #define AR71XX_PCI_MEM_SIZE	0x07000000
51 
52 #define AR71XX_PCI_WIN0_OFFS	0x10000000
53 #define AR71XX_PCI_WIN1_OFFS	0x11000000
54 #define AR71XX_PCI_WIN2_OFFS	0x12000000
55 #define AR71XX_PCI_WIN3_OFFS	0x13000000
56 #define AR71XX_PCI_WIN4_OFFS	0x14000000
57 #define AR71XX_PCI_WIN5_OFFS	0x15000000
58 #define AR71XX_PCI_WIN6_OFFS	0x16000000
59 #define AR71XX_PCI_WIN7_OFFS	0x07000000
60 
61 #define AR71XX_PCI_CFG_BASE	\
62 	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
63 #define AR71XX_PCI_CFG_SIZE	0x100
64 
65 #define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
66 #define AR7240_USB_CTRL_SIZE	0x100
67 #define AR7240_OHCI_BASE	0x1b000000
68 #define AR7240_OHCI_SIZE	0x1000
69 
70 #define AR724X_PCI_MEM_BASE	0x10000000
71 #define AR724X_PCI_MEM_SIZE	0x04000000
72 
73 #define AR724X_PCI_CFG_BASE	0x14000000
74 #define AR724X_PCI_CFG_SIZE	0x1000
75 #define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000c0000)
76 #define AR724X_PCI_CRP_SIZE	0x1000
77 #define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
78 #define AR724X_PCI_CTRL_SIZE	0x100
79 
80 #define AR724X_EHCI_BASE	0x1b000000
81 #define AR724X_EHCI_SIZE	0x1000
82 
83 #define AR913X_EHCI_BASE	0x1b000000
84 #define AR913X_EHCI_SIZE	0x1000
85 #define AR913X_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
86 #define AR913X_WMAC_SIZE	0x30000
87 
88 #define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
89 #define AR933X_UART_SIZE	0x14
90 #define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
91 #define AR933X_GMAC_SIZE	0x04
92 #define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
93 #define AR933X_WMAC_SIZE	0x20000
94 #define AR933X_EHCI_BASE	0x1b000000
95 #define AR933X_EHCI_SIZE	0x1000
96 
97 #define AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
98 #define AR934X_GMAC_SIZE	0x14
99 #define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
100 #define AR934X_WMAC_SIZE	0x20000
101 #define AR934X_EHCI_BASE	0x1b000000
102 #define AR934X_EHCI_SIZE	0x200
103 #define AR934X_NFC_BASE		0x1b000200
104 #define AR934X_NFC_SIZE		0xb8
105 #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
106 #define AR934X_SRIF_SIZE	0x1000
107 
108 #define QCA953X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
109 #define QCA953X_GMAC_SIZE	0x14
110 #define QCA953X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
111 #define QCA953X_WMAC_SIZE	0x20000
112 #define QCA953X_EHCI_BASE	0x1b000000
113 #define QCA953X_EHCI_SIZE	0x200
114 #define QCA953X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
115 #define QCA953X_SRIF_SIZE	0x1000
116 
117 #define QCA953X_PCI_CFG_BASE0	0x14000000
118 #define QCA953X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
119 #define QCA953X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
120 #define QCA953X_PCI_MEM_BASE0	0x10000000
121 #define QCA953X_PCI_MEM_SIZE	0x02000000
122 
123 #define QCA955X_PCI_MEM_BASE0	0x10000000
124 #define QCA955X_PCI_MEM_BASE1	0x12000000
125 #define QCA955X_PCI_MEM_SIZE	0x02000000
126 #define QCA955X_PCI_CFG_BASE0	0x14000000
127 #define QCA955X_PCI_CFG_BASE1	0x16000000
128 #define QCA955X_PCI_CFG_SIZE	0x1000
129 #define QCA955X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
130 #define QCA955X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
131 #define QCA955X_PCI_CRP_SIZE	0x1000
132 #define QCA955X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
133 #define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
134 #define QCA955X_PCI_CTRL_SIZE	0x100
135 
136 #define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
137 #define QCA955X_GMAC_SIZE	0x40
138 #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
139 #define QCA955X_WMAC_SIZE	0x20000
140 #define QCA955X_EHCI0_BASE	0x1b000000
141 #define QCA955X_EHCI1_BASE	0x1b400000
142 #define QCA955X_EHCI_SIZE	0x1000
143 #define QCA955X_NFC_BASE	0x1b800200
144 #define QCA955X_NFC_SIZE	0xb8
145 
146 #define QCA956X_PCI_MEM_BASE1	0x12000000
147 #define QCA956X_PCI_MEM_SIZE	0x02000000
148 #define QCA956X_PCI_CFG_BASE1	0x16000000
149 #define QCA956X_PCI_CFG_SIZE	0x1000
150 #define QCA956X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
151 #define QCA956X_PCI_CRP_SIZE	0x1000
152 #define QCA956X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
153 #define QCA956X_PCI_CTRL_SIZE	0x100
154 
155 #define QCA956X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
156 #define QCA956X_WMAC_SIZE	0x20000
157 #define QCA956X_EHCI0_BASE	0x1b000000
158 #define QCA956X_EHCI1_BASE	0x1b400000
159 #define QCA956X_EHCI_SIZE	0x200
160 #define QCA956X_GMAC_SGMII_BASE	(AR71XX_APB_BASE + 0x00070000)
161 #define QCA956X_GMAC_SGMII_SIZE	0x64
162 #define QCA956X_PLL_BASE	(AR71XX_APB_BASE + 0x00050000)
163 #define QCA956X_PLL_SIZE	0x50
164 #define QCA956X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
165 #define QCA956X_GMAC_SIZE	0x64
166 
167 /*
168  * Hidden Registers
169  */
170 #define QCA956X_MAC_CFG_BASE		0xb9000000
171 #define QCA956X_MAC_CFG_SIZE		0x64
172 
173 #define QCA956X_MAC_CFG1_REG		0x00
174 #define QCA956X_MAC_CFG1_SOFT_RST	BIT(31)
175 #define QCA956X_MAC_CFG1_RX_RST		BIT(19)
176 #define QCA956X_MAC_CFG1_TX_RST		BIT(18)
177 #define QCA956X_MAC_CFG1_LOOPBACK	BIT(8)
178 #define QCA956X_MAC_CFG1_RX_EN		BIT(2)
179 #define QCA956X_MAC_CFG1_TX_EN		BIT(0)
180 
181 #define QCA956X_MAC_CFG2_REG		0x04
182 #define QCA956X_MAC_CFG2_IF_1000	BIT(9)
183 #define QCA956X_MAC_CFG2_IF_10_100	BIT(8)
184 #define QCA956X_MAC_CFG2_HUGE_FRAME_EN	BIT(5)
185 #define QCA956X_MAC_CFG2_LEN_CHECK	BIT(4)
186 #define QCA956X_MAC_CFG2_PAD_CRC_EN	BIT(2)
187 #define QCA956X_MAC_CFG2_FDX		BIT(0)
188 
189 #define QCA956X_MAC_MII_MGMT_CFG_REG	0x20
190 #define QCA956X_MGMT_CFG_CLK_DIV_20	0x07
191 
192 #define QCA956X_MAC_FIFO_CFG0_REG	0x48
193 #define QCA956X_MAC_FIFO_CFG1_REG	0x4c
194 #define QCA956X_MAC_FIFO_CFG2_REG	0x50
195 #define QCA956X_MAC_FIFO_CFG3_REG	0x54
196 #define QCA956X_MAC_FIFO_CFG4_REG	0x58
197 #define QCA956X_MAC_FIFO_CFG5_REG	0x5c
198 
199 #define QCA956X_DAM_RESET_OFFSET	0xb90001bc
200 #define QCA956X_DAM_RESET_SIZE		0x4
201 #define QCA956X_INLINE_CHKSUM_ENG	BIT(27)
202 
203 /*
204  * DDR_CTRL block
205  */
206 #define AR71XX_DDR_REG_PCI_WIN0		0x7c
207 #define AR71XX_DDR_REG_PCI_WIN1		0x80
208 #define AR71XX_DDR_REG_PCI_WIN2		0x84
209 #define AR71XX_DDR_REG_PCI_WIN3		0x88
210 #define AR71XX_DDR_REG_PCI_WIN4		0x8c
211 #define AR71XX_DDR_REG_PCI_WIN5		0x90
212 #define AR71XX_DDR_REG_PCI_WIN6		0x94
213 #define AR71XX_DDR_REG_PCI_WIN7		0x98
214 #define AR71XX_DDR_REG_FLUSH_GE0	0x9c
215 #define AR71XX_DDR_REG_FLUSH_GE1	0xa0
216 #define AR71XX_DDR_REG_FLUSH_USB	0xa4
217 #define AR71XX_DDR_REG_FLUSH_PCI	0xa8
218 
219 #define AR724X_DDR_REG_FLUSH_GE0	0x7c
220 #define AR724X_DDR_REG_FLUSH_GE1	0x80
221 #define AR724X_DDR_REG_FLUSH_USB	0x84
222 #define AR724X_DDR_REG_FLUSH_PCIE	0x88
223 
224 #define AR913X_DDR_REG_FLUSH_GE0	0x7c
225 #define AR913X_DDR_REG_FLUSH_GE1	0x80
226 #define AR913X_DDR_REG_FLUSH_USB	0x84
227 #define AR913X_DDR_REG_FLUSH_WMAC	0x88
228 
229 #define AR933X_DDR_REG_FLUSH_GE0	0x7c
230 #define AR933X_DDR_REG_FLUSH_GE1	0x80
231 #define AR933X_DDR_REG_FLUSH_USB	0x84
232 #define AR933X_DDR_REG_FLUSH_WMAC	0x88
233 
234 #define AR934X_DDR_REG_FLUSH_GE0	0x9c
235 #define AR934X_DDR_REG_FLUSH_GE1	0xa0
236 #define AR934X_DDR_REG_FLUSH_USB	0xa4
237 #define AR934X_DDR_REG_FLUSH_PCIE	0xa8
238 #define AR934X_DDR_REG_FLUSH_WMAC	0xac
239 
240 #define QCA953X_DDR_REG_FLUSH_GE0	0x9c
241 #define QCA953X_DDR_REG_FLUSH_GE1	0xa0
242 #define QCA953X_DDR_REG_FLUSH_USB	0xa4
243 #define QCA953X_DDR_REG_FLUSH_PCIE	0xa8
244 #define QCA953X_DDR_REG_FLUSH_WMAC	0xac
245 
246 /*
247  * PLL block
248  */
249 #define AR71XX_PLL_REG_CPU_CONFIG	0x00
250 #define AR71XX_PLL_REG_SEC_CONFIG	0x04
251 #define AR71XX_PLL_REG_ETH0_INT_CLOCK	0x10
252 #define AR71XX_PLL_REG_ETH1_INT_CLOCK	0x14
253 
254 #define AR71XX_PLL_FB_SHIFT		3
255 #define AR71XX_PLL_FB_MASK		0x1f
256 #define AR71XX_CPU_DIV_SHIFT		16
257 #define AR71XX_CPU_DIV_MASK		0x3
258 #define AR71XX_DDR_DIV_SHIFT		18
259 #define AR71XX_DDR_DIV_MASK		0x3
260 #define AR71XX_AHB_DIV_SHIFT		20
261 #define AR71XX_AHB_DIV_MASK		0x7
262 
263 #define AR71XX_ETH0_PLL_SHIFT		17
264 #define AR71XX_ETH1_PLL_SHIFT		19
265 
266 #define AR724X_PLL_REG_CPU_CONFIG	0x00
267 #define AR724X_PLL_REG_PCIE_CONFIG	0x10
268 
269 #define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS	BIT(16)
270 #define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET	BIT(25)
271 
272 #define AR724X_PLL_FB_SHIFT		0
273 #define AR724X_PLL_FB_MASK		0x3ff
274 #define AR724X_PLL_REF_DIV_SHIFT	10
275 #define AR724X_PLL_REF_DIV_MASK		0xf
276 #define AR724X_AHB_DIV_SHIFT		19
277 #define AR724X_AHB_DIV_MASK		0x1
278 #define AR724X_DDR_DIV_SHIFT		22
279 #define AR724X_DDR_DIV_MASK		0x3
280 
281 #define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c
282 
283 #define AR913X_PLL_REG_CPU_CONFIG	0x00
284 #define AR913X_PLL_REG_ETH_CONFIG	0x04
285 #define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
286 #define AR913X_PLL_REG_ETH1_INT_CLOCK	0x18
287 
288 #define AR913X_PLL_FB_SHIFT		0
289 #define AR913X_PLL_FB_MASK		0x3ff
290 #define AR913X_DDR_DIV_SHIFT		22
291 #define AR913X_DDR_DIV_MASK		0x3
292 #define AR913X_AHB_DIV_SHIFT		19
293 #define AR913X_AHB_DIV_MASK		0x1
294 
295 #define AR913X_ETH0_PLL_SHIFT		20
296 #define AR913X_ETH1_PLL_SHIFT		22
297 
298 #define AR933X_PLL_CPU_CONFIG_REG	0x00
299 #define AR933X_PLL_CLOCK_CTRL_REG	0x08
300 
301 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
302 #define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
303 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
304 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
305 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
306 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
307 
308 #define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
309 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
310 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
311 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
312 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
313 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
314 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
315 
316 #define AR934X_PLL_CPU_CONFIG_REG		0x00
317 #define AR934X_PLL_DDR_CONFIG_REG		0x04
318 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
319 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
320 #define AR934X_PLL_ETH_XMII_CONTROL_REG		0x2c
321 
322 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
323 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
324 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
325 #define AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
326 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
327 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
328 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
329 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
330 
331 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
332 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
333 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
334 #define AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
335 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
336 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
337 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
338 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
339 
340 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	BIT(2)
341 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	BIT(3)
342 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	BIT(4)
343 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
344 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
345 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
346 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
347 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
348 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
349 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
350 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
351 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
352 
353 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
354 
355 #define QCA953X_PLL_CPU_CONFIG_REG		0x00
356 #define QCA953X_PLL_DDR_CONFIG_REG		0x04
357 #define QCA953X_PLL_CLK_CTRL_REG		0x08
358 #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
359 #define QCA953X_PLL_ETH_XMII_CONTROL_REG	0x2c
360 #define QCA953X_PLL_ETH_SGMII_CONTROL_REG	0x48
361 
362 #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
363 #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
364 #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT	6
365 #define QCA953X_PLL_CPU_CONFIG_NINT_MASK	0x3f
366 #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
367 #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
368 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
369 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
370 
371 #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
372 #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
373 #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT	10
374 #define QCA953X_PLL_DDR_CONFIG_NINT_MASK	0x3f
375 #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
376 #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
377 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
378 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
379 
380 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
381 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
382 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
383 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
384 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
385 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
386 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
387 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
388 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
389 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
390 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
391 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
392 
393 #define QCA955X_PLL_CPU_CONFIG_REG		0x00
394 #define QCA955X_PLL_DDR_CONFIG_REG		0x04
395 #define QCA955X_PLL_CLK_CTRL_REG		0x08
396 #define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
397 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
398 #define QCA955X_PLL_ETH_SGMII_SERDES_REG	0x4c
399 
400 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
401 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
402 #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT	6
403 #define QCA955X_PLL_CPU_CONFIG_NINT_MASK	0x3f
404 #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
405 #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
406 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
407 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
408 
409 #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
410 #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
411 #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT	10
412 #define QCA955X_PLL_DDR_CONFIG_NINT_MASK	0x3f
413 #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
414 #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
415 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
416 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
417 
418 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
419 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
420 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
421 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
422 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
423 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
424 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
425 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
426 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
427 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
428 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
429 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
430 
431 #define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT	BIT(2)
432 #define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK		BIT(1)
433 #define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL		BIT(0)
434 
435 #define QCA956X_PLL_CPU_CONFIG_REG			0x00
436 #define QCA956X_PLL_CPU_CONFIG1_REG			0x04
437 #define QCA956X_PLL_DDR_CONFIG_REG			0x08
438 #define QCA956X_PLL_DDR_CONFIG1_REG			0x0c
439 #define QCA956X_PLL_CLK_CTRL_REG			0x10
440 #define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG		0x28
441 #define QCA956X_PLL_ETH_XMII_CONTROL_REG		0x30
442 #define QCA956X_PLL_ETH_SGMII_SERDES_REG		0x4c
443 
444 #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
445 #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
446 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
447 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
448 
449 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
450 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
451 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
452 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x1fff
453 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
454 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
455 
456 #define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
457 #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
458 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
459 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
460 
461 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
462 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
463 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
464 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x1fff
465 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
466 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff
467 
468 #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
469 #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
470 #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
471 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
472 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
473 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
474 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
475 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
476 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
477 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL	BIT(20)
478 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
479 #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
480 
481 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB		BIT(5)
482 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1		BIT(6)
483 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL		BIT(7)
484 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
485 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK	 0xf
486 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP		BIT(12)
487 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2		BIT(13)
488 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1		BIT(14)
489 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2		BIT(15)
490 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE	BIT(16)
491 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE		BIT(17)
492 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL		BIT(18)
493 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL		BIT(19)
494 
495 #define QCA956X_PLL_ETH_XMII_TX_INVERT			BIT(1)
496 #define QCA956X_PLL_ETH_XMII_GIGE			BIT(25)
497 #define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT		28
498 #define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK		0x3
499 #define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT		26
500 #define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK		3
501 
502 #define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT		BIT(2)
503 #define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK			BIT(1)
504 #define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL			BIT(0)
505 
506 /*
507  * USB_CONFIG block
508  */
509 #define AR71XX_USB_CTRL_REG_FLADJ	0x00
510 #define AR71XX_USB_CTRL_REG_CONFIG	0x04
511 
512 /*
513  * RESET block
514  */
515 #define AR71XX_RESET_REG_TIMER			0x00
516 #define AR71XX_RESET_REG_TIMER_RELOAD		0x04
517 #define AR71XX_RESET_REG_WDOG_CTRL		0x08
518 #define AR71XX_RESET_REG_WDOG			0x0c
519 #define AR71XX_RESET_REG_MISC_INT_STATUS	0x10
520 #define AR71XX_RESET_REG_MISC_INT_ENABLE	0x14
521 #define AR71XX_RESET_REG_PCI_INT_STATUS		0x18
522 #define AR71XX_RESET_REG_PCI_INT_ENABLE		0x1c
523 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS	0x20
524 #define AR71XX_RESET_REG_RESET_MODULE		0x24
525 #define AR71XX_RESET_REG_PERFC_CTRL		0x2c
526 #define AR71XX_RESET_REG_PERFC0			0x30
527 #define AR71XX_RESET_REG_PERFC1			0x34
528 #define AR71XX_RESET_REG_REV_ID			0x90
529 
530 #define AR913X_RESET_REG_GLOBAL_INT_STATUS	0x18
531 #define AR913X_RESET_REG_RESET_MODULE		0x1c
532 #define AR913X_RESET_REG_PERF_CTRL		0x20
533 #define AR913X_RESET_REG_PERFC0			0x24
534 #define AR913X_RESET_REG_PERFC1			0x28
535 
536 #define AR724X_RESET_REG_RESET_MODULE		0x1c
537 
538 #define AR933X_RESET_REG_RESET_MODULE		0x1c
539 #define AR933X_RESET_REG_BOOTSTRAP		0xac
540 
541 #define AR934X_RESET_REG_RESET_MODULE		0x1c
542 #define AR934X_RESET_REG_BOOTSTRAP		0xb0
543 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
544 
545 #define QCA953X_RESET_REG_RESET_MODULE		0x1c
546 #define QCA953X_RESET_REG_BOOTSTRAP		0xb0
547 #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
548 
549 #define QCA955X_RESET_REG_RESET_MODULE		0x1c
550 #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
551 #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
552 
553 #define QCA956X_RESET_REG_RESET_MODULE		0x1c
554 #define QCA956X_RESET_REG_BOOTSTRAP		0xb0
555 #define QCA956X_RESET_REG_EXT_INT_STATUS	0xac
556 
557 #define MISC_INT_MIPS_SI_TIMERINT_MASK	BIT(28)
558 #define MISC_INT_ETHSW			BIT(12)
559 #define MISC_INT_TIMER4			BIT(10)
560 #define MISC_INT_TIMER3			BIT(9)
561 #define MISC_INT_TIMER2			BIT(8)
562 #define MISC_INT_DMA			BIT(7)
563 #define MISC_INT_OHCI			BIT(6)
564 #define MISC_INT_PERFC			BIT(5)
565 #define MISC_INT_WDOG			BIT(4)
566 #define MISC_INT_UART			BIT(3)
567 #define MISC_INT_GPIO			BIT(2)
568 #define MISC_INT_ERROR			BIT(1)
569 #define MISC_INT_TIMER			BIT(0)
570 
571 #define AR71XX_RESET_EXTERNAL		BIT(28)
572 #define AR71XX_RESET_FULL_CHIP		BIT(24)
573 #define AR71XX_RESET_CPU_NMI		BIT(21)
574 #define AR71XX_RESET_CPU_COLD		BIT(20)
575 #define AR71XX_RESET_DMA		BIT(19)
576 #define AR71XX_RESET_SLIC		BIT(18)
577 #define AR71XX_RESET_STEREO		BIT(17)
578 #define AR71XX_RESET_DDR		BIT(16)
579 #define AR71XX_RESET_GE1_MAC		BIT(13)
580 #define AR71XX_RESET_GE1_PHY		BIT(12)
581 #define AR71XX_RESET_USBSUS_OVERRIDE	BIT(10)
582 #define AR71XX_RESET_GE0_MAC		BIT(9)
583 #define AR71XX_RESET_GE0_PHY		BIT(8)
584 #define AR71XX_RESET_USB_OHCI_DLL	BIT(6)
585 #define AR71XX_RESET_USB_HOST		BIT(5)
586 #define AR71XX_RESET_USB_PHY		BIT(4)
587 #define AR71XX_RESET_PCI_BUS		BIT(1)
588 #define AR71XX_RESET_PCI_CORE		BIT(0)
589 
590 #define AR7240_RESET_USB_HOST		BIT(5)
591 #define AR7240_RESET_OHCI_DLL		BIT(3)
592 
593 #define AR724X_RESET_GE1_MDIO		BIT(23)
594 #define AR724X_RESET_GE0_MDIO		BIT(22)
595 #define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
596 #define AR724X_RESET_PCIE_PHY		BIT(7)
597 #define AR724X_RESET_PCIE		BIT(6)
598 #define AR724X_RESET_USB_HOST		BIT(5)
599 #define AR724X_RESET_USB_PHY		BIT(4)
600 #define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)
601 
602 #define AR913X_RESET_AMBA2WMAC		BIT(22)
603 #define AR913X_RESET_USBSUS_OVERRIDE	BIT(10)
604 #define AR913X_RESET_USB_HOST		BIT(5)
605 #define AR913X_RESET_USB_PHY		BIT(4)
606 
607 #define AR933X_RESET_GE1_MDIO		BIT(23)
608 #define AR933X_RESET_GE0_MDIO		BIT(22)
609 #define AR933X_RESET_GE1_MAC		BIT(13)
610 #define AR933X_RESET_WMAC		BIT(11)
611 #define AR933X_RESET_GE0_MAC		BIT(9)
612 #define AR933X_RESET_USB_HOST		BIT(5)
613 #define AR933X_RESET_USB_PHY		BIT(4)
614 #define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)
615 
616 #define AR934X_RESET_HOST		BIT(31)
617 #define AR934X_RESET_SLIC		BIT(30)
618 #define AR934X_RESET_HDMA		BIT(29)
619 #define AR934X_RESET_EXTERNAL		BIT(28)
620 #define AR934X_RESET_RTC		BIT(27)
621 #define AR934X_RESET_PCIE_EP_INT	BIT(26)
622 #define AR934X_RESET_CHKSUM_ACC		BIT(25)
623 #define AR934X_RESET_FULL_CHIP		BIT(24)
624 #define AR934X_RESET_GE1_MDIO		BIT(23)
625 #define AR934X_RESET_GE0_MDIO		BIT(22)
626 #define AR934X_RESET_CPU_NMI		BIT(21)
627 #define AR934X_RESET_CPU_COLD		BIT(20)
628 #define AR934X_RESET_HOST_RESET_INT	BIT(19)
629 #define AR934X_RESET_PCIE_EP		BIT(18)
630 #define AR934X_RESET_UART1		BIT(17)
631 #define AR934X_RESET_DDR		BIT(16)
632 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
633 #define AR934X_RESET_NANDF		BIT(14)
634 #define AR934X_RESET_GE1_MAC		BIT(13)
635 #define AR934X_RESET_ETH_SWITCH_ANALOG	BIT(12)
636 #define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
637 #define AR934X_RESET_HOST_DMA_INT	BIT(10)
638 #define AR934X_RESET_GE0_MAC		BIT(9)
639 #define AR934X_RESET_ETH_SWITCH		BIT(8)
640 #define AR934X_RESET_PCIE_PHY		BIT(7)
641 #define AR934X_RESET_PCIE		BIT(6)
642 #define AR934X_RESET_USB_HOST		BIT(5)
643 #define AR934X_RESET_USB_PHY		BIT(4)
644 #define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
645 #define AR934X_RESET_LUT		BIT(2)
646 #define AR934X_RESET_MBOX		BIT(1)
647 #define AR934X_RESET_I2S		BIT(0)
648 
649 #define QCA953X_RESET_USB_EXT_PWR	BIT(29)
650 #define QCA953X_RESET_EXTERNAL		BIT(28)
651 #define QCA953X_RESET_RTC		BIT(27)
652 #define QCA953X_RESET_FULL_CHIP		BIT(24)
653 #define QCA953X_RESET_GE1_MDIO		BIT(23)
654 #define QCA953X_RESET_GE0_MDIO		BIT(22)
655 #define QCA953X_RESET_CPU_NMI		BIT(21)
656 #define QCA953X_RESET_CPU_COLD		BIT(20)
657 #define QCA953X_RESET_DDR		BIT(16)
658 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
659 #define QCA953X_RESET_GE1_MAC		BIT(13)
660 #define QCA953X_RESET_ETH_SWITCH_ANALOG	BIT(12)
661 #define QCA953X_RESET_USB_PHY_ANALOG	BIT(11)
662 #define QCA953X_RESET_GE0_MAC		BIT(9)
663 #define QCA953X_RESET_ETH_SWITCH	BIT(8)
664 #define QCA953X_RESET_PCIE_PHY		BIT(7)
665 #define QCA953X_RESET_PCIE		BIT(6)
666 #define QCA953X_RESET_USB_HOST		BIT(5)
667 #define QCA953X_RESET_USB_PHY		BIT(4)
668 #define QCA953X_RESET_USBSUS_OVERRIDE	BIT(3)
669 
670 #define QCA955X_RESET_HOST		BIT(31)
671 #define QCA955X_RESET_SLIC		BIT(30)
672 #define QCA955X_RESET_HDMA		BIT(29)
673 #define QCA955X_RESET_EXTERNAL		BIT(28)
674 #define QCA955X_RESET_RTC		BIT(27)
675 #define QCA955X_RESET_PCIE_EP_INT	BIT(26)
676 #define QCA955X_RESET_CHKSUM_ACC	BIT(25)
677 #define QCA955X_RESET_FULL_CHIP		BIT(24)
678 #define QCA955X_RESET_GE1_MDIO		BIT(23)
679 #define QCA955X_RESET_GE0_MDIO		BIT(22)
680 #define QCA955X_RESET_CPU_NMI		BIT(21)
681 #define QCA955X_RESET_CPU_COLD		BIT(20)
682 #define QCA955X_RESET_HOST_RESET_INT	BIT(19)
683 #define QCA955X_RESET_PCIE_EP		BIT(18)
684 #define QCA955X_RESET_UART1		BIT(17)
685 #define QCA955X_RESET_DDR		BIT(16)
686 #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
687 #define QCA955X_RESET_NANDF		BIT(14)
688 #define QCA955X_RESET_GE1_MAC		BIT(13)
689 #define QCA955X_RESET_SGMII_ANALOG	BIT(12)
690 #define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
691 #define QCA955X_RESET_HOST_DMA_INT	BIT(10)
692 #define QCA955X_RESET_GE0_MAC		BIT(9)
693 #define QCA955X_RESET_SGMII		BIT(8)
694 #define QCA955X_RESET_PCIE_PHY		BIT(7)
695 #define QCA955X_RESET_PCIE		BIT(6)
696 #define QCA955X_RESET_USB_HOST		BIT(5)
697 #define QCA955X_RESET_USB_PHY		BIT(4)
698 #define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
699 #define QCA955X_RESET_LUT		BIT(2)
700 #define QCA955X_RESET_MBOX		BIT(1)
701 #define QCA955X_RESET_I2S		BIT(0)
702 
703 #define QCA956X_RESET_EXTERNAL		BIT(28)
704 #define QCA956X_RESET_FULL_CHIP		BIT(24)
705 #define QCA956X_RESET_GE1_MDIO		BIT(23)
706 #define QCA956X_RESET_GE0_MDIO		BIT(22)
707 #define QCA956X_RESET_CPU_NMI		BIT(21)
708 #define QCA956X_RESET_CPU_COLD		BIT(20)
709 #define QCA956X_RESET_DMA		BIT(19)
710 #define QCA956X_RESET_DDR		BIT(16)
711 #define QCA956X_RESET_GE1_MAC		BIT(13)
712 #define QCA956X_RESET_SGMII_ANALOG	BIT(12)
713 #define QCA956X_RESET_USB_PHY_ANALOG	BIT(11)
714 #define QCA956X_RESET_GE0_MAC		BIT(9)
715 #define QCA956X_RESET_SGMII		BIT(8)
716 #define QCA956X_RESET_USB_HOST		BIT(5)
717 #define QCA956X_RESET_USB_PHY		BIT(4)
718 #define QCA956X_RESET_USBSUS_OVERRIDE	BIT(3)
719 #define QCA956X_RESET_SWITCH_ANALOG	BIT(2)
720 #define QCA956X_RESET_SWITCH		BIT(0)
721 
722 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
723 #define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
724 #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
725 
726 #define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
727 #define AR934X_BOOTSTRAP_SW_OPTION7	BIT(22)
728 #define AR934X_BOOTSTRAP_SW_OPTION6	BIT(21)
729 #define AR934X_BOOTSTRAP_SW_OPTION5	BIT(20)
730 #define AR934X_BOOTSTRAP_SW_OPTION4	BIT(19)
731 #define AR934X_BOOTSTRAP_SW_OPTION3	BIT(18)
732 #define AR934X_BOOTSTRAP_SW_OPTION2	BIT(17)
733 #define AR934X_BOOTSTRAP_SW_OPTION1	BIT(16)
734 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
735 #define AR934X_BOOTSTRAP_PCIE_RC	BIT(6)
736 #define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
737 #define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
738 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
739 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
740 #define AR934X_BOOTSTRAP_DDR1		BIT(0)
741 
742 #define QCA953X_BOOTSTRAP_SW_OPTION2	BIT(12)
743 #define QCA953X_BOOTSTRAP_SW_OPTION1	BIT(11)
744 #define QCA953X_BOOTSTRAP_EJTAG_MODE	BIT(5)
745 #define QCA953X_BOOTSTRAP_REF_CLK_40	BIT(4)
746 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
747 #define QCA953X_BOOTSTRAP_DDR1		BIT(0)
748 
749 #define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
750 
751 #define QCA956X_BOOTSTRAP_REF_CLK_40	BIT(2)
752 
753 #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
754 #define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
755 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
756 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
757 #define AR934X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
758 #define AR934X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
759 #define AR934X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
760 #define AR934X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
761 #define AR934X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
762 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \
763 	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
764 	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
765 
766 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \
767 	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
768 	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
769 	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
770 
771 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
772 #define QCA953X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
773 #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
774 #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
775 #define QCA953X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
776 #define QCA953X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
777 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
778 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
779 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
780 #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
781 	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
782 	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
783 
784 #define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
785 	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
786 	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
787 	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
788 
789 #define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
790 #define QCA955X_EXT_INT_WMAC_TX			BIT(1)
791 #define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
792 #define QCA955X_EXT_INT_WMAC_RXHP		BIT(3)
793 #define QCA955X_EXT_INT_PCIE_RC1		BIT(4)
794 #define QCA955X_EXT_INT_PCIE_RC1_INT0		BIT(5)
795 #define QCA955X_EXT_INT_PCIE_RC1_INT1		BIT(6)
796 #define QCA955X_EXT_INT_PCIE_RC1_INT2		BIT(7)
797 #define QCA955X_EXT_INT_PCIE_RC1_INT3		BIT(8)
798 #define QCA955X_EXT_INT_PCIE_RC2		BIT(12)
799 #define QCA955X_EXT_INT_PCIE_RC2_INT0		BIT(13)
800 #define QCA955X_EXT_INT_PCIE_RC2_INT1		BIT(14)
801 #define QCA955X_EXT_INT_PCIE_RC2_INT2		BIT(15)
802 #define QCA955X_EXT_INT_PCIE_RC2_INT3		BIT(16)
803 #define QCA955X_EXT_INT_USB1			BIT(24)
804 #define QCA955X_EXT_INT_USB2			BIT(28)
805 
806 #define QCA955X_EXT_INT_WMAC_ALL \
807 	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
808 	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
809 
810 #define QCA955X_EXT_INT_PCIE_RC1_ALL \
811 	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
812 	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
813 	 QCA955X_EXT_INT_PCIE_RC1_INT3)
814 
815 #define QCA955X_EXT_INT_PCIE_RC2_ALL \
816 	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
817 	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
818 	 QCA955X_EXT_INT_PCIE_RC2_INT3)
819 
820 #define QCA956X_EXT_INT_WMAC_MISC		BIT(0)
821 #define QCA956X_EXT_INT_WMAC_TX			BIT(1)
822 #define QCA956X_EXT_INT_WMAC_RXLP		BIT(2)
823 #define QCA956X_EXT_INT_WMAC_RXHP		BIT(3)
824 #define QCA956X_EXT_INT_PCIE_RC1		BIT(4)
825 #define QCA956X_EXT_INT_PCIE_RC1_INT0		BIT(5)
826 #define QCA956X_EXT_INT_PCIE_RC1_INT1		BIT(6)
827 #define QCA956X_EXT_INT_PCIE_RC1_INT2		BIT(7)
828 #define QCA956X_EXT_INT_PCIE_RC1_INT3		BIT(8)
829 #define QCA956X_EXT_INT_PCIE_RC2		BIT(12)
830 #define QCA956X_EXT_INT_PCIE_RC2_INT0		BIT(13)
831 #define QCA956X_EXT_INT_PCIE_RC2_INT1		BIT(14)
832 #define QCA956X_EXT_INT_PCIE_RC2_INT2		BIT(15)
833 #define QCA956X_EXT_INT_PCIE_RC2_INT3		BIT(16)
834 #define QCA956X_EXT_INT_USB1			BIT(24)
835 #define QCA956X_EXT_INT_USB2			BIT(28)
836 
837 #define QCA956X_EXT_INT_WMAC_ALL \
838 	(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
839 	 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
840 
841 #define QCA956X_EXT_INT_PCIE_RC1_ALL \
842 	(QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
843 	 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
844 	 QCA956X_EXT_INT_PCIE_RC1_INT3)
845 
846 #define QCA956X_EXT_INT_PCIE_RC2_ALL \
847 	(QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
848 	 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
849 	 QCA956X_EXT_INT_PCIE_RC2_INT3)
850 
851 #define REV_ID_MAJOR_MASK		0xfff0
852 #define REV_ID_MAJOR_AR71XX		0x00a0
853 #define REV_ID_MAJOR_AR913X		0x00b0
854 #define REV_ID_MAJOR_AR7240		0x00c0
855 #define REV_ID_MAJOR_AR7241		0x0100
856 #define REV_ID_MAJOR_AR7242		0x1100
857 #define REV_ID_MAJOR_AR9330		0x0110
858 #define REV_ID_MAJOR_AR9331		0x1110
859 #define REV_ID_MAJOR_AR9341		0x0120
860 #define REV_ID_MAJOR_AR9342		0x1120
861 #define REV_ID_MAJOR_AR9344		0x2120
862 #define REV_ID_MAJOR_QCA9533		0x0140
863 #define REV_ID_MAJOR_QCA9533_V2		0x0160
864 #define REV_ID_MAJOR_QCA9556		0x0130
865 #define REV_ID_MAJOR_QCA9558		0x1130
866 #define REV_ID_MAJOR_TP9343		0x0150
867 #define REV_ID_MAJOR_QCA956X		0x1150
868 
869 #define AR71XX_REV_ID_MINOR_MASK	0x3
870 #define AR71XX_REV_ID_MINOR_AR7130	0x0
871 #define AR71XX_REV_ID_MINOR_AR7141	0x1
872 #define AR71XX_REV_ID_MINOR_AR7161	0x2
873 #define AR71XX_REV_ID_REVISION_MASK	0x3
874 #define AR71XX_REV_ID_REVISION_SHIFT	2
875 
876 #define AR913X_REV_ID_MINOR_MASK	0x3
877 #define AR913X_REV_ID_MINOR_AR9130	0x0
878 #define AR913X_REV_ID_MINOR_AR9132	0x1
879 #define AR913X_REV_ID_REVISION_MASK	0x3
880 #define AR913X_REV_ID_REVISION_SHIFT	2
881 
882 #define AR933X_REV_ID_REVISION_MASK	0x3
883 
884 #define AR724X_REV_ID_REVISION_MASK	0x3
885 
886 #define AR934X_REV_ID_REVISION_MASK	0xf
887 
888 #define QCA953X_REV_ID_REVISION_MASK	0xf
889 
890 #define QCA955X_REV_ID_REVISION_MASK	0xf
891 
892 #define QCA956X_REV_ID_REVISION_MASK	0xf
893 
894 /*
895  * SPI block
896  */
897 #define AR71XX_SPI_REG_FS	0x00	/* Function Select */
898 #define AR71XX_SPI_REG_CTRL	0x04	/* SPI Control */
899 #define AR71XX_SPI_REG_IOC	0x08	/* SPI I/O Control */
900 #define AR71XX_SPI_REG_RDS	0x0c	/* Read Data Shift */
901 
902 #define AR71XX_SPI_FS_GPIO	BIT(0)	/* Enable GPIO mode */
903 
904 #define AR71XX_SPI_CTRL_RD	BIT(6)	/* Remap Disable */
905 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f
906 
907 #define AR71XX_SPI_IOC_DO	BIT(0)	/* Data Out pin */
908 #define AR71XX_SPI_IOC_CLK	BIT(8)	/* CLK pin */
909 #define AR71XX_SPI_IOC_CS(n)	BIT(16 + (n))
910 #define AR71XX_SPI_IOC_CS0	AR71XX_SPI_IOC_CS(0)
911 #define AR71XX_SPI_IOC_CS1	AR71XX_SPI_IOC_CS(1)
912 #define AR71XX_SPI_IOC_CS2	AR71XX_SPI_IOC_CS(2)
913 #define AR71XX_SPI_IOC_CS_ALL	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
914 				 AR71XX_SPI_IOC_CS2)
915 
916 /*
917  * GPIO block
918  */
919 #define AR71XX_GPIO_REG_OE		0x00
920 #define AR71XX_GPIO_REG_IN		0x04
921 #define AR71XX_GPIO_REG_OUT		0x08
922 #define AR71XX_GPIO_REG_SET		0x0c
923 #define AR71XX_GPIO_REG_CLEAR		0x10
924 #define AR71XX_GPIO_REG_INT_MODE	0x14
925 #define AR71XX_GPIO_REG_INT_TYPE	0x18
926 #define AR71XX_GPIO_REG_INT_POLARITY	0x1c
927 #define AR71XX_GPIO_REG_INT_PENDING	0x20
928 #define AR71XX_GPIO_REG_INT_ENABLE	0x24
929 #define AR71XX_GPIO_REG_FUNC		0x28
930 
931 #define AR934X_GPIO_REG_OUT_FUNC0	0x2c
932 #define AR934X_GPIO_REG_OUT_FUNC1	0x30
933 #define AR934X_GPIO_REG_OUT_FUNC2	0x34
934 #define AR934X_GPIO_REG_OUT_FUNC3	0x38
935 #define AR934X_GPIO_REG_OUT_FUNC4	0x3c
936 #define AR934X_GPIO_REG_OUT_FUNC5	0x40
937 #define AR934X_GPIO_REG_FUNC		0x6c
938 
939 #define QCA953X_GPIO_REG_OUT_FUNC0	0x2c
940 #define QCA953X_GPIO_REG_OUT_FUNC1	0x30
941 #define QCA953X_GPIO_REG_OUT_FUNC2	0x34
942 #define QCA953X_GPIO_REG_OUT_FUNC3	0x38
943 #define QCA953X_GPIO_REG_OUT_FUNC4	0x3c
944 #define QCA953X_GPIO_REG_IN_ENABLE0	0x44
945 #define QCA953X_GPIO_REG_FUNC		0x6c
946 
947 #define QCA953X_GPIO_OUT_MUX_SPI_CS1		10
948 #define QCA953X_GPIO_OUT_MUX_SPI_CS2		11
949 #define QCA953X_GPIO_OUT_MUX_SPI_CS0		9
950 #define QCA953X_GPIO_OUT_MUX_SPI_CLK		8
951 #define QCA953X_GPIO_OUT_MUX_SPI_MOSI		12
952 #define QCA953X_GPIO_OUT_MUX_LED_LINK1		41
953 #define QCA953X_GPIO_OUT_MUX_LED_LINK2		42
954 #define QCA953X_GPIO_OUT_MUX_LED_LINK3		43
955 #define QCA953X_GPIO_OUT_MUX_LED_LINK4		44
956 #define QCA953X_GPIO_OUT_MUX_LED_LINK5		45
957 
958 #define QCA955X_GPIO_REG_OUT_FUNC0	0x2c
959 #define QCA955X_GPIO_REG_OUT_FUNC1	0x30
960 #define QCA955X_GPIO_REG_OUT_FUNC2	0x34
961 #define QCA955X_GPIO_REG_OUT_FUNC3	0x38
962 #define QCA955X_GPIO_REG_OUT_FUNC4	0x3c
963 #define QCA955X_GPIO_REG_OUT_FUNC5	0x40
964 #define QCA955X_GPIO_REG_FUNC		0x6c
965 
966 #define QCA956X_GPIO_REG_OUT_FUNC0	0x2c
967 #define QCA956X_GPIO_REG_OUT_FUNC1	0x30
968 #define QCA956X_GPIO_REG_OUT_FUNC2	0x34
969 #define QCA956X_GPIO_REG_OUT_FUNC3	0x38
970 #define QCA956X_GPIO_REG_OUT_FUNC4	0x3c
971 #define QCA956X_GPIO_REG_OUT_FUNC5	0x40
972 #define QCA956X_GPIO_REG_IN_ENABLE0	0x44
973 #define QCA956X_GPIO_REG_IN_ENABLE3	0x50
974 #define QCA956X_GPIO_REG_FUNC		0x6c
975 
976 #define QCA956X_GPIO_OUT_MUX_GE0_MDO	32
977 #define QCA956X_GPIO_OUT_MUX_GE0_MDC	33
978 
979 #define AR71XX_GPIO_COUNT		16
980 #define AR7240_GPIO_COUNT		18
981 #define AR7241_GPIO_COUNT		20
982 #define AR913X_GPIO_COUNT		22
983 #define AR933X_GPIO_COUNT		30
984 #define AR934X_GPIO_COUNT		23
985 #define QCA953X_GPIO_COUNT		18
986 #define QCA955X_GPIO_COUNT		24
987 #define QCA956X_GPIO_COUNT		23
988 
989 /*
990  * SRIF block
991  */
992 #define AR934X_SRIF_CPU_DPLL1_REG	0x1c0
993 #define AR934X_SRIF_CPU_DPLL2_REG	0x1c4
994 #define AR934X_SRIF_CPU_DPLL3_REG	0x1c8
995 
996 #define AR934X_SRIF_DDR_DPLL1_REG	0x240
997 #define AR934X_SRIF_DDR_DPLL2_REG	0x244
998 #define AR934X_SRIF_DDR_DPLL3_REG	0x248
999 
1000 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
1001 #define AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
1002 #define AR934X_SRIF_DPLL1_NINT_SHIFT	18
1003 #define AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
1004 #define AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
1005 
1006 #define AR934X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
1007 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
1008 #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
1009 
1010 #define QCA953X_SRIF_CPU_DPLL1_REG	0x1c0
1011 #define QCA953X_SRIF_CPU_DPLL2_REG	0x1c4
1012 #define QCA953X_SRIF_CPU_DPLL3_REG	0x1c8
1013 
1014 #define QCA953X_SRIF_DDR_DPLL1_REG	0x240
1015 #define QCA953X_SRIF_DDR_DPLL2_REG	0x244
1016 #define QCA953X_SRIF_DDR_DPLL3_REG	0x248
1017 
1018 #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT	27
1019 #define QCA953X_SRIF_DPLL1_REFDIV_MASK	0x1f
1020 #define QCA953X_SRIF_DPLL1_NINT_SHIFT	18
1021 #define QCA953X_SRIF_DPLL1_NINT_MASK	0x1ff
1022 #define QCA953X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
1023 
1024 #define QCA953X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
1025 #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT	13
1026 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK	0x7
1027 
1028 #define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
1029 #define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
1030 #define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
1031 #define AR71XX_GPIO_FUNC_SPI_CS1_EN		BIT(12)
1032 #define AR71XX_GPIO_FUNC_UART_EN		BIT(8)
1033 #define AR71XX_GPIO_FUNC_USB_OC_EN		BIT(4)
1034 #define AR71XX_GPIO_FUNC_USB_CLK_EN		BIT(0)
1035 
1036 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
1037 #define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
1038 #define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
1039 #define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
1040 #define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
1041 #define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
1042 #define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
1043 #define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
1044 #define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
1045 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
1046 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
1047 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
1048 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
1049 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
1050 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
1051 #define AR724X_GPIO_FUNC_UART_EN		BIT(1)
1052 #define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
1053 
1054 #define AR913X_GPIO_FUNC_WMAC_LED_EN		BIT(22)
1055 #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN		BIT(21)
1056 #define AR913X_GPIO_FUNC_I2S_REFCLKEN		BIT(20)
1057 #define AR913X_GPIO_FUNC_I2S_MCKEN		BIT(19)
1058 #define AR913X_GPIO_FUNC_I2S1_EN		BIT(18)
1059 #define AR913X_GPIO_FUNC_I2S0_EN		BIT(17)
1060 #define AR913X_GPIO_FUNC_SLIC_EN		BIT(16)
1061 #define AR913X_GPIO_FUNC_UART_RTSCTS_EN		BIT(9)
1062 #define AR913X_GPIO_FUNC_UART_EN		BIT(8)
1063 #define AR913X_GPIO_FUNC_USB_CLK_EN		BIT(4)
1064 
1065 #define AR933X_GPIO_FUNC_SPDIF2TCK		BIT(31)
1066 #define AR933X_GPIO_FUNC_SPDIF_EN		BIT(30)
1067 #define AR933X_GPIO_FUNC_I2SO_22_18_EN		BIT(29)
1068 #define AR933X_GPIO_FUNC_I2S_MCK_EN		BIT(27)
1069 #define AR933X_GPIO_FUNC_I2SO_EN		BIT(26)
1070 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL	BIT(25)
1071 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL	BIT(24)
1072 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT	BIT(23)
1073 #define AR933X_GPIO_FUNC_SPI_EN			BIT(18)
1074 #define AR933X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
1075 #define AR933X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
1076 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
1077 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
1078 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
1079 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
1080 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
1081 #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
1082 #define AR933X_GPIO_FUNC_UART_EN		BIT(1)
1083 #define AR933X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
1084 
1085 #define AR934X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
1086 #define AR934X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
1087 #define AR934X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
1088 #define AR934X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
1089 #define AR934X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
1090 #define AR934X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
1091 #define AR934X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
1092 #define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
1093 #define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
1094 
1095 #define AR934X_GPIO_OUT_GPIO		0
1096 #define AR934X_GPIO_OUT_SPI_CS1	7
1097 #define AR934X_GPIO_OUT_LED_LINK0	41
1098 #define AR934X_GPIO_OUT_LED_LINK1	42
1099 #define AR934X_GPIO_OUT_LED_LINK2	43
1100 #define AR934X_GPIO_OUT_LED_LINK3	44
1101 #define AR934X_GPIO_OUT_LED_LINK4	45
1102 #define AR934X_GPIO_OUT_EXT_LNA0	46
1103 #define AR934X_GPIO_OUT_EXT_LNA1	47
1104 
1105 #define QCA955X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
1106 #define QCA955X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
1107 #define QCA955X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
1108 #define QCA955X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
1109 #define QCA955X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
1110 #define QCA955X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
1111 #define QCA955X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
1112 #define QCA955X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
1113 
1114 #define QCA955X_GPIO_OUT_GPIO		0
1115 #define QCA955X_MII_EXT_MDI		1
1116 #define QCA955X_SLIC_DATA_OUT		3
1117 #define QCA955X_SLIC_PCM_FS		4
1118 #define QCA955X_SLIC_PCM_CLK		5
1119 #define QCA955X_SPI_CLK			8
1120 #define QCA955X_SPI_CS_0		9
1121 #define QCA955X_SPI_CS_1		10
1122 #define QCA955X_SPI_CS_2		11
1123 #define QCA955X_SPI_MISO		12
1124 #define QCA955X_I2S_CLK			13
1125 #define QCA955X_I2S_WS			14
1126 #define QCA955X_I2S_SD			15
1127 #define QCA955X_I2S_MCK			16
1128 #define QCA955X_SPDIF_OUT		17
1129 #define QCA955X_UART1_TD		18
1130 #define QCA955X_UART1_RTS		19
1131 #define QCA955X_UART1_RD		20
1132 #define QCA955X_UART1_CTS		21
1133 #define QCA955X_UART0_SOUT		22
1134 #define QCA955X_SPDIF2_OUT		23
1135 #define QCA955X_LED_SGMII_SPEED0	24
1136 #define QCA955X_LED_SGMII_SPEED1	25
1137 #define QCA955X_LED_SGMII_DUPLEX	26
1138 #define QCA955X_LED_SGMII_LINK_UP	27
1139 #define QCA955X_SGMII_SPEED0_INVERT	28
1140 #define QCA955X_SGMII_SPEED1_INVERT	29
1141 #define QCA955X_SGMII_DUPLEX_INVERT	30
1142 #define QCA955X_SGMII_LINK_UP_INVERT	31
1143 #define QCA955X_GE1_MII_MDO		32
1144 #define QCA955X_GE1_MII_MDC		33
1145 #define QCA955X_SWCOM2			38
1146 #define QCA955X_SWCOM3			39
1147 #define QCA955X_MAC2_GPIO		40
1148 #define QCA955X_MAC3_GPIO		41
1149 #define QCA955X_ATT_LED			42
1150 #define QCA955X_PWR_LED			43
1151 #define QCA955X_TX_FRAME		44
1152 #define QCA955X_RX_CLEAR_EXTERNAL	45
1153 #define QCA955X_LED_NETWORK_EN		46
1154 #define QCA955X_LED_POWER_EN		47
1155 #define QCA955X_WMAC_GLUE_WOW		68
1156 #define QCA955X_RX_CLEAR_EXTENSION	70
1157 #define QCA955X_CP_NAND_CS1		73
1158 #define QCA955X_USB_SUSPEND		74
1159 #define QCA955X_ETH_TX_ERR		75
1160 #define QCA955X_DDR_DQ_OE		76
1161 #define QCA955X_CLKREQ_N_EP		77
1162 #define QCA955X_CLKREQ_N_RC		78
1163 #define QCA955X_CLK_OBS0		79
1164 #define QCA955X_CLK_OBS1		80
1165 #define QCA955X_CLK_OBS2		81
1166 #define QCA955X_CLK_OBS3		82
1167 #define QCA955X_CLK_OBS4		83
1168 #define QCA955X_CLK_OBS5		84
1169 
1170 /*
1171  * MII_CTRL block
1172  */
1173 #define AR71XX_MII_REG_MII0_CTRL	0x00
1174 #define AR71XX_MII_REG_MII1_CTRL	0x04
1175 
1176 #define AR71XX_MII_CTRL_IF_MASK		3
1177 #define AR71XX_MII_CTRL_SPEED_SHIFT	4
1178 #define AR71XX_MII_CTRL_SPEED_MASK	3
1179 #define AR71XX_MII_CTRL_SPEED_10	0
1180 #define AR71XX_MII_CTRL_SPEED_100	1
1181 #define AR71XX_MII_CTRL_SPEED_1000	2
1182 
1183 #define AR71XX_MII0_CTRL_IF_GMII	0
1184 #define AR71XX_MII0_CTRL_IF_MII		1
1185 #define AR71XX_MII0_CTRL_IF_RGMII	2
1186 #define AR71XX_MII0_CTRL_IF_RMII	3
1187 
1188 #define AR71XX_MII1_CTRL_IF_RGMII	0
1189 #define AR71XX_MII1_CTRL_IF_RMII	1
1190 
1191 /*
1192  * AR933X GMAC interface
1193  */
1194 #define AR933X_GMAC_REG_ETH_CFG		0x00
1195 
1196 #define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
1197 #define AR933X_ETH_CFG_MII_GE0		BIT(1)
1198 #define AR933X_ETH_CFG_GMII_GE0		BIT(2)
1199 #define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
1200 #define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
1201 #define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
1202 #define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
1203 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
1204 #define AR933X_ETH_CFG_RMII_GE0		BIT(9)
1205 #define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
1206 #define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)
1207 
1208 /*
1209  * AR934X GMAC Interface
1210  */
1211 #define AR934X_GMAC_REG_ETH_CFG		0x00
1212 
1213 #define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
1214 #define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
1215 #define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
1216 #define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
1217 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
1218 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
1219 #define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
1220 #define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
1221 #define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
1222 #define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
1223 #define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
1224 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
1225 #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
1226 #define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
1227 #define AR934X_ETH_CFG_RXD_DELAY_MASK   0x3
1228 #define AR934X_ETH_CFG_RXD_DELAY_SHIFT  14
1229 #define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
1230 #define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
1231 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
1232 
1233 /*
1234  * QCA953X GMAC Interface
1235  */
1236 #define QCA953X_GMAC_REG_ETH_CFG		0x00
1237 
1238 #define QCA953X_ETH_CFG_SW_ONLY_MODE		BIT(6)
1239 #define QCA953X_ETH_CFG_SW_PHY_SWAP		BIT(7)
1240 #define QCA953X_ETH_CFG_SW_APB_ACCESS		BIT(9)
1241 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
1242 
1243 /*
1244  * QCA955X GMAC Interface
1245  */
1246 
1247 #define QCA955X_GMAC_REG_ETH_CFG	0x00
1248 #define QCA955X_GMAC_REG_SGMII_SERDES	0x18
1249 
1250 #define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
1251 #define QCA955X_ETH_CFG_MII_GE0		BIT(1)
1252 #define QCA955X_ETH_CFG_GMII_GE0	BIT(2)
1253 #define QCA955X_ETH_CFG_MII_GE0_MASTER	BIT(3)
1254 #define QCA955X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
1255 #define QCA955X_ETH_CFG_GE0_ERR_EN	BIT(5)
1256 #define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
1257 #define QCA955X_ETH_CFG_RMII_GE0	BIT(10)
1258 #define QCA955X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
1259 #define QCA955X_ETH_CFG_RMII_GE0_MASTER	BIT(12)
1260 #define QCA955X_ETH_CFG_RXD_DELAY_MASK	0x3
1261 #define QCA955X_ETH_CFG_RXD_DELAY_SHIFT	14
1262 #define QCA955X_ETH_CFG_RDV_DELAY	BIT(16)
1263 #define QCA955X_ETH_CFG_RDV_DELAY_MASK	0x3
1264 #define QCA955X_ETH_CFG_RDV_DELAY_SHIFT	16
1265 #define QCA955X_ETH_CFG_TXD_DELAY_MASK	0x3
1266 #define QCA955X_ETH_CFG_TXD_DELAY_SHIFT	18
1267 #define QCA955X_ETH_CFG_TXE_DELAY_MASK	0x3
1268 #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT	20
1269 
1270 #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS	BIT(15)
1271 #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
1272 #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1273 /*
1274  * QCA956X GMAC Interface
1275  */
1276 
1277 #define QCA956X_GMAC_REG_ETH_CFG	0x00
1278 #define QCA956X_GMAC_REG_SGMII_RESET	0x14
1279 #define QCA956X_GMAC_REG_SGMII_SERDES	0x18
1280 #define QCA956X_GMAC_REG_MR_AN_CONTROL	0x1c
1281 #define QCA956X_GMAC_REG_SGMII_CONFIG	0x34
1282 #define QCA956X_GMAC_REG_SGMII_DEBUG	0x58
1283 
1284 #define QCA956X_ETH_CFG_RGMII_EN		BIT(0)
1285 #define QCA956X_ETH_CFG_GE0_SGMII		BIT(6)
1286 #define QCA956X_ETH_CFG_SW_ONLY_MODE		BIT(7)
1287 #define QCA956X_ETH_CFG_SW_PHY_SWAP		BIT(8)
1288 #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(9)
1289 #define QCA956X_ETH_CFG_SW_APB_ACCESS		BIT(10)
1290 #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
1291 #define QCA956X_ETH_CFG_RXD_DELAY_MASK		0x3
1292 #define QCA956X_ETH_CFG_RXD_DELAY_SHIFT		14
1293 #define QCA956X_ETH_CFG_RDV_DELAY_MASK		0x3
1294 #define QCA956X_ETH_CFG_RDV_DELAY_SHIFT		16
1295 
1296 #define QCA956X_SGMII_RESET_RX_CLK_N_RESET	0x0
1297 #define QCA956X_SGMII_RESET_RX_CLK_N		BIT(0)
1298 #define QCA956X_SGMII_RESET_TX_CLK_N		BIT(1)
1299 #define QCA956X_SGMII_RESET_RX_125M_N		BIT(2)
1300 #define QCA956X_SGMII_RESET_TX_125M_N		BIT(3)
1301 #define QCA956X_SGMII_RESET_HW_RX_125M_N	BIT(4)
1302 
1303 #define QCA956X_SGMII_SERDES_CDR_BW_MASK	0x3
1304 #define QCA956X_SGMII_SERDES_CDR_BW_SHIFT	1
1305 #define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK	0x7
1306 #define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT	4
1307 #define QCA956X_SGMII_SERDES_PLL_BW		BIT(8)
1308 #define QCA956X_SGMII_SERDES_VCO_FAST		BIT(9)
1309 #define QCA956X_SGMII_SERDES_VCO_SLOW		BIT(10)
1310 #define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS	BIT(15)
1311 #define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT	BIT(16)
1312 #define QCA956X_SGMII_SERDES_FIBER_SDO		BIT(17)
1313 #define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
1314 #define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
1315 #define QCA956X_SGMII_SERDES_VCO_REG_SHIFT	27
1316 #define QCA956X_SGMII_SERDES_VCO_REG_MASK	0xf
1317 
1318 #define QCA956X_MR_AN_CONTROL_AN_ENABLE		BIT(12)
1319 #define QCA956X_MR_AN_CONTROL_PHY_RESET		BIT(15)
1320 
1321 #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT	0
1322 #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK	0x7
1323 
1324 #endif /* __ASM_MACH_AR71XX_REGS_H */
1325