1 /* 2 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 20 #ifndef __AR7_H__ 21 #define __AR7_H__ 22 23 #include <linux/delay.h> 24 #include <linux/io.h> 25 #include <linux/errno.h> 26 27 #include <asm/addrspace.h> 28 29 #define AR7_SDRAM_BASE 0x14000000 30 31 #define AR7_REGS_BASE 0x08610000 32 33 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000) 34 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) 35 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */ 36 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) 37 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80) 38 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20) 39 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) 40 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) 41 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) 42 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) 43 #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) 44 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) 45 #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) 46 #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) 47 #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) 48 49 #define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00) 50 #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) 51 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 52 53 #define AR7_RESET_PEREPHERIAL 0x0 54 #define AR7_RESET_SOFTWARE 0x4 55 #define AR7_RESET_STATUS 0x8 56 57 #define AR7_RESET_BIT_CPMAC_LO 17 58 #define AR7_RESET_BIT_CPMAC_HI 21 59 #define AR7_RESET_BIT_MDIO 22 60 #define AR7_RESET_BIT_EPHY 26 61 62 /* GPIO control registers */ 63 #define AR7_GPIO_INPUT 0x0 64 #define AR7_GPIO_OUTPUT 0x4 65 #define AR7_GPIO_DIR 0x8 66 #define AR7_GPIO_ENABLE 0xc 67 68 #define AR7_CHIP_7100 0x18 69 #define AR7_CHIP_7200 0x2b 70 #define AR7_CHIP_7300 0x05 71 72 /* Interrupts */ 73 #define AR7_IRQ_UART0 15 74 #define AR7_IRQ_UART1 16 75 76 /* Clocks */ 77 #define AR7_AFE_CLOCK 35328000 78 #define AR7_REF_CLOCK 25000000 79 #define AR7_XTAL_CLOCK 24000000 80 81 /* DCL */ 82 #define AR7_WDT_HW_ENA 0x10 83 84 struct plat_cpmac_data { 85 int reset_bit; 86 int power_bit; 87 u32 phy_mask; 88 char dev_addr[6]; 89 }; 90 91 struct plat_dsl_data { 92 int reset_bit_dsl; 93 int reset_bit_sar; 94 }; 95 96 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; 97 98 static inline u16 ar7_chip_id(void) 99 { 100 return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; 101 } 102 103 static inline u8 ar7_chip_rev(void) 104 { 105 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; 106 } 107 108 static inline int ar7_cpu_freq(void) 109 { 110 return ar7_cpu_clock; 111 } 112 113 static inline int ar7_bus_freq(void) 114 { 115 return ar7_bus_clock; 116 } 117 118 static inline int ar7_vbus_freq(void) 119 { 120 return ar7_bus_clock / 2; 121 } 122 #define ar7_cpmac_freq ar7_vbus_freq 123 124 static inline int ar7_dsp_freq(void) 125 { 126 return ar7_dsp_clock; 127 } 128 129 static inline int ar7_has_high_cpmac(void) 130 { 131 u16 chip_id = ar7_chip_id(); 132 switch (chip_id) { 133 case AR7_CHIP_7100: 134 case AR7_CHIP_7200: 135 return 0; 136 case AR7_CHIP_7300: 137 return 1; 138 default: 139 return -ENXIO; 140 } 141 } 142 #define ar7_has_high_vlynq ar7_has_high_cpmac 143 #define ar7_has_second_uart ar7_has_high_cpmac 144 145 static inline void ar7_device_enable(u32 bit) 146 { 147 void *reset_reg = 148 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); 149 writel(readl(reset_reg) | (1 << bit), reset_reg); 150 msleep(20); 151 } 152 153 static inline void ar7_device_disable(u32 bit) 154 { 155 void *reset_reg = 156 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); 157 writel(readl(reset_reg) & ~(1 << bit), reset_reg); 158 msleep(20); 159 } 160 161 static inline void ar7_device_reset(u32 bit) 162 { 163 ar7_device_disable(bit); 164 ar7_device_enable(bit); 165 } 166 167 static inline void ar7_device_on(u32 bit) 168 { 169 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 170 writel(readl(power_reg) | (1 << bit), power_reg); 171 msleep(20); 172 } 173 174 static inline void ar7_device_off(u32 bit) 175 { 176 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 177 writel(readl(power_reg) & ~(1 << bit), power_reg); 178 msleep(20); 179 } 180 181 #endif /* __AR7_H__ */ 182