17ca5dc14SFlorian Fainelli /* 27ca5dc14SFlorian Fainelli * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> 37ca5dc14SFlorian Fainelli * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> 47ca5dc14SFlorian Fainelli * 57ca5dc14SFlorian Fainelli * This program is free software; you can redistribute it and/or modify 67ca5dc14SFlorian Fainelli * it under the terms of the GNU General Public License as published by 77ca5dc14SFlorian Fainelli * the Free Software Foundation; either version 2 of the License, or 87ca5dc14SFlorian Fainelli * (at your option) any later version. 97ca5dc14SFlorian Fainelli * 107ca5dc14SFlorian Fainelli * This program is distributed in the hope that it will be useful, 117ca5dc14SFlorian Fainelli * but WITHOUT ANY WARRANTY; without even the implied warranty of 127ca5dc14SFlorian Fainelli * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 137ca5dc14SFlorian Fainelli * GNU General Public License for more details. 147ca5dc14SFlorian Fainelli * 157ca5dc14SFlorian Fainelli * You should have received a copy of the GNU General Public License 167ca5dc14SFlorian Fainelli * along with this program; if not, write to the Free Software 177ca5dc14SFlorian Fainelli * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 187ca5dc14SFlorian Fainelli */ 197ca5dc14SFlorian Fainelli 207ca5dc14SFlorian Fainelli #ifndef __AR7_H__ 217ca5dc14SFlorian Fainelli #define __AR7_H__ 227ca5dc14SFlorian Fainelli 237ca5dc14SFlorian Fainelli #include <linux/delay.h> 247ca5dc14SFlorian Fainelli #include <linux/io.h> 257ca5dc14SFlorian Fainelli #include <linux/errno.h> 267ca5dc14SFlorian Fainelli 277ca5dc14SFlorian Fainelli #include <asm/addrspace.h> 287ca5dc14SFlorian Fainelli 297ca5dc14SFlorian Fainelli #define AR7_SDRAM_BASE 0x14000000 307ca5dc14SFlorian Fainelli 317ca5dc14SFlorian Fainelli #define AR7_REGS_BASE 0x08610000 327ca5dc14SFlorian Fainelli 337ca5dc14SFlorian Fainelli #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000) 347ca5dc14SFlorian Fainelli #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) 357ca5dc14SFlorian Fainelli /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */ 367ca5dc14SFlorian Fainelli #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) 377ca5dc14SFlorian Fainelli #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80) 387ca5dc14SFlorian Fainelli #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20) 397ca5dc14SFlorian Fainelli #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) 407ca5dc14SFlorian Fainelli #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) 417ca5dc14SFlorian Fainelli #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) 427ca5dc14SFlorian Fainelli #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) 437ca5dc14SFlorian Fainelli #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) 447ca5dc14SFlorian Fainelli #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) 457ca5dc14SFlorian Fainelli #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) 467ca5dc14SFlorian Fainelli #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) 477ca5dc14SFlorian Fainelli #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) 487ca5dc14SFlorian Fainelli 497ca5dc14SFlorian Fainelli #define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00) 507ca5dc14SFlorian Fainelli #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) 517ca5dc14SFlorian Fainelli #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 527ca5dc14SFlorian Fainelli 537ca5dc14SFlorian Fainelli #define AR7_RESET_PEREPHERIAL 0x0 547ca5dc14SFlorian Fainelli #define AR7_RESET_SOFTWARE 0x4 557ca5dc14SFlorian Fainelli #define AR7_RESET_STATUS 0x8 567ca5dc14SFlorian Fainelli 577ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_CPMAC_LO 17 587ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_CPMAC_HI 21 597ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_MDIO 22 607ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_EPHY 26 617ca5dc14SFlorian Fainelli 627ca5dc14SFlorian Fainelli /* GPIO control registers */ 637ca5dc14SFlorian Fainelli #define AR7_GPIO_INPUT 0x0 647ca5dc14SFlorian Fainelli #define AR7_GPIO_OUTPUT 0x4 657ca5dc14SFlorian Fainelli #define AR7_GPIO_DIR 0x8 667ca5dc14SFlorian Fainelli #define AR7_GPIO_ENABLE 0xc 677ca5dc14SFlorian Fainelli 687ca5dc14SFlorian Fainelli #define AR7_CHIP_7100 0x18 697ca5dc14SFlorian Fainelli #define AR7_CHIP_7200 0x2b 707ca5dc14SFlorian Fainelli #define AR7_CHIP_7300 0x05 717ca5dc14SFlorian Fainelli 727ca5dc14SFlorian Fainelli /* Interrupts */ 737ca5dc14SFlorian Fainelli #define AR7_IRQ_UART0 15 747ca5dc14SFlorian Fainelli #define AR7_IRQ_UART1 16 757ca5dc14SFlorian Fainelli 767ca5dc14SFlorian Fainelli /* Clocks */ 777ca5dc14SFlorian Fainelli #define AR7_AFE_CLOCK 35328000 787ca5dc14SFlorian Fainelli #define AR7_REF_CLOCK 25000000 797ca5dc14SFlorian Fainelli #define AR7_XTAL_CLOCK 24000000 807ca5dc14SFlorian Fainelli 8172838a17SFlorian Fainelli /* DCL */ 8272838a17SFlorian Fainelli #define AR7_WDT_HW_ENA 0x10 8372838a17SFlorian Fainelli 847ca5dc14SFlorian Fainelli struct plat_cpmac_data { 857ca5dc14SFlorian Fainelli int reset_bit; 867ca5dc14SFlorian Fainelli int power_bit; 877ca5dc14SFlorian Fainelli u32 phy_mask; 887ca5dc14SFlorian Fainelli char dev_addr[6]; 897ca5dc14SFlorian Fainelli }; 907ca5dc14SFlorian Fainelli 917ca5dc14SFlorian Fainelli struct plat_dsl_data { 927ca5dc14SFlorian Fainelli int reset_bit_dsl; 937ca5dc14SFlorian Fainelli int reset_bit_sar; 947ca5dc14SFlorian Fainelli }; 957ca5dc14SFlorian Fainelli 967ca5dc14SFlorian Fainelli extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; 977ca5dc14SFlorian Fainelli 987ca5dc14SFlorian Fainelli static inline u16 ar7_chip_id(void) 997ca5dc14SFlorian Fainelli { 1007ca5dc14SFlorian Fainelli return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; 1017ca5dc14SFlorian Fainelli } 1027ca5dc14SFlorian Fainelli 1037ca5dc14SFlorian Fainelli static inline u8 ar7_chip_rev(void) 1047ca5dc14SFlorian Fainelli { 1057ca5dc14SFlorian Fainelli return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; 1067ca5dc14SFlorian Fainelli } 1077ca5dc14SFlorian Fainelli 108780019ddSFlorian Fainelli struct clk { 109780019ddSFlorian Fainelli unsigned int rate; 110780019ddSFlorian Fainelli }; 1117ca5dc14SFlorian Fainelli 1127ca5dc14SFlorian Fainelli static inline int ar7_has_high_cpmac(void) 1137ca5dc14SFlorian Fainelli { 1147ca5dc14SFlorian Fainelli u16 chip_id = ar7_chip_id(); 1157ca5dc14SFlorian Fainelli switch (chip_id) { 1167ca5dc14SFlorian Fainelli case AR7_CHIP_7100: 1177ca5dc14SFlorian Fainelli case AR7_CHIP_7200: 1187ca5dc14SFlorian Fainelli return 0; 1197ca5dc14SFlorian Fainelli case AR7_CHIP_7300: 1207ca5dc14SFlorian Fainelli return 1; 1217ca5dc14SFlorian Fainelli default: 1227ca5dc14SFlorian Fainelli return -ENXIO; 1237ca5dc14SFlorian Fainelli } 1247ca5dc14SFlorian Fainelli } 1257ca5dc14SFlorian Fainelli #define ar7_has_high_vlynq ar7_has_high_cpmac 1267ca5dc14SFlorian Fainelli #define ar7_has_second_uart ar7_has_high_cpmac 1277ca5dc14SFlorian Fainelli 1287ca5dc14SFlorian Fainelli static inline void ar7_device_enable(u32 bit) 1297ca5dc14SFlorian Fainelli { 1307ca5dc14SFlorian Fainelli void *reset_reg = 1317ca5dc14SFlorian Fainelli (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); 1327ca5dc14SFlorian Fainelli writel(readl(reset_reg) | (1 << bit), reset_reg); 1337ca5dc14SFlorian Fainelli msleep(20); 1347ca5dc14SFlorian Fainelli } 1357ca5dc14SFlorian Fainelli 1367ca5dc14SFlorian Fainelli static inline void ar7_device_disable(u32 bit) 1377ca5dc14SFlorian Fainelli { 1387ca5dc14SFlorian Fainelli void *reset_reg = 1397ca5dc14SFlorian Fainelli (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); 1407ca5dc14SFlorian Fainelli writel(readl(reset_reg) & ~(1 << bit), reset_reg); 1417ca5dc14SFlorian Fainelli msleep(20); 1427ca5dc14SFlorian Fainelli } 1437ca5dc14SFlorian Fainelli 1447ca5dc14SFlorian Fainelli static inline void ar7_device_reset(u32 bit) 1457ca5dc14SFlorian Fainelli { 1467ca5dc14SFlorian Fainelli ar7_device_disable(bit); 1477ca5dc14SFlorian Fainelli ar7_device_enable(bit); 1487ca5dc14SFlorian Fainelli } 1497ca5dc14SFlorian Fainelli 1507ca5dc14SFlorian Fainelli static inline void ar7_device_on(u32 bit) 1517ca5dc14SFlorian Fainelli { 1527ca5dc14SFlorian Fainelli void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 1537ca5dc14SFlorian Fainelli writel(readl(power_reg) | (1 << bit), power_reg); 1547ca5dc14SFlorian Fainelli msleep(20); 1557ca5dc14SFlorian Fainelli } 1567ca5dc14SFlorian Fainelli 1577ca5dc14SFlorian Fainelli static inline void ar7_device_off(u32 bit) 1587ca5dc14SFlorian Fainelli { 1597ca5dc14SFlorian Fainelli void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 1607ca5dc14SFlorian Fainelli writel(readl(power_reg) & ~(1 << bit), power_reg); 1617ca5dc14SFlorian Fainelli msleep(20); 1627ca5dc14SFlorian Fainelli } 1637ca5dc14SFlorian Fainelli 1647ca5dc14SFlorian Fainelli #endif /* __AR7_H__ */ 165