1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Authors: Sanjay Lal <sanjayl@kymasys.com> 8 */ 9 10 #ifndef __MIPS_KVM_HOST_H__ 11 #define __MIPS_KVM_HOST_H__ 12 13 #include <linux/cpumask.h> 14 #include <linux/mutex.h> 15 #include <linux/hrtimer.h> 16 #include <linux/interrupt.h> 17 #include <linux/types.h> 18 #include <linux/kvm.h> 19 #include <linux/kvm_types.h> 20 #include <linux/threads.h> 21 #include <linux/spinlock.h> 22 23 #include <asm/inst.h> 24 #include <asm/mipsregs.h> 25 26 /* MIPS KVM register ids */ 27 #define MIPS_CP0_32(_R, _S) \ 28 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 29 30 #define MIPS_CP0_64(_R, _S) \ 31 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 32 33 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 34 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) 35 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) 36 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 37 #define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1) 38 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 39 #define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3) 40 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 41 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) 42 #define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2) 43 #define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3) 44 #define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4) 45 #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) 46 #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) 47 #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) 48 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 49 #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) 50 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 51 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 52 #define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1) 53 #define KVM_REG_MIPS_CP0_BADINSTRP MIPS_CP0_32(8, 2) 54 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 55 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 56 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 57 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 58 #define KVM_REG_MIPS_CP0_INTCTL MIPS_CP0_32(12, 1) 59 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 60 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 61 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 62 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) 63 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 64 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 65 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 66 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 67 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 68 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 69 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) 70 #define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2) 71 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) 72 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 73 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) 74 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) 75 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) 76 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) 77 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) 78 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) 79 80 81 #define KVM_MAX_VCPUS 8 82 #define KVM_USER_MEM_SLOTS 8 83 /* memory slots that does not exposed to userspace */ 84 #define KVM_PRIVATE_MEM_SLOTS 0 85 86 #define KVM_HALT_POLL_NS_DEFAULT 500000 87 88 #ifdef CONFIG_KVM_MIPS_VZ 89 extern unsigned long GUESTID_MASK; 90 extern unsigned long GUESTID_FIRST_VERSION; 91 extern unsigned long GUESTID_VERSION_MASK; 92 #endif 93 94 95 /* 96 * Special address that contains the comm page, used for reducing # of traps 97 * This needs to be within 32Kb of 0x0 (so the zero register can be used), but 98 * preferably not at 0x0 so that most kernel NULL pointer dereferences can be 99 * caught. 100 */ 101 #define KVM_GUEST_COMMPAGE_ADDR ((PAGE_SIZE > 0x8000) ? 0 : \ 102 (0x8000 - PAGE_SIZE)) 103 104 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ 105 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) 106 107 #define KVM_GUEST_KUSEG 0x00000000UL 108 #define KVM_GUEST_KSEG0 0x40000000UL 109 #define KVM_GUEST_KSEG1 0x40000000UL 110 #define KVM_GUEST_KSEG23 0x60000000UL 111 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000) 112 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 113 114 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 115 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) 116 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) 117 118 /* 119 * Map an address to a certain kernel segment 120 */ 121 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 122 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) 123 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) 124 125 #define KVM_INVALID_PAGE 0xdeadbeef 126 #define KVM_INVALID_ADDR 0xdeadbeef 127 128 /* 129 * EVA has overlapping user & kernel address spaces, so user VAs may be > 130 * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of 131 * PAGE_OFFSET. 132 */ 133 134 #define KVM_HVA_ERR_BAD (-1UL) 135 #define KVM_HVA_ERR_RO_BAD (-2UL) 136 137 static inline bool kvm_is_error_hva(unsigned long addr) 138 { 139 return IS_ERR_VALUE(addr); 140 } 141 142 struct kvm_vm_stat { 143 ulong remote_tlb_flush; 144 }; 145 146 struct kvm_vcpu_stat { 147 u64 wait_exits; 148 u64 cache_exits; 149 u64 signal_exits; 150 u64 int_exits; 151 u64 cop_unusable_exits; 152 u64 tlbmod_exits; 153 u64 tlbmiss_ld_exits; 154 u64 tlbmiss_st_exits; 155 u64 addrerr_st_exits; 156 u64 addrerr_ld_exits; 157 u64 syscall_exits; 158 u64 resvd_inst_exits; 159 u64 break_inst_exits; 160 u64 trap_inst_exits; 161 u64 msa_fpe_exits; 162 u64 fpe_exits; 163 u64 msa_disabled_exits; 164 u64 flush_dcache_exits; 165 #ifdef CONFIG_KVM_MIPS_VZ 166 u64 vz_gpsi_exits; 167 u64 vz_gsfc_exits; 168 u64 vz_hc_exits; 169 u64 vz_grr_exits; 170 u64 vz_gva_exits; 171 u64 vz_ghfc_exits; 172 u64 vz_gpa_exits; 173 u64 vz_resvd_exits; 174 #endif 175 u64 halt_successful_poll; 176 u64 halt_attempted_poll; 177 u64 halt_poll_success_ns; 178 u64 halt_poll_fail_ns; 179 u64 halt_poll_invalid; 180 u64 halt_wakeup; 181 }; 182 183 struct kvm_arch_memory_slot { 184 }; 185 186 struct kvm_arch { 187 /* Guest physical mm */ 188 struct mm_struct gpa_mm; 189 /* Mask of CPUs needing GPA ASID flush */ 190 cpumask_t asid_flush_mask; 191 }; 192 193 #define N_MIPS_COPROC_REGS 32 194 #define N_MIPS_COPROC_SEL 8 195 196 struct mips_coproc { 197 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; 198 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS 199 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; 200 #endif 201 }; 202 203 /* 204 * Coprocessor 0 register names 205 */ 206 #define MIPS_CP0_TLB_INDEX 0 207 #define MIPS_CP0_TLB_RANDOM 1 208 #define MIPS_CP0_TLB_LOW 2 209 #define MIPS_CP0_TLB_LO0 2 210 #define MIPS_CP0_TLB_LO1 3 211 #define MIPS_CP0_TLB_CONTEXT 4 212 #define MIPS_CP0_TLB_PG_MASK 5 213 #define MIPS_CP0_TLB_WIRED 6 214 #define MIPS_CP0_HWRENA 7 215 #define MIPS_CP0_BAD_VADDR 8 216 #define MIPS_CP0_COUNT 9 217 #define MIPS_CP0_TLB_HI 10 218 #define MIPS_CP0_COMPARE 11 219 #define MIPS_CP0_STATUS 12 220 #define MIPS_CP0_CAUSE 13 221 #define MIPS_CP0_EXC_PC 14 222 #define MIPS_CP0_PRID 15 223 #define MIPS_CP0_CONFIG 16 224 #define MIPS_CP0_LLADDR 17 225 #define MIPS_CP0_WATCH_LO 18 226 #define MIPS_CP0_WATCH_HI 19 227 #define MIPS_CP0_TLB_XCONTEXT 20 228 #define MIPS_CP0_ECC 26 229 #define MIPS_CP0_CACHE_ERR 27 230 #define MIPS_CP0_TAG_LO 28 231 #define MIPS_CP0_TAG_HI 29 232 #define MIPS_CP0_ERROR_PC 30 233 #define MIPS_CP0_DEBUG 23 234 #define MIPS_CP0_DEPC 24 235 #define MIPS_CP0_PERFCNT 25 236 #define MIPS_CP0_ERRCTL 26 237 #define MIPS_CP0_DATA_LO 28 238 #define MIPS_CP0_DATA_HI 29 239 #define MIPS_CP0_DESAVE 31 240 241 #define MIPS_CP0_CONFIG_SEL 0 242 #define MIPS_CP0_CONFIG1_SEL 1 243 #define MIPS_CP0_CONFIG2_SEL 2 244 #define MIPS_CP0_CONFIG3_SEL 3 245 #define MIPS_CP0_CONFIG4_SEL 4 246 #define MIPS_CP0_CONFIG5_SEL 5 247 248 #define MIPS_CP0_GUESTCTL2 10 249 #define MIPS_CP0_GUESTCTL2_SEL 5 250 #define MIPS_CP0_GTOFFSET 12 251 #define MIPS_CP0_GTOFFSET_SEL 7 252 253 /* Resume Flags */ 254 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ 255 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ 256 257 #define RESUME_GUEST 0 258 #define RESUME_GUEST_DR RESUME_FLAG_DR 259 #define RESUME_HOST RESUME_FLAG_HOST 260 261 enum emulation_result { 262 EMULATE_DONE, /* no further processing */ 263 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ 264 EMULATE_FAIL, /* can't emulate this instruction */ 265 EMULATE_WAIT, /* WAIT instruction */ 266 EMULATE_PRIV_FAIL, 267 EMULATE_EXCEPT, /* A guest exception has been generated */ 268 EMULATE_HYPERCALL, /* HYPCALL instruction */ 269 }; 270 271 #define mips3_paddr_to_tlbpfn(x) \ 272 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) 273 #define mips3_tlbpfn_to_paddr(x) \ 274 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) 275 276 #define MIPS3_PG_SHIFT 6 277 #define MIPS3_PG_FRAME 0x3fffffc0 278 279 #define VPN2_MASK 0xffffe000 280 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID 281 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G) 282 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) 283 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID) 284 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1) 285 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V) 286 #define TLB_IS_DIRTY(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D) 287 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ 288 ((y) & VPN2_MASK & ~(x).tlb_mask)) 289 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ 290 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID)) 291 292 struct kvm_mips_tlb { 293 long tlb_mask; 294 long tlb_hi; 295 long tlb_lo[2]; 296 }; 297 298 #define KVM_NR_MEM_OBJS 4 299 300 /* 301 * We don't want allocation failures within the mmu code, so we preallocate 302 * enough memory for a single page fault in a cache. 303 */ 304 struct kvm_mmu_memory_cache { 305 int nobjs; 306 void *objects[KVM_NR_MEM_OBJS]; 307 }; 308 309 #define KVM_MIPS_AUX_FPU 0x1 310 #define KVM_MIPS_AUX_MSA 0x2 311 312 #define KVM_MIPS_GUEST_TLB_SIZE 64 313 struct kvm_vcpu_arch { 314 void *guest_ebase; 315 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu); 316 317 /* Host registers preserved across guest mode execution */ 318 unsigned long host_stack; 319 unsigned long host_gp; 320 unsigned long host_pgd; 321 unsigned long host_entryhi; 322 323 /* Host CP0 registers used when handling exits from guest */ 324 unsigned long host_cp0_badvaddr; 325 unsigned long host_cp0_epc; 326 u32 host_cp0_cause; 327 u32 host_cp0_guestctl0; 328 u32 host_cp0_badinstr; 329 u32 host_cp0_badinstrp; 330 331 /* GPRS */ 332 unsigned long gprs[32]; 333 unsigned long hi; 334 unsigned long lo; 335 unsigned long pc; 336 337 /* FPU State */ 338 struct mips_fpu_struct fpu; 339 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */ 340 unsigned int aux_inuse; 341 342 /* COP0 State */ 343 struct mips_coproc *cop0; 344 345 /* Host KSEG0 address of the EI/DI offset */ 346 void *kseg0_commpage; 347 348 /* Resume PC after MMIO completion */ 349 unsigned long io_pc; 350 /* GPR used as IO source/target */ 351 u32 io_gpr; 352 353 struct hrtimer comparecount_timer; 354 /* Count timer control KVM register */ 355 u32 count_ctl; 356 /* Count bias from the raw time */ 357 u32 count_bias; 358 /* Frequency of timer in Hz */ 359 u32 count_hz; 360 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ 361 s64 count_dyn_bias; 362 /* Resume time */ 363 ktime_t count_resume; 364 /* Period of timer tick in ns */ 365 u64 count_period; 366 367 /* Bitmask of exceptions that are pending */ 368 unsigned long pending_exceptions; 369 370 /* Bitmask of pending exceptions to be cleared */ 371 unsigned long pending_exceptions_clr; 372 373 /* S/W Based TLB for guest */ 374 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; 375 376 /* Guest kernel/user [partial] mm */ 377 struct mm_struct guest_kernel_mm, guest_user_mm; 378 379 /* Guest ASID of last user mode execution */ 380 unsigned int last_user_gasid; 381 382 /* Cache some mmu pages needed inside spinlock regions */ 383 struct kvm_mmu_memory_cache mmu_page_cache; 384 385 #ifdef CONFIG_KVM_MIPS_VZ 386 /* vcpu's vzguestid is different on each host cpu in an smp system */ 387 u32 vzguestid[NR_CPUS]; 388 389 /* wired guest TLB entries */ 390 struct kvm_mips_tlb *wired_tlb; 391 unsigned int wired_tlb_limit; 392 unsigned int wired_tlb_used; 393 394 /* emulated guest MAAR registers */ 395 unsigned long maar[6]; 396 #endif 397 398 /* Last CPU the VCPU state was loaded on */ 399 int last_sched_cpu; 400 /* Last CPU the VCPU actually executed guest code on */ 401 int last_exec_cpu; 402 403 /* WAIT executed */ 404 int wait; 405 406 u8 fpu_enabled; 407 u8 msa_enabled; 408 }; 409 410 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, 411 unsigned long val) 412 { 413 unsigned long temp; 414 do { 415 __asm__ __volatile__( 416 " .set push \n" 417 " .set "MIPS_ISA_ARCH_LEVEL" \n" 418 " " __LL "%0, %1 \n" 419 " or %0, %2 \n" 420 " " __SC "%0, %1 \n" 421 " .set pop \n" 422 : "=&r" (temp), "+m" (*reg) 423 : "r" (val)); 424 } while (unlikely(!temp)); 425 } 426 427 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, 428 unsigned long val) 429 { 430 unsigned long temp; 431 do { 432 __asm__ __volatile__( 433 " .set push \n" 434 " .set "MIPS_ISA_ARCH_LEVEL" \n" 435 " " __LL "%0, %1 \n" 436 " and %0, %2 \n" 437 " " __SC "%0, %1 \n" 438 " .set pop \n" 439 : "=&r" (temp), "+m" (*reg) 440 : "r" (~val)); 441 } while (unlikely(!temp)); 442 } 443 444 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, 445 unsigned long change, 446 unsigned long val) 447 { 448 unsigned long temp; 449 do { 450 __asm__ __volatile__( 451 " .set push \n" 452 " .set "MIPS_ISA_ARCH_LEVEL" \n" 453 " " __LL "%0, %1 \n" 454 " and %0, %2 \n" 455 " or %0, %3 \n" 456 " " __SC "%0, %1 \n" 457 " .set pop \n" 458 : "=&r" (temp), "+m" (*reg) 459 : "r" (~change), "r" (val & change)); 460 } while (unlikely(!temp)); 461 } 462 463 /* Guest register types, used in accessor build below */ 464 #define __KVMT32 u32 465 #define __KVMTl unsigned long 466 467 /* 468 * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg() 469 * These operate on the saved guest C0 state in RAM. 470 */ 471 472 /* Generate saved context simple accessors */ 473 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ 474 static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \ 475 { \ 476 return cop0->reg[(_reg)][(sel)]; \ 477 } \ 478 static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0, \ 479 __KVMT##type val) \ 480 { \ 481 cop0->reg[(_reg)][(sel)] = val; \ 482 } 483 484 /* Generate saved context bitwise modifiers */ 485 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ 486 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \ 487 __KVMT##type val) \ 488 { \ 489 cop0->reg[(_reg)][(sel)] |= val; \ 490 } \ 491 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \ 492 __KVMT##type val) \ 493 { \ 494 cop0->reg[(_reg)][(sel)] &= ~val; \ 495 } \ 496 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \ 497 __KVMT##type mask, \ 498 __KVMT##type val) \ 499 { \ 500 unsigned long _mask = mask; \ 501 cop0->reg[(_reg)][(sel)] &= ~_mask; \ 502 cop0->reg[(_reg)][(sel)] |= val & _mask; \ 503 } 504 505 /* Generate saved context atomic bitwise modifiers */ 506 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ 507 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \ 508 __KVMT##type val) \ 509 { \ 510 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ 511 } \ 512 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \ 513 __KVMT##type val) \ 514 { \ 515 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ 516 } \ 517 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \ 518 __KVMT##type mask, \ 519 __KVMT##type val) \ 520 { \ 521 _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \ 522 val); \ 523 } 524 525 /* 526 * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg() 527 * These operate on the VZ guest C0 context in hardware. 528 */ 529 530 /* Generate VZ guest context simple accessors */ 531 #define __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ 532 static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \ 533 { \ 534 return read_gc0_##name(); \ 535 } \ 536 static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0, \ 537 __KVMT##type val) \ 538 { \ 539 write_gc0_##name(val); \ 540 } 541 542 /* Generate VZ guest context bitwise modifiers */ 543 #define __BUILD_KVM_SET_VZ(name, type, _reg, sel) \ 544 static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0, \ 545 __KVMT##type val) \ 546 { \ 547 set_gc0_##name(val); \ 548 } \ 549 static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0, \ 550 __KVMT##type val) \ 551 { \ 552 clear_gc0_##name(val); \ 553 } \ 554 static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0, \ 555 __KVMT##type mask, \ 556 __KVMT##type val) \ 557 { \ 558 change_gc0_##name(mask, val); \ 559 } 560 561 /* Generate VZ guest context save/restore to/from saved context */ 562 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \ 563 static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0) \ 564 { \ 565 write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ 566 } \ 567 static inline void kvm_save_gc0_##name(struct mips_coproc *cop0) \ 568 { \ 569 cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \ 570 } 571 572 /* 573 * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2() 574 * These wrap a set of operations to provide them with a different name. 575 */ 576 577 /* Generate simple accessor wrapper */ 578 #define __BUILD_KVM_RW_WRAP(name1, name2, type) \ 579 static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0) \ 580 { \ 581 return kvm_read_##name2(cop0); \ 582 } \ 583 static inline void kvm_write_##name1(struct mips_coproc *cop0, \ 584 __KVMT##type val) \ 585 { \ 586 kvm_write_##name2(cop0, val); \ 587 } 588 589 /* Generate bitwise modifier wrapper */ 590 #define __BUILD_KVM_SET_WRAP(name1, name2, type) \ 591 static inline void kvm_set_##name1(struct mips_coproc *cop0, \ 592 __KVMT##type val) \ 593 { \ 594 kvm_set_##name2(cop0, val); \ 595 } \ 596 static inline void kvm_clear_##name1(struct mips_coproc *cop0, \ 597 __KVMT##type val) \ 598 { \ 599 kvm_clear_##name2(cop0, val); \ 600 } \ 601 static inline void kvm_change_##name1(struct mips_coproc *cop0, \ 602 __KVMT##type mask, \ 603 __KVMT##type val) \ 604 { \ 605 kvm_change_##name2(cop0, mask, val); \ 606 } 607 608 /* 609 * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg() 610 * These generate accessors operating on the saved context in RAM, and wrap them 611 * with the common guest C0 accessors (for use by common emulation code). 612 */ 613 614 #define __BUILD_KVM_RW_SW(name, type, _reg, sel) \ 615 __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ 616 __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type) 617 618 #define __BUILD_KVM_SET_SW(name, type, _reg, sel) \ 619 __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ 620 __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type) 621 622 #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel) \ 623 __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ 624 __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type) 625 626 #ifndef CONFIG_KVM_MIPS_VZ 627 628 /* 629 * T&E (trap & emulate software based virtualisation) 630 * We generate the common accessors operating exclusively on the saved context 631 * in RAM. 632 */ 633 634 #define __BUILD_KVM_RW_HW __BUILD_KVM_RW_SW 635 #define __BUILD_KVM_SET_HW __BUILD_KVM_SET_SW 636 #define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_ATOMIC_SW 637 638 #else 639 640 /* 641 * VZ (hardware assisted virtualisation) 642 * These macros use the active guest state in VZ mode (hardware registers), 643 */ 644 645 /* 646 * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg() 647 * These generate accessors operating on the VZ guest context in hardware, and 648 * wrap them with the common guest C0 accessors (for use by common emulation 649 * code). 650 * 651 * Accessors operating on the saved context in RAM are also generated to allow 652 * convenient explicit saving and restoring of the state. 653 */ 654 655 #define __BUILD_KVM_RW_HW(name, type, _reg, sel) \ 656 __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ 657 __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ 658 __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type) \ 659 __BUILD_KVM_SAVE_VZ(name, _reg, sel) 660 661 #define __BUILD_KVM_SET_HW(name, type, _reg, sel) \ 662 __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ 663 __BUILD_KVM_SET_VZ(name, type, _reg, sel) \ 664 __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type) 665 666 /* 667 * We can't do atomic modifications of COP0 state if hardware can modify it. 668 * Races must be handled explicitly. 669 */ 670 #define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_SET_HW 671 672 #endif 673 674 /* 675 * Define accessors for CP0 registers that are accessible to the guest. These 676 * are primarily used by common emulation code, which may need to access the 677 * registers differently depending on the implementation. 678 * 679 * fns_hw/sw name type reg num select 680 */ 681 __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0) 682 __BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0) 683 __BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0) 684 __BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0) 685 __BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1) 686 __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2) 687 __BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3) 688 __BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0) 689 __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1) 690 __BUILD_KVM_RW_HW(segctl0, l, MIPS_CP0_TLB_PG_MASK, 2) 691 __BUILD_KVM_RW_HW(segctl1, l, MIPS_CP0_TLB_PG_MASK, 3) 692 __BUILD_KVM_RW_HW(segctl2, l, MIPS_CP0_TLB_PG_MASK, 4) 693 __BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5) 694 __BUILD_KVM_RW_HW(pwfield, l, MIPS_CP0_TLB_PG_MASK, 6) 695 __BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7) 696 __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0) 697 __BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED, 6) 698 __BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0) 699 __BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR, 0) 700 __BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR, 1) 701 __BUILD_KVM_RW_HW(badinstrp, 32, MIPS_CP0_BAD_VADDR, 2) 702 __BUILD_KVM_RW_SW(count, 32, MIPS_CP0_COUNT, 0) 703 __BUILD_KVM_RW_HW(entryhi, l, MIPS_CP0_TLB_HI, 0) 704 __BUILD_KVM_RW_HW(compare, 32, MIPS_CP0_COMPARE, 0) 705 __BUILD_KVM_RW_HW(status, 32, MIPS_CP0_STATUS, 0) 706 __BUILD_KVM_RW_HW(intctl, 32, MIPS_CP0_STATUS, 1) 707 __BUILD_KVM_RW_HW(cause, 32, MIPS_CP0_CAUSE, 0) 708 __BUILD_KVM_RW_HW(epc, l, MIPS_CP0_EXC_PC, 0) 709 __BUILD_KVM_RW_SW(prid, 32, MIPS_CP0_PRID, 0) 710 __BUILD_KVM_RW_HW(ebase, l, MIPS_CP0_PRID, 1) 711 __BUILD_KVM_RW_HW(config, 32, MIPS_CP0_CONFIG, 0) 712 __BUILD_KVM_RW_HW(config1, 32, MIPS_CP0_CONFIG, 1) 713 __BUILD_KVM_RW_HW(config2, 32, MIPS_CP0_CONFIG, 2) 714 __BUILD_KVM_RW_HW(config3, 32, MIPS_CP0_CONFIG, 3) 715 __BUILD_KVM_RW_HW(config4, 32, MIPS_CP0_CONFIG, 4) 716 __BUILD_KVM_RW_HW(config5, 32, MIPS_CP0_CONFIG, 5) 717 __BUILD_KVM_RW_HW(config6, 32, MIPS_CP0_CONFIG, 6) 718 __BUILD_KVM_RW_HW(config7, 32, MIPS_CP0_CONFIG, 7) 719 __BUILD_KVM_RW_SW(maari, l, MIPS_CP0_LLADDR, 2) 720 __BUILD_KVM_RW_HW(xcontext, l, MIPS_CP0_TLB_XCONTEXT, 0) 721 __BUILD_KVM_RW_HW(errorepc, l, MIPS_CP0_ERROR_PC, 0) 722 __BUILD_KVM_RW_HW(kscratch1, l, MIPS_CP0_DESAVE, 2) 723 __BUILD_KVM_RW_HW(kscratch2, l, MIPS_CP0_DESAVE, 3) 724 __BUILD_KVM_RW_HW(kscratch3, l, MIPS_CP0_DESAVE, 4) 725 __BUILD_KVM_RW_HW(kscratch4, l, MIPS_CP0_DESAVE, 5) 726 __BUILD_KVM_RW_HW(kscratch5, l, MIPS_CP0_DESAVE, 6) 727 __BUILD_KVM_RW_HW(kscratch6, l, MIPS_CP0_DESAVE, 7) 728 729 /* Bitwise operations (on HW state) */ 730 __BUILD_KVM_SET_HW(status, 32, MIPS_CP0_STATUS, 0) 731 /* Cause can be modified asynchronously from hardirq hrtimer callback */ 732 __BUILD_KVM_ATOMIC_HW(cause, 32, MIPS_CP0_CAUSE, 0) 733 __BUILD_KVM_SET_HW(ebase, l, MIPS_CP0_PRID, 1) 734 735 /* Bitwise operations (on saved state) */ 736 __BUILD_KVM_SET_SAVED(config, 32, MIPS_CP0_CONFIG, 0) 737 __BUILD_KVM_SET_SAVED(config1, 32, MIPS_CP0_CONFIG, 1) 738 __BUILD_KVM_SET_SAVED(config2, 32, MIPS_CP0_CONFIG, 2) 739 __BUILD_KVM_SET_SAVED(config3, 32, MIPS_CP0_CONFIG, 3) 740 __BUILD_KVM_SET_SAVED(config4, 32, MIPS_CP0_CONFIG, 4) 741 __BUILD_KVM_SET_SAVED(config5, 32, MIPS_CP0_CONFIG, 5) 742 743 /* Helpers */ 744 745 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu) 746 { 747 return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) && 748 vcpu->fpu_enabled; 749 } 750 751 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu) 752 { 753 return kvm_mips_guest_can_have_fpu(vcpu) && 754 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; 755 } 756 757 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu) 758 { 759 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) && 760 vcpu->msa_enabled; 761 } 762 763 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu) 764 { 765 return kvm_mips_guest_can_have_msa(vcpu) && 766 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; 767 } 768 769 struct kvm_mips_callbacks { 770 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); 771 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); 772 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); 773 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); 774 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); 775 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); 776 int (*handle_syscall)(struct kvm_vcpu *vcpu); 777 int (*handle_res_inst)(struct kvm_vcpu *vcpu); 778 int (*handle_break)(struct kvm_vcpu *vcpu); 779 int (*handle_trap)(struct kvm_vcpu *vcpu); 780 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu); 781 int (*handle_fpe)(struct kvm_vcpu *vcpu); 782 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); 783 int (*handle_guest_exit)(struct kvm_vcpu *vcpu); 784 int (*hardware_enable)(void); 785 void (*hardware_disable)(void); 786 int (*check_extension)(struct kvm *kvm, long ext); 787 int (*vcpu_init)(struct kvm_vcpu *vcpu); 788 void (*vcpu_uninit)(struct kvm_vcpu *vcpu); 789 int (*vcpu_setup)(struct kvm_vcpu *vcpu); 790 void (*flush_shadow_all)(struct kvm *kvm); 791 /* 792 * Must take care of flushing any cached GPA PTEs (e.g. guest entries in 793 * VZ root TLB, or T&E GVA page tables and corresponding root TLB 794 * mappings). 795 */ 796 void (*flush_shadow_memslot)(struct kvm *kvm, 797 const struct kvm_memory_slot *slot); 798 gpa_t (*gva_to_gpa)(gva_t gva); 799 void (*queue_timer_int)(struct kvm_vcpu *vcpu); 800 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); 801 void (*queue_io_int)(struct kvm_vcpu *vcpu, 802 struct kvm_mips_interrupt *irq); 803 void (*dequeue_io_int)(struct kvm_vcpu *vcpu, 804 struct kvm_mips_interrupt *irq); 805 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, 806 u32 cause); 807 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, 808 u32 cause); 809 unsigned long (*num_regs)(struct kvm_vcpu *vcpu); 810 int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices); 811 int (*get_one_reg)(struct kvm_vcpu *vcpu, 812 const struct kvm_one_reg *reg, s64 *v); 813 int (*set_one_reg)(struct kvm_vcpu *vcpu, 814 const struct kvm_one_reg *reg, s64 v); 815 int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 816 int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu); 817 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu); 818 void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu); 819 }; 820 extern struct kvm_mips_callbacks *kvm_mips_callbacks; 821 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); 822 823 /* Debug: dump vcpu state */ 824 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); 825 826 extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu); 827 828 /* Building of entry/exception code */ 829 int kvm_mips_entry_setup(void); 830 void *kvm_mips_build_vcpu_run(void *addr); 831 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler); 832 void *kvm_mips_build_exception(void *addr, void *handler); 833 void *kvm_mips_build_exit(void *addr); 834 835 /* FPU/MSA context management */ 836 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu); 837 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu); 838 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu); 839 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu); 840 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu); 841 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu); 842 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu); 843 void kvm_own_fpu(struct kvm_vcpu *vcpu); 844 void kvm_own_msa(struct kvm_vcpu *vcpu); 845 void kvm_drop_fpu(struct kvm_vcpu *vcpu); 846 void kvm_lose_fpu(struct kvm_vcpu *vcpu); 847 848 /* TLB handling */ 849 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu); 850 851 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu); 852 853 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu); 854 855 #ifdef CONFIG_KVM_MIPS_VZ 856 int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr, 857 struct kvm_vcpu *vcpu, bool write_fault); 858 #endif 859 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, 860 struct kvm_vcpu *vcpu, 861 bool write_fault); 862 863 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, 864 struct kvm_vcpu *vcpu); 865 866 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, 867 struct kvm_mips_tlb *tlb, 868 unsigned long gva, 869 bool write_fault); 870 871 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, 872 u32 *opc, 873 struct kvm_run *run, 874 struct kvm_vcpu *vcpu, 875 bool write_fault); 876 877 extern void kvm_mips_dump_host_tlbs(void); 878 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 879 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi, 880 bool user, bool kernel); 881 882 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, 883 unsigned long entryhi); 884 885 #ifdef CONFIG_KVM_MIPS_VZ 886 int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 887 int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva, 888 unsigned long *gpa); 889 void kvm_vz_local_flush_roottlb_all_guests(void); 890 void kvm_vz_local_flush_guesttlb_all(void); 891 void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index, 892 unsigned int count); 893 void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index, 894 unsigned int count); 895 #endif 896 897 void kvm_mips_suspend_mm(int cpu); 898 void kvm_mips_resume_mm(int cpu); 899 900 /* MMU handling */ 901 902 /** 903 * enum kvm_mips_flush - Types of MMU flushes. 904 * @KMF_USER: Flush guest user virtual memory mappings. 905 * Guest USeg only. 906 * @KMF_KERN: Flush guest kernel virtual memory mappings. 907 * Guest USeg and KSeg2/3. 908 * @KMF_GPA: Flush guest physical memory mappings. 909 * Also includes KSeg0 if KMF_KERN is set. 910 */ 911 enum kvm_mips_flush { 912 KMF_USER = 0x0, 913 KMF_KERN = 0x1, 914 KMF_GPA = 0x2, 915 }; 916 void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags); 917 bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn); 918 int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn); 919 pgd_t *kvm_pgd_alloc(void); 920 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); 921 void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr, 922 bool user); 923 void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu); 924 void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu); 925 926 enum kvm_mips_fault_result { 927 KVM_MIPS_MAPPED = 0, 928 KVM_MIPS_GVA, 929 KVM_MIPS_GPA, 930 KVM_MIPS_TLB, 931 KVM_MIPS_TLBINV, 932 KVM_MIPS_TLBMOD, 933 }; 934 enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu, 935 unsigned long gva, 936 bool write); 937 938 #define KVM_ARCH_WANT_MMU_NOTIFIER 939 int kvm_unmap_hva_range(struct kvm *kvm, 940 unsigned long start, unsigned long end); 941 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 942 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 943 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 944 945 /* Emulation */ 946 int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out); 947 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause); 948 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out); 949 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out); 950 951 /** 952 * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault. 953 * @vcpu: Virtual CPU. 954 * 955 * Returns: Whether the TLBL exception was likely due to an instruction 956 * fetch fault rather than a data load fault. 957 */ 958 static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu) 959 { 960 unsigned long badvaddr = vcpu->host_cp0_badvaddr; 961 unsigned long epc = msk_isa16_mode(vcpu->pc); 962 u32 cause = vcpu->host_cp0_cause; 963 964 if (epc == badvaddr) 965 return true; 966 967 /* 968 * Branches may be 32-bit or 16-bit instructions. 969 * This isn't exact, but we don't really support MIPS16 or microMIPS yet 970 * in KVM anyway. 971 */ 972 if ((cause & CAUSEF_BD) && badvaddr - epc <= 4) 973 return true; 974 975 return false; 976 } 977 978 extern enum emulation_result kvm_mips_emulate_inst(u32 cause, 979 u32 *opc, 980 struct kvm_run *run, 981 struct kvm_vcpu *vcpu); 982 983 long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu); 984 985 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause, 986 u32 *opc, 987 struct kvm_run *run, 988 struct kvm_vcpu *vcpu); 989 990 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, 991 u32 *opc, 992 struct kvm_run *run, 993 struct kvm_vcpu *vcpu); 994 995 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, 996 u32 *opc, 997 struct kvm_run *run, 998 struct kvm_vcpu *vcpu); 999 1000 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, 1001 u32 *opc, 1002 struct kvm_run *run, 1003 struct kvm_vcpu *vcpu); 1004 1005 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, 1006 u32 *opc, 1007 struct kvm_run *run, 1008 struct kvm_vcpu *vcpu); 1009 1010 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, 1011 u32 *opc, 1012 struct kvm_run *run, 1013 struct kvm_vcpu *vcpu); 1014 1015 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, 1016 u32 *opc, 1017 struct kvm_run *run, 1018 struct kvm_vcpu *vcpu); 1019 1020 extern enum emulation_result kvm_mips_handle_ri(u32 cause, 1021 u32 *opc, 1022 struct kvm_run *run, 1023 struct kvm_vcpu *vcpu); 1024 1025 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, 1026 u32 *opc, 1027 struct kvm_run *run, 1028 struct kvm_vcpu *vcpu); 1029 1030 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, 1031 u32 *opc, 1032 struct kvm_run *run, 1033 struct kvm_vcpu *vcpu); 1034 1035 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, 1036 u32 *opc, 1037 struct kvm_run *run, 1038 struct kvm_vcpu *vcpu); 1039 1040 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, 1041 u32 *opc, 1042 struct kvm_run *run, 1043 struct kvm_vcpu *vcpu); 1044 1045 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, 1046 u32 *opc, 1047 struct kvm_run *run, 1048 struct kvm_vcpu *vcpu); 1049 1050 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, 1051 u32 *opc, 1052 struct kvm_run *run, 1053 struct kvm_vcpu *vcpu); 1054 1055 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, 1056 struct kvm_run *run); 1057 1058 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu); 1059 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count); 1060 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack); 1061 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz); 1062 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); 1063 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); 1064 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); 1065 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); 1066 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); 1067 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); 1068 1069 /* fairly internal functions requiring some care to use */ 1070 int kvm_mips_count_disabled(struct kvm_vcpu *vcpu); 1071 ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count); 1072 int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before, 1073 u32 count, int min_drift); 1074 1075 #ifdef CONFIG_KVM_MIPS_VZ 1076 void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu); 1077 void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu); 1078 #else 1079 static inline void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) {} 1080 static inline void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu) {} 1081 #endif 1082 1083 enum emulation_result kvm_mips_check_privilege(u32 cause, 1084 u32 *opc, 1085 struct kvm_run *run, 1086 struct kvm_vcpu *vcpu); 1087 1088 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst, 1089 u32 *opc, 1090 u32 cause, 1091 struct kvm_run *run, 1092 struct kvm_vcpu *vcpu); 1093 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, 1094 u32 *opc, 1095 u32 cause, 1096 struct kvm_run *run, 1097 struct kvm_vcpu *vcpu); 1098 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst, 1099 u32 cause, 1100 struct kvm_run *run, 1101 struct kvm_vcpu *vcpu); 1102 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst, 1103 u32 cause, 1104 struct kvm_run *run, 1105 struct kvm_vcpu *vcpu); 1106 1107 /* COP0 */ 1108 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu); 1109 1110 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu); 1111 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu); 1112 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu); 1113 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu); 1114 1115 /* Hypercalls (hypcall.c) */ 1116 1117 enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu, 1118 union mips_instruction inst); 1119 int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu); 1120 1121 /* Dynamic binary translation */ 1122 extern int kvm_mips_trans_cache_index(union mips_instruction inst, 1123 u32 *opc, struct kvm_vcpu *vcpu); 1124 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc, 1125 struct kvm_vcpu *vcpu); 1126 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc, 1127 struct kvm_vcpu *vcpu); 1128 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc, 1129 struct kvm_vcpu *vcpu); 1130 1131 /* Misc */ 1132 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); 1133 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); 1134 1135 static inline void kvm_arch_hardware_unsetup(void) {} 1136 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1137 static inline void kvm_arch_free_memslot(struct kvm *kvm, 1138 struct kvm_memory_slot *slot) {} 1139 static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {} 1140 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 1141 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {} 1142 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {} 1143 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1144 1145 #endif /* __MIPS_KVM_HOST_H__ */ 1146