1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support 4 */ 5 #ifndef _ASM_JAZZDMA_H 6 #define _ASM_JAZZDMA_H 7 8 /* 9 * Prototypes and macros 10 */ 11 extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); 12 extern int vdma_free(unsigned long laddr); 13 extern int vdma_remap(unsigned long laddr, unsigned long paddr, 14 unsigned long size); 15 extern unsigned long vdma_phys2log(unsigned long paddr); 16 extern unsigned long vdma_log2phys(unsigned long laddr); 17 extern void vdma_stats(void); /* for debugging only */ 18 19 extern void vdma_enable(int channel); 20 extern void vdma_disable(int channel); 21 extern void vdma_set_mode(int channel, int mode); 22 extern void vdma_set_addr(int channel, long addr); 23 extern void vdma_set_count(int channel, int count); 24 extern int vdma_get_residue(int channel); 25 extern int vdma_get_enable(int channel); 26 27 /* 28 * some definitions used by the driver functions 29 */ 30 #define VDMA_PAGESIZE 4096 31 #define VDMA_PGTBL_ENTRIES 4096 32 #define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES) 33 #define VDMA_PAGE_EMPTY 0xff000000 34 35 /* 36 * Macros to get page no. and offset of a given address 37 * Note that VDMA_PAGE() works for physical addresses only 38 */ 39 #define VDMA_PAGE(a) ((unsigned int)(a) >> 12) 40 #define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1)) 41 42 /* 43 * error code returned by vdma_alloc() 44 * (See also arch/mips/kernel/jazzdma.c) 45 */ 46 #define VDMA_ERROR 0xffffffff 47 48 /* 49 * VDMA pagetable entry description 50 */ 51 typedef volatile struct VDMA_PGTBL_ENTRY { 52 unsigned int frame; /* physical frame no. */ 53 unsigned int owner; /* owner of this entry (0=free) */ 54 } VDMA_PGTBL_ENTRY; 55 56 57 /* 58 * DMA channel control registers 59 * in the R4030 MCT_ADR chip 60 */ 61 #define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */ 62 /* 0xE0000100,120,140... */ 63 #define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ 64 /* 0xE0000108,128,148... */ 65 #define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */ 66 /* 0xE0000110,130,150... */ 67 #define JAZZ_R4030_CHNL_ADDR 0xE0000118 /* 8 DMA Channel Address Regs, */ 68 /* 0xE0000118,138,158... */ 69 70 /* channel enable register bits */ 71 72 #define R4030_CHNL_ENABLE (1<<0) 73 #define R4030_CHNL_WRITE (1<<1) 74 #define R4030_TC_INTR (1<<8) 75 #define R4030_MEM_INTR (1<<9) 76 #define R4030_ADDR_INTR (1<<10) 77 78 /* 79 * Channel mode register bits 80 */ 81 #define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ 82 #define R4030_MODE_ATIME_80 (1) 83 #define R4030_MODE_ATIME_120 (2) 84 #define R4030_MODE_ATIME_160 (3) 85 #define R4030_MODE_ATIME_200 (4) 86 #define R4030_MODE_ATIME_240 (5) 87 #define R4030_MODE_ATIME_280 (6) 88 #define R4030_MODE_ATIME_320 (7) 89 #define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */ 90 #define R4030_MODE_WIDTH_16 (2<<3) 91 #define R4030_MODE_WIDTH_32 (3<<3) 92 #define R4030_MODE_INTR_EN (1<<5) 93 #define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ 94 #define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ 95 96 #endif /* _ASM_JAZZDMA_H */ 97