1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support 4384740dcSRalf Baechle */ 5384740dcSRalf Baechle #ifndef _ASM_JAZZDMA_H 6384740dcSRalf Baechle #define _ASM_JAZZDMA_H 7384740dcSRalf Baechle 8384740dcSRalf Baechle /* 9384740dcSRalf Baechle * Prototypes and macros 10384740dcSRalf Baechle */ 11384740dcSRalf Baechle extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); 12384740dcSRalf Baechle extern int vdma_free(unsigned long laddr); 13384740dcSRalf Baechle extern unsigned long vdma_phys2log(unsigned long paddr); 14384740dcSRalf Baechle extern unsigned long vdma_log2phys(unsigned long laddr); 15384740dcSRalf Baechle extern void vdma_stats(void); /* for debugging only */ 16384740dcSRalf Baechle 17384740dcSRalf Baechle extern void vdma_enable(int channel); 18384740dcSRalf Baechle extern void vdma_disable(int channel); 19384740dcSRalf Baechle extern void vdma_set_mode(int channel, int mode); 20384740dcSRalf Baechle extern void vdma_set_addr(int channel, long addr); 21384740dcSRalf Baechle extern void vdma_set_count(int channel, int count); 22384740dcSRalf Baechle extern int vdma_get_residue(int channel); 23384740dcSRalf Baechle extern int vdma_get_enable(int channel); 24384740dcSRalf Baechle 25384740dcSRalf Baechle /* 26384740dcSRalf Baechle * some definitions used by the driver functions 27384740dcSRalf Baechle */ 28384740dcSRalf Baechle #define VDMA_PAGESIZE 4096 29384740dcSRalf Baechle #define VDMA_PGTBL_ENTRIES 4096 30384740dcSRalf Baechle #define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES) 31384740dcSRalf Baechle #define VDMA_PAGE_EMPTY 0xff000000 32384740dcSRalf Baechle 33384740dcSRalf Baechle /* 34384740dcSRalf Baechle * Macros to get page no. and offset of a given address 35384740dcSRalf Baechle * Note that VDMA_PAGE() works for physical addresses only 36384740dcSRalf Baechle */ 37384740dcSRalf Baechle #define VDMA_PAGE(a) ((unsigned int)(a) >> 12) 38384740dcSRalf Baechle #define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1)) 39384740dcSRalf Baechle 40384740dcSRalf Baechle /* 41384740dcSRalf Baechle * VDMA pagetable entry description 42384740dcSRalf Baechle */ 43384740dcSRalf Baechle typedef volatile struct VDMA_PGTBL_ENTRY { 44384740dcSRalf Baechle unsigned int frame; /* physical frame no. */ 45384740dcSRalf Baechle unsigned int owner; /* owner of this entry (0=free) */ 46384740dcSRalf Baechle } VDMA_PGTBL_ENTRY; 47384740dcSRalf Baechle 48384740dcSRalf Baechle 49384740dcSRalf Baechle /* 50384740dcSRalf Baechle * DMA channel control registers 51384740dcSRalf Baechle * in the R4030 MCT_ADR chip 52384740dcSRalf Baechle */ 53384740dcSRalf Baechle #define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */ 54384740dcSRalf Baechle /* 0xE0000100,120,140... */ 55384740dcSRalf Baechle #define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ 56384740dcSRalf Baechle /* 0xE0000108,128,148... */ 57384740dcSRalf Baechle #define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */ 58384740dcSRalf Baechle /* 0xE0000110,130,150... */ 59384740dcSRalf Baechle #define JAZZ_R4030_CHNL_ADDR 0xE0000118 /* 8 DMA Channel Address Regs, */ 60384740dcSRalf Baechle /* 0xE0000118,138,158... */ 61384740dcSRalf Baechle 62384740dcSRalf Baechle /* channel enable register bits */ 63384740dcSRalf Baechle 64384740dcSRalf Baechle #define R4030_CHNL_ENABLE (1<<0) 65384740dcSRalf Baechle #define R4030_CHNL_WRITE (1<<1) 66384740dcSRalf Baechle #define R4030_TC_INTR (1<<8) 67384740dcSRalf Baechle #define R4030_MEM_INTR (1<<9) 68384740dcSRalf Baechle #define R4030_ADDR_INTR (1<<10) 69384740dcSRalf Baechle 70384740dcSRalf Baechle /* 71384740dcSRalf Baechle * Channel mode register bits 72384740dcSRalf Baechle */ 73384740dcSRalf Baechle #define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ 74384740dcSRalf Baechle #define R4030_MODE_ATIME_80 (1) 75384740dcSRalf Baechle #define R4030_MODE_ATIME_120 (2) 76384740dcSRalf Baechle #define R4030_MODE_ATIME_160 (3) 77384740dcSRalf Baechle #define R4030_MODE_ATIME_200 (4) 78384740dcSRalf Baechle #define R4030_MODE_ATIME_240 (5) 79384740dcSRalf Baechle #define R4030_MODE_ATIME_280 (6) 80384740dcSRalf Baechle #define R4030_MODE_ATIME_320 (7) 81384740dcSRalf Baechle #define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */ 82384740dcSRalf Baechle #define R4030_MODE_WIDTH_16 (2<<3) 83384740dcSRalf Baechle #define R4030_MODE_WIDTH_32 (3<<3) 84384740dcSRalf Baechle #define R4030_MODE_INTR_EN (1<<5) 85384740dcSRalf Baechle #define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ 86384740dcSRalf Baechle #define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ 87384740dcSRalf Baechle 88384740dcSRalf Baechle #endif /* _ASM_JAZZDMA_H */ 89