116216333SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * Galileo/Marvell GT641xx IRQ definitions. 4384740dcSRalf Baechle * 5ada8e951SYoichi Yuasa * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 6384740dcSRalf Baechle */ 7384740dcSRalf Baechle #ifndef _ASM_IRQ_GT641XX_H 8384740dcSRalf Baechle #define _ASM_IRQ_GT641XX_H 9384740dcSRalf Baechle 10384740dcSRalf Baechle #ifndef GT641XX_IRQ_BASE 11384740dcSRalf Baechle #define GT641XX_IRQ_BASE 8 12384740dcSRalf Baechle #endif 13384740dcSRalf Baechle 14384740dcSRalf Baechle #define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) 15384740dcSRalf Baechle #define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) 16384740dcSRalf Baechle #define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) 17384740dcSRalf Baechle #define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) 18384740dcSRalf Baechle #define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) 19384740dcSRalf Baechle #define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) 20384740dcSRalf Baechle #define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) 21384740dcSRalf Baechle #define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) 22384740dcSRalf Baechle #define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) 23384740dcSRalf Baechle #define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) 24384740dcSRalf Baechle #define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) 25384740dcSRalf Baechle #define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) 26384740dcSRalf Baechle #define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) 27384740dcSRalf Baechle #define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) 28384740dcSRalf Baechle #define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) 29384740dcSRalf Baechle #define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) 30384740dcSRalf Baechle #define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) 31384740dcSRalf Baechle #define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) 32384740dcSRalf Baechle #define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) 33384740dcSRalf Baechle #define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) 34384740dcSRalf Baechle #define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) 35384740dcSRalf Baechle #define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) 36384740dcSRalf Baechle #define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) 37384740dcSRalf Baechle #define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) 38384740dcSRalf Baechle #define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) 39384740dcSRalf Baechle #define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) 40384740dcSRalf Baechle #define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) 41384740dcSRalf Baechle #define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) 42384740dcSRalf Baechle #define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) 43384740dcSRalf Baechle 44384740dcSRalf Baechle extern void gt641xx_irq_dispatch(void); 45384740dcSRalf Baechle extern void gt641xx_irq_init(void); 46384740dcSRalf Baechle 47384740dcSRalf Baechle #endif /* _ASM_IRQ_GT641XX_H */ 48