1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle 7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle 8 */ 9 #ifndef _ASM_IRQ_H 10 #define _ASM_IRQ_H 11 12 #include <linux/linkage.h> 13 #include <linux/smp.h> 14 #include <linux/irqdomain.h> 15 16 #include <asm/mipsmtregs.h> 17 18 #include <irq.h> 19 20 #ifdef CONFIG_I8259 21 static inline int irq_canonicalize(int irq) 22 { 23 return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); 24 } 25 #else 26 #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ 27 #endif 28 29 #ifdef CONFIG_MIPS_MT_SMTC 30 31 struct irqaction; 32 33 extern unsigned long irq_hwmask[]; 34 extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, 35 unsigned long hwmask); 36 37 static inline void smtc_im_ack_irq(unsigned int irq) 38 { 39 if (irq_hwmask[irq] & ST0_IM) 40 set_c0_status(irq_hwmask[irq] & ST0_IM); 41 } 42 43 #else 44 45 static inline void smtc_im_ack_irq(unsigned int irq) 46 { 47 } 48 49 #endif /* CONFIG_MIPS_MT_SMTC */ 50 51 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 52 #include <linux/cpumask.h> 53 54 extern int plat_set_irq_affinity(struct irq_data *d, 55 const struct cpumask *affinity, bool force); 56 extern void smtc_forward_irq(struct irq_data *d); 57 58 /* 59 * IRQ affinity hook invoked at the beginning of interrupt dispatch 60 * if option is enabled. 61 * 62 * Up through Linux 2.6.22 (at least) cpumask operations are very 63 * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity 64 * used a "fast path" per-IRQ-descriptor cache of affinity information 65 * to reduce latency. As there is a project afoot to optimize the 66 * cpumask implementations, this version is optimistically assuming 67 * that cpumask.h macro overhead is reasonable during interrupt dispatch. 68 */ 69 static inline int handle_on_other_cpu(unsigned int irq) 70 { 71 struct irq_data *d = irq_get_irq_data(irq); 72 73 if (cpumask_test_cpu(smp_processor_id(), d->affinity)) 74 return 0; 75 smtc_forward_irq(d); 76 return 1; 77 } 78 79 #else /* Not doing SMTC affinity */ 80 81 static inline int handle_on_other_cpu(unsigned int irq) { return 0; } 82 83 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 84 85 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP 86 87 static inline void smtc_im_backstop(unsigned int irq) 88 { 89 if (irq_hwmask[irq] & 0x0000ff00) 90 write_c0_tccontext(read_c0_tccontext() & 91 ~(irq_hwmask[irq] & 0x0000ff00)); 92 } 93 94 /* 95 * Clear interrupt mask handling "backstop" if irq_hwmask 96 * entry so indicates. This implies that the ack() or end() 97 * functions will take over re-enabling the low-level mask. 98 * Otherwise it will be done on return from exception. 99 */ 100 static inline int smtc_handle_on_other_cpu(unsigned int irq) 101 { 102 int ret = handle_on_other_cpu(irq); 103 104 if (!ret) 105 smtc_im_backstop(irq); 106 return ret; 107 } 108 109 #else 110 111 static inline void smtc_im_backstop(unsigned int irq) { } 112 static inline int smtc_handle_on_other_cpu(unsigned int irq) 113 { 114 return handle_on_other_cpu(irq); 115 } 116 117 #endif 118 119 extern void do_IRQ(unsigned int irq); 120 121 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 122 123 extern void do_IRQ_no_affinity(unsigned int irq); 124 125 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 126 127 extern void arch_init_irq(void); 128 extern void spurious_interrupt(void); 129 130 extern int allocate_irqno(void); 131 extern void alloc_legacy_irqno(void); 132 extern void free_irqno(unsigned int irq); 133 134 /* 135 * Before R2 the timer and performance counter interrupts were both fixed to 136 * IE7. Since R2 their number has to be read from the c0_intctl register. 137 */ 138 #define CP0_LEGACY_COMPARE_IRQ 7 139 #define CP0_LEGACY_PERFCNT_IRQ 7 140 141 extern int cp0_compare_irq; 142 extern int cp0_compare_irq_shift; 143 extern int cp0_perfcount_irq; 144 145 #endif /* _ASM_IRQ_H */ 146