xref: /openbmc/linux/arch/mips/include/asm/irq.h (revision b737eecd)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
7  * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
8  */
9 #ifndef _ASM_IRQ_H
10 #define _ASM_IRQ_H
11 
12 #include <linux/linkage.h>
13 #include <linux/smp.h>
14 #include <linux/irqdomain.h>
15 
16 #include <asm/mipsmtregs.h>
17 
18 #include <irq.h>
19 
20 #define IRQ_STACK_SIZE			THREAD_SIZE
21 #define IRQ_STACK_START			(IRQ_STACK_SIZE - 16)
22 
23 extern void __init init_IRQ(void);
24 extern void *irq_stack[NR_CPUS];
25 
26 /*
27  * The highest address on the IRQ stack contains a dummy frame put down in
28  * genex.S (handle_int & except_vec_vi_handler) which is structured as follows:
29  *
30  *   top ------------
31  *       | task sp  | <- irq_stack[cpu] + IRQ_STACK_START
32  *       ------------
33  *       |          | <- First frame of IRQ context
34  *       ------------
35  *
36  * task sp holds a copy of the task stack pointer where the struct pt_regs
37  * from exception entry can be found.
38  */
39 
40 static inline bool on_irq_stack(int cpu, unsigned long sp)
41 {
42 	unsigned long low = (unsigned long)irq_stack[cpu];
43 	unsigned long high = low + IRQ_STACK_SIZE;
44 
45 	return (low <= sp && sp <= high);
46 }
47 
48 #ifdef CONFIG_I8259
49 static inline int irq_canonicalize(int irq)
50 {
51 	return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
52 }
53 #else
54 #define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
55 #endif
56 
57 asmlinkage void plat_irq_dispatch(void);
58 
59 extern void do_IRQ(unsigned int irq);
60 
61 extern void arch_init_irq(void);
62 extern void spurious_interrupt(void);
63 
64 extern int allocate_irqno(void);
65 extern void alloc_legacy_irqno(void);
66 extern void free_irqno(unsigned int irq);
67 
68 /*
69  * Before R2 the timer and performance counter interrupts were both fixed to
70  * IE7.	 Since R2 their number has to be read from the c0_intctl register.
71  */
72 #define CP0_LEGACY_COMPARE_IRQ 7
73 #define CP0_LEGACY_PERFCNT_IRQ 7
74 
75 extern int cp0_compare_irq;
76 extern int cp0_compare_irq_shift;
77 extern int cp0_perfcount_irq;
78 extern int cp0_fdc_irq;
79 
80 extern int get_c0_fdc_int(void);
81 
82 void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
83 				    bool exclude_self);
84 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
85 
86 #endif /* _ASM_IRQ_H */
87