xref: /openbmc/linux/arch/mips/include/asm/irq.h (revision a9ebfc40)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
7  * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
8  */
9 #ifndef _ASM_IRQ_H
10 #define _ASM_IRQ_H
11 
12 #include <linux/linkage.h>
13 #include <linux/smp.h>
14 
15 #include <asm/mipsmtregs.h>
16 
17 #include <irq.h>
18 
19 #define IRQ_STACK_SIZE			THREAD_SIZE
20 #define IRQ_STACK_START			(IRQ_STACK_SIZE - 16)
21 
22 extern void *irq_stack[NR_CPUS];
23 
24 /*
25  * The highest address on the IRQ stack contains a dummy frame put down in
26  * genex.S (handle_int & except_vec_vi_handler) which is structured as follows:
27  *
28  *   top ------------
29  *       | task sp  | <- irq_stack[cpu] + IRQ_STACK_START
30  *       ------------
31  *       |          | <- First frame of IRQ context
32  *       ------------
33  *
34  * task sp holds a copy of the task stack pointer where the struct pt_regs
35  * from exception entry can be found.
36  */
37 
38 static inline bool on_irq_stack(int cpu, unsigned long sp)
39 {
40 	unsigned long low = (unsigned long)irq_stack[cpu];
41 	unsigned long high = low + IRQ_STACK_SIZE;
42 
43 	return (low <= sp && sp <= high);
44 }
45 
46 #ifdef CONFIG_I8259
47 static inline int irq_canonicalize(int irq)
48 {
49 	return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
50 }
51 #else
52 #define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
53 #endif
54 
55 asmlinkage void plat_irq_dispatch(void);
56 
57 extern void do_IRQ(unsigned int irq);
58 
59 struct irq_domain;
60 extern void do_domain_IRQ(struct irq_domain *domain, unsigned int irq);
61 
62 extern void arch_init_irq(void);
63 extern void spurious_interrupt(void);
64 
65 /*
66  * Before R2 the timer and performance counter interrupts were both fixed to
67  * IE7.	 Since R2 their number has to be read from the c0_intctl register.
68  */
69 #define CP0_LEGACY_COMPARE_IRQ 7
70 #define CP0_LEGACY_PERFCNT_IRQ 7
71 
72 extern int cp0_compare_irq;
73 extern int cp0_compare_irq_shift;
74 extern int cp0_perfcount_irq;
75 extern int cp0_fdc_irq;
76 
77 extern int get_c0_fdc_int(void);
78 
79 void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
80 				    int exclude_cpu);
81 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
82 
83 #endif /* _ASM_IRQ_H */
84