xref: /openbmc/linux/arch/mips/include/asm/irq.h (revision 9dbbc3b9)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
7  * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
8  */
9 #ifndef _ASM_IRQ_H
10 #define _ASM_IRQ_H
11 
12 #include <linux/linkage.h>
13 #include <linux/smp.h>
14 
15 #include <asm/mipsmtregs.h>
16 
17 #include <irq.h>
18 
19 #define IRQ_STACK_SIZE			THREAD_SIZE
20 #define IRQ_STACK_START			(IRQ_STACK_SIZE - 16)
21 
22 extern void __init init_IRQ(void);
23 extern void *irq_stack[NR_CPUS];
24 
25 /*
26  * The highest address on the IRQ stack contains a dummy frame put down in
27  * genex.S (handle_int & except_vec_vi_handler) which is structured as follows:
28  *
29  *   top ------------
30  *       | task sp  | <- irq_stack[cpu] + IRQ_STACK_START
31  *       ------------
32  *       |          | <- First frame of IRQ context
33  *       ------------
34  *
35  * task sp holds a copy of the task stack pointer where the struct pt_regs
36  * from exception entry can be found.
37  */
38 
39 static inline bool on_irq_stack(int cpu, unsigned long sp)
40 {
41 	unsigned long low = (unsigned long)irq_stack[cpu];
42 	unsigned long high = low + IRQ_STACK_SIZE;
43 
44 	return (low <= sp && sp <= high);
45 }
46 
47 #ifdef CONFIG_I8259
48 static inline int irq_canonicalize(int irq)
49 {
50 	return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
51 }
52 #else
53 #define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
54 #endif
55 
56 asmlinkage void plat_irq_dispatch(void);
57 
58 extern void do_IRQ(unsigned int irq);
59 
60 extern void arch_init_irq(void);
61 extern void spurious_interrupt(void);
62 
63 extern int allocate_irqno(void);
64 extern void alloc_legacy_irqno(void);
65 extern void free_irqno(unsigned int irq);
66 
67 /*
68  * Before R2 the timer and performance counter interrupts were both fixed to
69  * IE7.	 Since R2 their number has to be read from the c0_intctl register.
70  */
71 #define CP0_LEGACY_COMPARE_IRQ 7
72 #define CP0_LEGACY_PERFCNT_IRQ 7
73 
74 extern int cp0_compare_irq;
75 extern int cp0_compare_irq_shift;
76 extern int cp0_perfcount_irq;
77 extern int cp0_fdc_irq;
78 
79 extern int get_c0_fdc_int(void);
80 
81 void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
82 				    bool exclude_self);
83 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
84 
85 #endif /* _ASM_IRQ_H */
86