1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2000 Harald Koerfgen
7  */
8 
9 #ifndef __ASM_IP32_INTS_H
10 #define __ASM_IP32_INTS_H
11 
12 #include <asm/irq.h>
13 
14 /*
15  * This list reflects the assignment of interrupt numbers to
16  * interrupting events.	 Order is fairly irrelevant to handling
17  * priority.  This differs from irix.
18  */
19 
20 enum ip32_irq_no {
21 	/*
22 	 * CPU interrupts are 0 ... 7
23 	 */
24 
25 	CRIME_IRQ_BASE			= MIPS_CPU_IRQ_BASE + 8,
26 
27 	/*
28 	 * MACE
29 	 */
30 	MACE_VID_IN1_IRQ		= CRIME_IRQ_BASE,
31 	MACE_VID_IN2_IRQ,
32 	MACE_VID_OUT_IRQ,
33 	MACE_ETHERNET_IRQ,
34 	/* SUPERIO, MISC, and AUDIO are MACEISA */
35 	__MACE_SUPERIO,
36 	__MACE_MISC,
37 	__MACE_AUDIO,
38 	MACE_PCI_BRIDGE_IRQ,
39 
40 	/*
41 	 * MACEPCI
42 	 */
43 	MACEPCI_SCSI0_IRQ,
44 	MACEPCI_SCSI1_IRQ,
45 	MACEPCI_SLOT0_IRQ,
46 	MACEPCI_SLOT1_IRQ,
47 	MACEPCI_SLOT2_IRQ,
48 	MACEPCI_SHARED0_IRQ,
49 	MACEPCI_SHARED1_IRQ,
50 	MACEPCI_SHARED2_IRQ,
51 
52 	/*
53 	 * CRIME
54 	 */
55 	CRIME_GBE0_IRQ,
56 	CRIME_GBE1_IRQ,
57 	CRIME_GBE2_IRQ,
58 	CRIME_GBE3_IRQ,
59 	CRIME_CPUERR_IRQ,
60 	CRIME_MEMERR_IRQ,
61 	CRIME_RE_EMPTY_E_IRQ,
62 	CRIME_RE_FULL_E_IRQ,
63 	CRIME_RE_IDLE_E_IRQ,
64 	CRIME_RE_EMPTY_L_IRQ,
65 	CRIME_RE_FULL_L_IRQ,
66 	CRIME_RE_IDLE_L_IRQ,
67 	CRIME_SOFT0_IRQ,
68 	CRIME_SOFT1_IRQ,
69 	CRIME_SOFT2_IRQ,
70 	CRIME_SYSCORERR_IRQ		= CRIME_SOFT2_IRQ,
71 	CRIME_VICE_IRQ,
72 
73 	/*
74 	 * MACEISA
75 	 */
76 	MACEISA_AUDIO_SW_IRQ,
77 	MACEISA_AUDIO_SC_IRQ,
78 	MACEISA_AUDIO1_DMAT_IRQ,
79 	MACEISA_AUDIO1_OF_IRQ,
80 	MACEISA_AUDIO2_DMAT_IRQ,
81 	MACEISA_AUDIO2_MERR_IRQ,
82 	MACEISA_AUDIO3_DMAT_IRQ,
83 	MACEISA_AUDIO3_MERR_IRQ,
84 	MACEISA_RTC_IRQ,
85 	MACEISA_KEYB_IRQ,
86 	/* MACEISA_KEYB_POLL is not an IRQ */
87 	__MACEISA_KEYB_POLL,
88 	MACEISA_MOUSE_IRQ,
89 	/* MACEISA_MOUSE_POLL is not an IRQ */
90 	__MACEISA_MOUSE_POLL,
91 	MACEISA_TIMER0_IRQ,
92 	MACEISA_TIMER1_IRQ,
93 	MACEISA_TIMER2_IRQ,
94 	MACEISA_PARALLEL_IRQ,
95 	MACEISA_PAR_CTXA_IRQ,
96 	MACEISA_PAR_CTXB_IRQ,
97 	MACEISA_PAR_MERR_IRQ,
98 	MACEISA_SERIAL1_IRQ,
99 	MACEISA_SERIAL1_TDMAT_IRQ,
100 	MACEISA_SERIAL1_TDMAPR_IRQ,
101 	MACEISA_SERIAL1_TDMAME_IRQ,
102 	MACEISA_SERIAL1_RDMAT_IRQ,
103 	MACEISA_SERIAL1_RDMAOR_IRQ,
104 	MACEISA_SERIAL2_IRQ,
105 	MACEISA_SERIAL2_TDMAT_IRQ,
106 	MACEISA_SERIAL2_TDMAPR_IRQ,
107 	MACEISA_SERIAL2_TDMAME_IRQ,
108 	MACEISA_SERIAL2_RDMAT_IRQ,
109 	MACEISA_SERIAL2_RDMAOR_IRQ,
110 
111 	IP32_IRQ_MAX			= MACEISA_SERIAL2_RDMAOR_IRQ
112 };
113 
114 #endif /* __ASM_IP32_INTS_H */
115