1 /* 2 * include/asm-mips/i8259.h 3 * 4 * i8259A interrupt definitions. 5 * 6 * Copyright (C) 2003 Maciej W. Rozycki 7 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #ifndef _ASM_I8259_H 15 #define _ASM_I8259_H 16 17 #include <linux/compiler.h> 18 #include <linux/spinlock.h> 19 20 #include <asm/io.h> 21 #include <irq.h> 22 23 /* i8259A PIC registers */ 24 #define PIC_MASTER_CMD 0x20 25 #define PIC_MASTER_IMR 0x21 26 #define PIC_MASTER_ISR PIC_MASTER_CMD 27 #define PIC_MASTER_POLL PIC_MASTER_ISR 28 #define PIC_MASTER_OCW3 PIC_MASTER_ISR 29 #define PIC_SLAVE_CMD 0xa0 30 #define PIC_SLAVE_IMR 0xa1 31 32 /* i8259A PIC related value */ 33 #define PIC_CASCADE_IR 2 34 #define MASTER_ICW4_DEFAULT 0x01 35 #define SLAVE_ICW4_DEFAULT 0x01 36 #define PIC_ICW4_AEOI 2 37 38 extern raw_spinlock_t i8259A_lock; 39 40 extern void make_8259A_irq(unsigned int irq); 41 42 extern void init_i8259_irqs(void); 43 44 /** 45 * i8159_set_poll() - Override the i8259 polling function 46 * @poll: pointer to platform-specific polling function 47 * 48 * Call this to override the generic i8259 polling function, which directly 49 * accesses i8259 registers, with a platform specific one which may be faster 50 * in cases where hardware provides a more optimal means of polling for an 51 * interrupt. 52 */ 53 extern void i8259_set_poll(int (*poll)(void)); 54 55 /* 56 * Do the traditional i8259 interrupt polling thing. This is for the few 57 * cases where no better interrupt acknowledge method is available and we 58 * absolutely must touch the i8259. 59 */ 60 static inline int i8259_irq(void) 61 { 62 int irq; 63 64 raw_spin_lock(&i8259A_lock); 65 66 /* Perform an interrupt acknowledge cycle on controller 1. */ 67 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ 68 irq = inb(PIC_MASTER_CMD) & 7; 69 if (irq == PIC_CASCADE_IR) { 70 /* 71 * Interrupt is cascaded so perform interrupt 72 * acknowledge on controller 2. 73 */ 74 outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */ 75 irq = (inb(PIC_SLAVE_CMD) & 7) + 8; 76 } 77 78 if (unlikely(irq == 7)) { 79 /* 80 * This may be a spurious interrupt. 81 * 82 * Read the interrupt status register (ISR). If the most 83 * significant bit is not set then there is no valid 84 * interrupt. 85 */ 86 outb(0x0B, PIC_MASTER_ISR); /* ISR register */ 87 if(~inb(PIC_MASTER_ISR) & 0x80) 88 irq = -1; 89 } 90 91 raw_spin_unlock(&i8259A_lock); 92 93 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; 94 } 95 96 #endif /* _ASM_I8259_H */ 97