xref: /openbmc/linux/arch/mips/include/asm/futex.h (revision fd7710cb)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)
7  */
8 #ifndef _ASM_FUTEX_H
9 #define _ASM_FUTEX_H
10 
11 #ifdef __KERNEL__
12 
13 #include <linux/futex.h>
14 #include <linux/uaccess.h>
15 #include <asm/asm-eva.h>
16 #include <asm/barrier.h>
17 #include <asm/compiler.h>
18 #include <asm/errno.h>
19 #include <asm/sync.h>
20 #include <asm/war.h>
21 
22 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)		\
23 {									\
24 	if (cpu_has_llsc && R10000_LLSC_WAR) {				\
25 		__asm__ __volatile__(					\
26 		"	.set	push				\n"	\
27 		"	.set	noat				\n"	\
28 		"	.set	push				\n"	\
29 		"	.set	arch=r4000			\n"	\
30 		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
31 		"	.set	pop				\n"	\
32 		"	" insn	"				\n"	\
33 		"	.set	arch=r4000			\n"	\
34 		"2:	sc	$1, %2				\n"	\
35 		"	beqzl	$1, 1b				\n"	\
36 		__stringify(__WEAK_LLSC_MB) "			\n"	\
37 		"3:						\n"	\
38 		"	.insn					\n"	\
39 		"	.set	pop				\n"	\
40 		"	.section .fixup,\"ax\"			\n"	\
41 		"4:	li	%0, %6				\n"	\
42 		"	j	3b				\n"	\
43 		"	.previous				\n"	\
44 		"	.section __ex_table,\"a\"		\n"	\
45 		"	"__UA_ADDR "\t1b, 4b			\n"	\
46 		"	"__UA_ADDR "\t2b, 4b			\n"	\
47 		"	.previous				\n"	\
48 		: "=r" (ret), "=&r" (oldval),				\
49 		  "=" GCC_OFF_SMALL_ASM() (*uaddr)				\
50 		: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg),	\
51 		  "i" (-EFAULT)						\
52 		: "memory");						\
53 	} else if (cpu_has_llsc) {					\
54 		__asm__ __volatile__(					\
55 		"	.set	push				\n"	\
56 		"	.set	noat				\n"	\
57 		"	.set	push				\n"	\
58 		"	.set	"MIPS_ISA_ARCH_LEVEL"		\n"	\
59 		"	" __SYNC(full, loongson3_war) "		\n"	\
60 		"1:	"user_ll("%1", "%4")" # __futex_atomic_op\n"	\
61 		"	.set	pop				\n"	\
62 		"	" insn	"				\n"	\
63 		"	.set	"MIPS_ISA_ARCH_LEVEL"		\n"	\
64 		"2:	"user_sc("$1", "%2")"			\n"	\
65 		"	beqz	$1, 1b				\n"	\
66 		__stringify(__WEAK_LLSC_MB) "			\n"	\
67 		"3:						\n"	\
68 		"	.insn					\n"	\
69 		"	.set	pop				\n"	\
70 		"	.section .fixup,\"ax\"			\n"	\
71 		"4:	li	%0, %6				\n"	\
72 		"	j	3b				\n"	\
73 		"	.previous				\n"	\
74 		"	.section __ex_table,\"a\"		\n"	\
75 		"	"__UA_ADDR "\t1b, 4b			\n"	\
76 		"	"__UA_ADDR "\t2b, 4b			\n"	\
77 		"	.previous				\n"	\
78 		: "=r" (ret), "=&r" (oldval),				\
79 		  "=" GCC_OFF_SMALL_ASM() (*uaddr)				\
80 		: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg),	\
81 		  "i" (-EFAULT)						\
82 		: "memory");						\
83 	} else								\
84 		ret = -ENOSYS;						\
85 }
86 
87 static inline int
88 arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
89 {
90 	int oldval = 0, ret;
91 
92 	pagefault_disable();
93 
94 	switch (op) {
95 	case FUTEX_OP_SET:
96 		__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
97 		break;
98 
99 	case FUTEX_OP_ADD:
100 		__futex_atomic_op("addu $1, %1, %z5",
101 				  ret, oldval, uaddr, oparg);
102 		break;
103 	case FUTEX_OP_OR:
104 		__futex_atomic_op("or	$1, %1, %z5",
105 				  ret, oldval, uaddr, oparg);
106 		break;
107 	case FUTEX_OP_ANDN:
108 		__futex_atomic_op("and	$1, %1, %z5",
109 				  ret, oldval, uaddr, ~oparg);
110 		break;
111 	case FUTEX_OP_XOR:
112 		__futex_atomic_op("xor	$1, %1, %z5",
113 				  ret, oldval, uaddr, oparg);
114 		break;
115 	default:
116 		ret = -ENOSYS;
117 	}
118 
119 	pagefault_enable();
120 
121 	if (!ret)
122 		*oval = oldval;
123 
124 	return ret;
125 }
126 
127 static inline int
128 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
129 			      u32 oldval, u32 newval)
130 {
131 	int ret = 0;
132 	u32 val;
133 
134 	if (!access_ok(uaddr, sizeof(u32)))
135 		return -EFAULT;
136 
137 	if (cpu_has_llsc && R10000_LLSC_WAR) {
138 		__asm__ __volatile__(
139 		"# futex_atomic_cmpxchg_inatomic			\n"
140 		"	.set	push					\n"
141 		"	.set	noat					\n"
142 		"	.set	push					\n"
143 		"	.set	arch=r4000				\n"
144 		"1:	ll	%1, %3					\n"
145 		"	bne	%1, %z4, 3f				\n"
146 		"	.set	pop					\n"
147 		"	move	$1, %z5					\n"
148 		"	.set	arch=r4000				\n"
149 		"2:	sc	$1, %2					\n"
150 		"	beqzl	$1, 1b					\n"
151 		__stringify(__WEAK_LLSC_MB) "				\n"
152 		"3:							\n"
153 		"	.insn						\n"
154 		"	.set	pop					\n"
155 		"	.section .fixup,\"ax\"				\n"
156 		"4:	li	%0, %6					\n"
157 		"	j	3b					\n"
158 		"	.previous					\n"
159 		"	.section __ex_table,\"a\"			\n"
160 		"	"__UA_ADDR "\t1b, 4b				\n"
161 		"	"__UA_ADDR "\t2b, 4b				\n"
162 		"	.previous					\n"
163 		: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
164 		: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
165 		  "i" (-EFAULT)
166 		: "memory");
167 	} else if (cpu_has_llsc) {
168 		__asm__ __volatile__(
169 		"# futex_atomic_cmpxchg_inatomic			\n"
170 		"	.set	push					\n"
171 		"	.set	noat					\n"
172 		"	.set	push					\n"
173 		"	.set	"MIPS_ISA_ARCH_LEVEL"			\n"
174 		"	" __SYNC(full, loongson3_war) "			\n"
175 		"1:	"user_ll("%1", "%3")"				\n"
176 		"	bne	%1, %z4, 3f				\n"
177 		"	.set	pop					\n"
178 		"	move	$1, %z5					\n"
179 		"	.set	"MIPS_ISA_ARCH_LEVEL"			\n"
180 		"2:	"user_sc("$1", "%2")"				\n"
181 		"	beqz	$1, 1b					\n"
182 		"3:	" __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
183 		"	.insn						\n"
184 		"	.set	pop					\n"
185 		"	.section .fixup,\"ax\"				\n"
186 		"4:	li	%0, %6					\n"
187 		"	j	3b					\n"
188 		"	.previous					\n"
189 		"	.section __ex_table,\"a\"			\n"
190 		"	"__UA_ADDR "\t1b, 4b				\n"
191 		"	"__UA_ADDR "\t2b, 4b				\n"
192 		"	.previous					\n"
193 		: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
194 		: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
195 		  "i" (-EFAULT)
196 		: "memory");
197 	} else
198 		return -ENOSYS;
199 
200 	*uval = val;
201 	return ret;
202 }
203 
204 #endif
205 #endif /* _ASM_FUTEX_H */
206