1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org) 7 */ 8 #ifndef _ASM_FUTEX_H 9 #define _ASM_FUTEX_H 10 11 #ifdef __KERNEL__ 12 13 #include <linux/futex.h> 14 #include <linux/uaccess.h> 15 #include <asm/asm-eva.h> 16 #include <asm/barrier.h> 17 #include <asm/compiler.h> 18 #include <asm/errno.h> 19 #include <asm/sync.h> 20 #include <asm/war.h> 21 22 #define arch_futex_atomic_op_inuser arch_futex_atomic_op_inuser 23 #define futex_atomic_cmpxchg_inatomic futex_atomic_cmpxchg_inatomic 24 #include <asm-generic/futex.h> 25 26 #define __futex_atomic_op(op, insn, ret, oldval, uaddr, oparg) \ 27 { \ 28 if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { \ 29 __asm__ __volatile__( \ 30 " .set push \n" \ 31 " .set noat \n" \ 32 " .set push \n" \ 33 " .set arch=r4000 \n" \ 34 "1: ll %1, %4 # __futex_atomic_op \n" \ 35 " .set pop \n" \ 36 " " insn " \n" \ 37 " .set arch=r4000 \n" \ 38 "2: sc $1, %2 \n" \ 39 " beqzl $1, 1b \n" \ 40 __stringify(__WEAK_LLSC_MB) " \n" \ 41 "3: \n" \ 42 " .insn \n" \ 43 " .set pop \n" \ 44 " .section .fixup,\"ax\" \n" \ 45 "4: li %0, %6 \n" \ 46 " j 3b \n" \ 47 " .previous \n" \ 48 " .section __ex_table,\"a\" \n" \ 49 " "__UA_ADDR "\t1b, 4b \n" \ 50 " "__UA_ADDR "\t2b, 4b \n" \ 51 " .previous \n" \ 52 : "=r" (ret), "=&r" (oldval), \ 53 "=" GCC_OFF_SMALL_ASM() (*uaddr) \ 54 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \ 55 "i" (-EFAULT) \ 56 : "memory"); \ 57 } else if (cpu_has_llsc) { \ 58 __asm__ __volatile__( \ 59 " .set push \n" \ 60 " .set noat \n" \ 61 " .set push \n" \ 62 " .set "MIPS_ISA_ARCH_LEVEL" \n" \ 63 " " __SYNC(full, loongson3_war) " \n" \ 64 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \ 65 " .set pop \n" \ 66 " " insn " \n" \ 67 " .set "MIPS_ISA_ARCH_LEVEL" \n" \ 68 "2: "user_sc("$1", "%2")" \n" \ 69 " beqz $1, 1b \n" \ 70 __stringify(__WEAK_LLSC_MB) " \n" \ 71 "3: \n" \ 72 " .insn \n" \ 73 " .set pop \n" \ 74 " .section .fixup,\"ax\" \n" \ 75 "4: li %0, %6 \n" \ 76 " j 3b \n" \ 77 " .previous \n" \ 78 " .section __ex_table,\"a\" \n" \ 79 " "__UA_ADDR "\t1b, 4b \n" \ 80 " "__UA_ADDR "\t2b, 4b \n" \ 81 " .previous \n" \ 82 : "=r" (ret), "=&r" (oldval), \ 83 "=" GCC_OFF_SMALL_ASM() (*uaddr) \ 84 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \ 85 "i" (-EFAULT) \ 86 : "memory"); \ 87 } else { \ 88 /* fallback for non-SMP */ \ 89 ret = futex_atomic_op_inuser_local(op, oparg, oval, uaddr); \ 90 } \ 91 } 92 93 static inline int 94 arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) 95 { 96 int oldval = 0, ret; 97 98 if (!access_ok(uaddr, sizeof(u32))) 99 return -EFAULT; 100 101 switch (op) { 102 case FUTEX_OP_SET: 103 __futex_atomic_op(op, "move $1, %z5", ret, oldval, uaddr, oparg); 104 break; 105 106 case FUTEX_OP_ADD: 107 __futex_atomic_op(op, "addu $1, %1, %z5", 108 ret, oldval, uaddr, oparg); 109 break; 110 case FUTEX_OP_OR: 111 __futex_atomic_op(op, "or $1, %1, %z5", 112 ret, oldval, uaddr, oparg); 113 break; 114 case FUTEX_OP_ANDN: 115 __futex_atomic_op(op, "and $1, %1, %z5", 116 ret, oldval, uaddr, ~oparg); 117 break; 118 case FUTEX_OP_XOR: 119 __futex_atomic_op(op, "xor $1, %1, %z5", 120 ret, oldval, uaddr, oparg); 121 break; 122 default: 123 ret = -ENOSYS; 124 } 125 126 if (!ret) 127 *oval = oldval; 128 129 return ret; 130 } 131 132 static inline int 133 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, 134 u32 oldval, u32 newval) 135 { 136 int ret = 0; 137 u32 val; 138 139 if (!access_ok(uaddr, sizeof(u32))) 140 return -EFAULT; 141 142 if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { 143 __asm__ __volatile__( 144 "# futex_atomic_cmpxchg_inatomic \n" 145 " .set push \n" 146 " .set noat \n" 147 " .set push \n" 148 " .set arch=r4000 \n" 149 "1: ll %1, %3 \n" 150 " bne %1, %z4, 3f \n" 151 " .set pop \n" 152 " move $1, %z5 \n" 153 " .set arch=r4000 \n" 154 "2: sc $1, %2 \n" 155 " beqzl $1, 1b \n" 156 __stringify(__WEAK_LLSC_MB) " \n" 157 "3: \n" 158 " .insn \n" 159 " .set pop \n" 160 " .section .fixup,\"ax\" \n" 161 "4: li %0, %6 \n" 162 " j 3b \n" 163 " .previous \n" 164 " .section __ex_table,\"a\" \n" 165 " "__UA_ADDR "\t1b, 4b \n" 166 " "__UA_ADDR "\t2b, 4b \n" 167 " .previous \n" 168 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr) 169 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval), 170 "i" (-EFAULT) 171 : "memory"); 172 } else if (cpu_has_llsc) { 173 __asm__ __volatile__( 174 "# futex_atomic_cmpxchg_inatomic \n" 175 " .set push \n" 176 " .set noat \n" 177 " .set push \n" 178 " .set "MIPS_ISA_ARCH_LEVEL" \n" 179 " " __SYNC(full, loongson3_war) " \n" 180 "1: "user_ll("%1", "%3")" \n" 181 " bne %1, %z4, 3f \n" 182 " .set pop \n" 183 " move $1, %z5 \n" 184 " .set "MIPS_ISA_ARCH_LEVEL" \n" 185 "2: "user_sc("$1", "%2")" \n" 186 " beqz $1, 1b \n" 187 "3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n" 188 " .insn \n" 189 " .set pop \n" 190 " .section .fixup,\"ax\" \n" 191 "4: li %0, %6 \n" 192 " j 3b \n" 193 " .previous \n" 194 " .section __ex_table,\"a\" \n" 195 " "__UA_ADDR "\t1b, 4b \n" 196 " "__UA_ADDR "\t2b, 4b \n" 197 " .previous \n" 198 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr) 199 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval), 200 "i" (-EFAULT) 201 : "memory"); 202 } else { 203 return futex_atomic_cmpxchg_inatomic_local(uval, uaddr, oldval, newval); 204 } 205 206 *uval = val; 207 return ret; 208 } 209 210 #endif 211 #endif /* _ASM_FUTEX_H */ 212