1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org) 7 */ 8 #ifndef _ASM_FUTEX_H 9 #define _ASM_FUTEX_H 10 11 #ifdef __KERNEL__ 12 13 #include <linux/futex.h> 14 #include <linux/uaccess.h> 15 #include <asm/asm-eva.h> 16 #include <asm/barrier.h> 17 #include <asm/errno.h> 18 #include <asm/war.h> 19 20 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 21 { \ 22 if (cpu_has_llsc && R10000_LLSC_WAR) { \ 23 __asm__ __volatile__( \ 24 " .set push \n" \ 25 " .set noat \n" \ 26 " .set mips3 \n" \ 27 "1: ll %1, %4 # __futex_atomic_op \n" \ 28 " .set mips0 \n" \ 29 " " insn " \n" \ 30 " .set mips3 \n" \ 31 "2: sc $1, %2 \n" \ 32 " beqzl $1, 1b \n" \ 33 __WEAK_LLSC_MB \ 34 "3: \n" \ 35 " .set pop \n" \ 36 " .set mips0 \n" \ 37 " .section .fixup,\"ax\" \n" \ 38 "4: li %0, %6 \n" \ 39 " j 3b \n" \ 40 " .previous \n" \ 41 " .section __ex_table,\"a\" \n" \ 42 " "__UA_ADDR "\t1b, 4b \n" \ 43 " "__UA_ADDR "\t2b, 4b \n" \ 44 " .previous \n" \ 45 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ 46 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ 47 : "memory"); \ 48 } else if (cpu_has_llsc) { \ 49 __asm__ __volatile__( \ 50 " .set push \n" \ 51 " .set noat \n" \ 52 " .set mips3 \n" \ 53 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \ 54 " .set mips0 \n" \ 55 " " insn " \n" \ 56 " .set mips3 \n" \ 57 "2: "user_sc("$1", "%2")" \n" \ 58 " beqz $1, 1b \n" \ 59 __WEAK_LLSC_MB \ 60 "3: \n" \ 61 " .set pop \n" \ 62 " .set mips0 \n" \ 63 " .section .fixup,\"ax\" \n" \ 64 "4: li %0, %6 \n" \ 65 " j 3b \n" \ 66 " .previous \n" \ 67 " .section __ex_table,\"a\" \n" \ 68 " "__UA_ADDR "\t1b, 4b \n" \ 69 " "__UA_ADDR "\t2b, 4b \n" \ 70 " .previous \n" \ 71 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ 72 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ 73 : "memory"); \ 74 } else \ 75 ret = -ENOSYS; \ 76 } 77 78 static inline int 79 futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) 80 { 81 int op = (encoded_op >> 28) & 7; 82 int cmp = (encoded_op >> 24) & 15; 83 int oparg = (encoded_op << 8) >> 20; 84 int cmparg = (encoded_op << 20) >> 20; 85 int oldval = 0, ret; 86 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 87 oparg = 1 << oparg; 88 89 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32))) 90 return -EFAULT; 91 92 pagefault_disable(); 93 94 switch (op) { 95 case FUTEX_OP_SET: 96 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg); 97 break; 98 99 case FUTEX_OP_ADD: 100 __futex_atomic_op("addu $1, %1, %z5", 101 ret, oldval, uaddr, oparg); 102 break; 103 case FUTEX_OP_OR: 104 __futex_atomic_op("or $1, %1, %z5", 105 ret, oldval, uaddr, oparg); 106 break; 107 case FUTEX_OP_ANDN: 108 __futex_atomic_op("and $1, %1, %z5", 109 ret, oldval, uaddr, ~oparg); 110 break; 111 case FUTEX_OP_XOR: 112 __futex_atomic_op("xor $1, %1, %z5", 113 ret, oldval, uaddr, oparg); 114 break; 115 default: 116 ret = -ENOSYS; 117 } 118 119 pagefault_enable(); 120 121 if (!ret) { 122 switch (cmp) { 123 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; 124 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; 125 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; 126 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; 127 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; 128 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; 129 default: ret = -ENOSYS; 130 } 131 } 132 return ret; 133 } 134 135 static inline int 136 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, 137 u32 oldval, u32 newval) 138 { 139 int ret = 0; 140 u32 val; 141 142 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) 143 return -EFAULT; 144 145 if (cpu_has_llsc && R10000_LLSC_WAR) { 146 __asm__ __volatile__( 147 "# futex_atomic_cmpxchg_inatomic \n" 148 " .set push \n" 149 " .set noat \n" 150 " .set mips3 \n" 151 "1: ll %1, %3 \n" 152 " bne %1, %z4, 3f \n" 153 " .set mips0 \n" 154 " move $1, %z5 \n" 155 " .set mips3 \n" 156 "2: sc $1, %2 \n" 157 " beqzl $1, 1b \n" 158 __WEAK_LLSC_MB 159 "3: \n" 160 " .set pop \n" 161 " .section .fixup,\"ax\" \n" 162 "4: li %0, %6 \n" 163 " j 3b \n" 164 " .previous \n" 165 " .section __ex_table,\"a\" \n" 166 " "__UA_ADDR "\t1b, 4b \n" 167 " "__UA_ADDR "\t2b, 4b \n" 168 " .previous \n" 169 : "+r" (ret), "=&r" (val), "=R" (*uaddr) 170 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) 171 : "memory"); 172 } else if (cpu_has_llsc) { 173 __asm__ __volatile__( 174 "# futex_atomic_cmpxchg_inatomic \n" 175 " .set push \n" 176 " .set noat \n" 177 " .set mips3 \n" 178 "1: "user_ll("%1", "%3")" \n" 179 " bne %1, %z4, 3f \n" 180 " .set mips0 \n" 181 " move $1, %z5 \n" 182 " .set mips3 \n" 183 "2: "user_sc("$1", "%2")" \n" 184 " beqz $1, 1b \n" 185 __WEAK_LLSC_MB 186 "3: \n" 187 " .set pop \n" 188 " .section .fixup,\"ax\" \n" 189 "4: li %0, %6 \n" 190 " j 3b \n" 191 " .previous \n" 192 " .section __ex_table,\"a\" \n" 193 " "__UA_ADDR "\t1b, 4b \n" 194 " "__UA_ADDR "\t2b, 4b \n" 195 " .previous \n" 196 : "+r" (ret), "=&r" (val), "=R" (*uaddr) 197 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) 198 : "memory"); 199 } else 200 return -ENOSYS; 201 202 *uval = val; 203 return ret; 204 } 205 206 #endif 207 #endif /* _ASM_FUTEX_H */ 208