xref: /openbmc/linux/arch/mips/include/asm/ftrace.h (revision a3ba49c1)
1d2bb0762SWu Zhangjin /*
2d2bb0762SWu Zhangjin  * This file is subject to the terms and conditions of the GNU General Public
3d2bb0762SWu Zhangjin  * License.  See the file "COPYING" in the main directory of this archive for
4d2bb0762SWu Zhangjin  * more details.
5d2bb0762SWu Zhangjin  *
6d2bb0762SWu Zhangjin  * Copyright (C) 2009 DSLab, Lanzhou University, China
7f7a904dfSWu Zhangjin  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
8d2bb0762SWu Zhangjin  */
9d2bb0762SWu Zhangjin 
10d2bb0762SWu Zhangjin #ifndef _ASM_MIPS_FTRACE_H
11d2bb0762SWu Zhangjin #define _ASM_MIPS_FTRACE_H
12d2bb0762SWu Zhangjin 
13d2bb0762SWu Zhangjin #ifdef CONFIG_FUNCTION_TRACER
14d2bb0762SWu Zhangjin 
15d2bb0762SWu Zhangjin #define MCOUNT_ADDR ((unsigned long)(_mcount))
16d2bb0762SWu Zhangjin #define MCOUNT_INSN_SIZE 4		/* sizeof mcount call */
17d2bb0762SWu Zhangjin 
18d2bb0762SWu Zhangjin #ifndef __ASSEMBLY__
19d2bb0762SWu Zhangjin extern void _mcount(void);
20d2bb0762SWu Zhangjin #define mcount _mcount
21d2bb0762SWu Zhangjin 
22046199caSWu Zhangjin #define safe_load(load, src, dst, error)		\
23046199caSWu Zhangjin do {							\
24046199caSWu Zhangjin 	asm volatile (					\
25b08ac66bSViller Hsiao 		"1: " load " %[tmp_dst], 0(%[tmp_src])\n"	\
26b08ac66bSViller Hsiao 		"   li %[tmp_err], 0\n"			\
27aedd153fSMarkos Chandras 		"2: .insn\n"				\
28046199caSWu Zhangjin 							\
29046199caSWu Zhangjin 		".section .fixup, \"ax\"\n"		\
30b08ac66bSViller Hsiao 		"3: li %[tmp_err], 1\n"			\
31046199caSWu Zhangjin 		"   j 2b\n"				\
32046199caSWu Zhangjin 		".previous\n"				\
33046199caSWu Zhangjin 							\
34046199caSWu Zhangjin 		".section\t__ex_table,\"a\"\n\t"	\
35*a3ba49c1SThomas Bogendoerfer 		STR(PTR_WD) "\t1b, 3b\n\t"		\
36046199caSWu Zhangjin 		".previous\n"				\
37046199caSWu Zhangjin 							\
38b08ac66bSViller Hsiao 		: [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
39b08ac66bSViller Hsiao 		: [tmp_src] "r" (src)			\
40046199caSWu Zhangjin 		: "memory"				\
41046199caSWu Zhangjin 	);						\
42046199caSWu Zhangjin } while (0)
43046199caSWu Zhangjin 
44046199caSWu Zhangjin #define safe_store(store, src, dst, error)	\
45046199caSWu Zhangjin do {						\
46046199caSWu Zhangjin 	asm volatile (				\
47b08ac66bSViller Hsiao 		"1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48b08ac66bSViller Hsiao 		"   li %[tmp_err], 0\n"		\
49aedd153fSMarkos Chandras 		"2: .insn\n"			\
50046199caSWu Zhangjin 						\
51046199caSWu Zhangjin 		".section .fixup, \"ax\"\n"	\
52b08ac66bSViller Hsiao 		"3: li %[tmp_err], 1\n"		\
53046199caSWu Zhangjin 		"   j 2b\n"			\
54046199caSWu Zhangjin 		".previous\n"			\
55046199caSWu Zhangjin 						\
56046199caSWu Zhangjin 		".section\t__ex_table,\"a\"\n\t"\
57*a3ba49c1SThomas Bogendoerfer 		STR(PTR_WD) "\t1b, 3b\n\t"	\
58046199caSWu Zhangjin 		".previous\n"			\
59046199caSWu Zhangjin 						\
60b08ac66bSViller Hsiao 		: [tmp_err] "=r" (error)	\
61b08ac66bSViller Hsiao 		: [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
62046199caSWu Zhangjin 		: "memory"			\
63046199caSWu Zhangjin 	);					\
64046199caSWu Zhangjin } while (0)
65046199caSWu Zhangjin 
66046199caSWu Zhangjin #define safe_load_code(dst, src, error) \
67046199caSWu Zhangjin 	safe_load(STR(lw), src, dst, error)
68046199caSWu Zhangjin #define safe_store_code(src, dst, error) \
69046199caSWu Zhangjin 	safe_store(STR(sw), src, dst, error)
70046199caSWu Zhangjin 
71046199caSWu Zhangjin #define safe_load_stack(dst, src, error) \
72046199caSWu Zhangjin 	safe_load(STR(PTR_L), src, dst, error)
73046199caSWu Zhangjin 
74046199caSWu Zhangjin #define safe_store_stack(src, dst, error) \
75046199caSWu Zhangjin 	safe_store(STR(PTR_S), src, dst, error)
76046199caSWu Zhangjin 
77046199caSWu Zhangjin 
78538f1952SWu Zhangjin #ifdef CONFIG_DYNAMIC_FTRACE
ftrace_call_adjust(unsigned long addr)79538f1952SWu Zhangjin static inline unsigned long ftrace_call_adjust(unsigned long addr)
80538f1952SWu Zhangjin {
81538f1952SWu Zhangjin 	return addr;
82538f1952SWu Zhangjin }
83538f1952SWu Zhangjin 
84538f1952SWu Zhangjin struct dyn_arch_ftrace {
85538f1952SWu Zhangjin };
86046199caSWu Zhangjin 
87538f1952SWu Zhangjin #endif /*  CONFIG_DYNAMIC_FTRACE */
88d2bb0762SWu Zhangjin #endif /* __ASSEMBLY__ */
89d2bb0762SWu Zhangjin #endif /* CONFIG_FUNCTION_TRACER */
90d2bb0762SWu Zhangjin #endif /* _ASM_MIPS_FTRACE_H */
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