1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * linux/include/asm/dma.h: Defines for using and allocating dma channels. 3384740dcSRalf Baechle * Written by Hennus Bergman, 1992. 4384740dcSRalf Baechle * High DMA channel support & info by Hannu Savolainen 5384740dcSRalf Baechle * and John Boyd, Nov. 1992. 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards 8384740dcSRalf Baechle * and can only be used for expansion cards. Onboard DMA controllers, such 9384740dcSRalf Baechle * as the R4030 on Jazz boards behave totally different! 10384740dcSRalf Baechle */ 11384740dcSRalf Baechle 12384740dcSRalf Baechle #ifndef _ASM_DMA_H 13384740dcSRalf Baechle #define _ASM_DMA_H 14384740dcSRalf Baechle 15384740dcSRalf Baechle #include <asm/io.h> /* need byte IO */ 16384740dcSRalf Baechle #include <linux/spinlock.h> /* And spinlocks */ 17384740dcSRalf Baechle #include <linux/delay.h> 18384740dcSRalf Baechle #include <asm/system.h> 19384740dcSRalf Baechle 20384740dcSRalf Baechle 21384740dcSRalf Baechle #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 22384740dcSRalf Baechle #define dma_outb outb_p 23384740dcSRalf Baechle #else 24384740dcSRalf Baechle #define dma_outb outb 25384740dcSRalf Baechle #endif 26384740dcSRalf Baechle 27384740dcSRalf Baechle #define dma_inb inb 28384740dcSRalf Baechle 29384740dcSRalf Baechle /* 30384740dcSRalf Baechle * NOTES about DMA transfers: 31384740dcSRalf Baechle * 32384740dcSRalf Baechle * controller 1: channels 0-3, byte operations, ports 00-1F 33384740dcSRalf Baechle * controller 2: channels 4-7, word operations, ports C0-DF 34384740dcSRalf Baechle * 35384740dcSRalf Baechle * - ALL registers are 8 bits only, regardless of transfer size 36384740dcSRalf Baechle * - channel 4 is not used - cascades 1 into 2. 37384740dcSRalf Baechle * - channels 0-3 are byte - addresses/counts are for physical bytes 38384740dcSRalf Baechle * - channels 5-7 are word - addresses/counts are for physical words 39384740dcSRalf Baechle * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 40384740dcSRalf Baechle * - transfer count loaded to registers is 1 less than actual count 41384740dcSRalf Baechle * - controller 2 offsets are all even (2x offsets for controller 1) 42384740dcSRalf Baechle * - page registers for 5-7 don't use data bit 0, represent 128K pages 43384740dcSRalf Baechle * - page registers for 0-3 use bit 0, represent 64K pages 44384740dcSRalf Baechle * 45384740dcSRalf Baechle * DMA transfers are limited to the lower 16MB of _physical_ memory. 46384740dcSRalf Baechle * Note that addresses loaded into registers must be _physical_ addresses, 47384740dcSRalf Baechle * not logical addresses (which may differ if paging is active). 48384740dcSRalf Baechle * 49384740dcSRalf Baechle * Address mapping for channels 0-3: 50384740dcSRalf Baechle * 51384740dcSRalf Baechle * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 52384740dcSRalf Baechle * | ... | | ... | | ... | 53384740dcSRalf Baechle * | ... | | ... | | ... | 54384740dcSRalf Baechle * | ... | | ... | | ... | 55384740dcSRalf Baechle * P7 ... P0 A7 ... A0 A7 ... A0 56384740dcSRalf Baechle * | Page | Addr MSB | Addr LSB | (DMA registers) 57384740dcSRalf Baechle * 58384740dcSRalf Baechle * Address mapping for channels 5-7: 59384740dcSRalf Baechle * 60384740dcSRalf Baechle * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 61384740dcSRalf Baechle * | ... | \ \ ... \ \ \ ... \ \ 62384740dcSRalf Baechle * | ... | \ \ ... \ \ \ ... \ (not used) 63384740dcSRalf Baechle * | ... | \ \ ... \ \ \ ... \ 64384740dcSRalf Baechle * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 65384740dcSRalf Baechle * | Page | Addr MSB | Addr LSB | (DMA registers) 66384740dcSRalf Baechle * 67384740dcSRalf Baechle * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 68384740dcSRalf Baechle * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 69384740dcSRalf Baechle * the hardware level, so odd-byte transfers aren't possible). 70384740dcSRalf Baechle * 71384740dcSRalf Baechle * Transfer count (_not # bytes_) is limited to 64K, represented as actual 72384740dcSRalf Baechle * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 73384740dcSRalf Baechle * and up to 128K bytes may be transferred on channels 5-7 in one operation. 74384740dcSRalf Baechle * 75384740dcSRalf Baechle */ 76384740dcSRalf Baechle 77384740dcSRalf Baechle #ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN 78384740dcSRalf Baechle #define MAX_DMA_CHANNELS 8 79384740dcSRalf Baechle #endif 80384740dcSRalf Baechle 81384740dcSRalf Baechle /* 82384740dcSRalf Baechle * The maximum address in KSEG0 that we can perform a DMA transfer to on this 83384740dcSRalf Baechle * platform. This describes only the PC style part of the DMA logic like on 84384740dcSRalf Baechle * Deskstations or Acer PICA but not the much more versatile DMA logic used 85384740dcSRalf Baechle * for the local devices on Acer PICA or Magnums. 86384740dcSRalf Baechle */ 87384740dcSRalf Baechle #if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28) 88384740dcSRalf Baechle /* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */ 89384740dcSRalf Baechle #define MAX_DMA_ADDRESS PAGE_OFFSET 90384740dcSRalf Baechle #else 91384740dcSRalf Baechle #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) 92384740dcSRalf Baechle #endif 93384740dcSRalf Baechle #define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) 94384740dcSRalf Baechle #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT)) 95384740dcSRalf Baechle 96384740dcSRalf Baechle /* 8237 DMA controllers */ 97384740dcSRalf Baechle #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 98384740dcSRalf Baechle #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 99384740dcSRalf Baechle 100384740dcSRalf Baechle /* DMA controller registers */ 101384740dcSRalf Baechle #define DMA1_CMD_REG 0x08 /* command register (w) */ 102384740dcSRalf Baechle #define DMA1_STAT_REG 0x08 /* status register (r) */ 103384740dcSRalf Baechle #define DMA1_REQ_REG 0x09 /* request register (w) */ 104384740dcSRalf Baechle #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 105384740dcSRalf Baechle #define DMA1_MODE_REG 0x0B /* mode register (w) */ 106384740dcSRalf Baechle #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 107384740dcSRalf Baechle #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 108384740dcSRalf Baechle #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 109384740dcSRalf Baechle #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 110384740dcSRalf Baechle #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 111384740dcSRalf Baechle 112384740dcSRalf Baechle #define DMA2_CMD_REG 0xD0 /* command register (w) */ 113384740dcSRalf Baechle #define DMA2_STAT_REG 0xD0 /* status register (r) */ 114384740dcSRalf Baechle #define DMA2_REQ_REG 0xD2 /* request register (w) */ 115384740dcSRalf Baechle #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 116384740dcSRalf Baechle #define DMA2_MODE_REG 0xD6 /* mode register (w) */ 117384740dcSRalf Baechle #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 118384740dcSRalf Baechle #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 119384740dcSRalf Baechle #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 120384740dcSRalf Baechle #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 121384740dcSRalf Baechle #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 122384740dcSRalf Baechle 123384740dcSRalf Baechle #define DMA_ADDR_0 0x00 /* DMA address registers */ 124384740dcSRalf Baechle #define DMA_ADDR_1 0x02 125384740dcSRalf Baechle #define DMA_ADDR_2 0x04 126384740dcSRalf Baechle #define DMA_ADDR_3 0x06 127384740dcSRalf Baechle #define DMA_ADDR_4 0xC0 128384740dcSRalf Baechle #define DMA_ADDR_5 0xC4 129384740dcSRalf Baechle #define DMA_ADDR_6 0xC8 130384740dcSRalf Baechle #define DMA_ADDR_7 0xCC 131384740dcSRalf Baechle 132384740dcSRalf Baechle #define DMA_CNT_0 0x01 /* DMA count registers */ 133384740dcSRalf Baechle #define DMA_CNT_1 0x03 134384740dcSRalf Baechle #define DMA_CNT_2 0x05 135384740dcSRalf Baechle #define DMA_CNT_3 0x07 136384740dcSRalf Baechle #define DMA_CNT_4 0xC2 137384740dcSRalf Baechle #define DMA_CNT_5 0xC6 138384740dcSRalf Baechle #define DMA_CNT_6 0xCA 139384740dcSRalf Baechle #define DMA_CNT_7 0xCE 140384740dcSRalf Baechle 141384740dcSRalf Baechle #define DMA_PAGE_0 0x87 /* DMA page registers */ 142384740dcSRalf Baechle #define DMA_PAGE_1 0x83 143384740dcSRalf Baechle #define DMA_PAGE_2 0x81 144384740dcSRalf Baechle #define DMA_PAGE_3 0x82 145384740dcSRalf Baechle #define DMA_PAGE_5 0x8B 146384740dcSRalf Baechle #define DMA_PAGE_6 0x89 147384740dcSRalf Baechle #define DMA_PAGE_7 0x8A 148384740dcSRalf Baechle 149384740dcSRalf Baechle #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 150384740dcSRalf Baechle #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 151384740dcSRalf Baechle #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 152384740dcSRalf Baechle 153384740dcSRalf Baechle #define DMA_AUTOINIT 0x10 154384740dcSRalf Baechle 155384740dcSRalf Baechle extern spinlock_t dma_spin_lock; 156384740dcSRalf Baechle 157384740dcSRalf Baechle static __inline__ unsigned long claim_dma_lock(void) 158384740dcSRalf Baechle { 159384740dcSRalf Baechle unsigned long flags; 160384740dcSRalf Baechle spin_lock_irqsave(&dma_spin_lock, flags); 161384740dcSRalf Baechle return flags; 162384740dcSRalf Baechle } 163384740dcSRalf Baechle 164384740dcSRalf Baechle static __inline__ void release_dma_lock(unsigned long flags) 165384740dcSRalf Baechle { 166384740dcSRalf Baechle spin_unlock_irqrestore(&dma_spin_lock, flags); 167384740dcSRalf Baechle } 168384740dcSRalf Baechle 169384740dcSRalf Baechle /* enable/disable a specific DMA channel */ 170384740dcSRalf Baechle static __inline__ void enable_dma(unsigned int dmanr) 171384740dcSRalf Baechle { 172384740dcSRalf Baechle if (dmanr<=3) 173384740dcSRalf Baechle dma_outb(dmanr, DMA1_MASK_REG); 174384740dcSRalf Baechle else 175384740dcSRalf Baechle dma_outb(dmanr & 3, DMA2_MASK_REG); 176384740dcSRalf Baechle } 177384740dcSRalf Baechle 178384740dcSRalf Baechle static __inline__ void disable_dma(unsigned int dmanr) 179384740dcSRalf Baechle { 180384740dcSRalf Baechle if (dmanr<=3) 181384740dcSRalf Baechle dma_outb(dmanr | 4, DMA1_MASK_REG); 182384740dcSRalf Baechle else 183384740dcSRalf Baechle dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 184384740dcSRalf Baechle } 185384740dcSRalf Baechle 186384740dcSRalf Baechle /* Clear the 'DMA Pointer Flip Flop'. 187384740dcSRalf Baechle * Write 0 for LSB/MSB, 1 for MSB/LSB access. 188384740dcSRalf Baechle * Use this once to initialize the FF to a known state. 189384740dcSRalf Baechle * After that, keep track of it. :-) 190384740dcSRalf Baechle * --- In order to do that, the DMA routines below should --- 191384740dcSRalf Baechle * --- only be used while holding the DMA lock ! --- 192384740dcSRalf Baechle */ 193384740dcSRalf Baechle static __inline__ void clear_dma_ff(unsigned int dmanr) 194384740dcSRalf Baechle { 195384740dcSRalf Baechle if (dmanr<=3) 196384740dcSRalf Baechle dma_outb(0, DMA1_CLEAR_FF_REG); 197384740dcSRalf Baechle else 198384740dcSRalf Baechle dma_outb(0, DMA2_CLEAR_FF_REG); 199384740dcSRalf Baechle } 200384740dcSRalf Baechle 201384740dcSRalf Baechle /* set mode (above) for a specific DMA channel */ 202384740dcSRalf Baechle static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 203384740dcSRalf Baechle { 204384740dcSRalf Baechle if (dmanr<=3) 205384740dcSRalf Baechle dma_outb(mode | dmanr, DMA1_MODE_REG); 206384740dcSRalf Baechle else 207384740dcSRalf Baechle dma_outb(mode | (dmanr&3), DMA2_MODE_REG); 208384740dcSRalf Baechle } 209384740dcSRalf Baechle 210384740dcSRalf Baechle /* Set only the page register bits of the transfer address. 211384740dcSRalf Baechle * This is used for successive transfers when we know the contents of 212384740dcSRalf Baechle * the lower 16 bits of the DMA current address register, but a 64k boundary 213384740dcSRalf Baechle * may have been crossed. 214384740dcSRalf Baechle */ 215384740dcSRalf Baechle static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 216384740dcSRalf Baechle { 217384740dcSRalf Baechle switch(dmanr) { 218384740dcSRalf Baechle case 0: 219384740dcSRalf Baechle dma_outb(pagenr, DMA_PAGE_0); 220384740dcSRalf Baechle break; 221384740dcSRalf Baechle case 1: 222384740dcSRalf Baechle dma_outb(pagenr, DMA_PAGE_1); 223384740dcSRalf Baechle break; 224384740dcSRalf Baechle case 2: 225384740dcSRalf Baechle dma_outb(pagenr, DMA_PAGE_2); 226384740dcSRalf Baechle break; 227384740dcSRalf Baechle case 3: 228384740dcSRalf Baechle dma_outb(pagenr, DMA_PAGE_3); 229384740dcSRalf Baechle break; 230384740dcSRalf Baechle case 5: 231384740dcSRalf Baechle dma_outb(pagenr & 0xfe, DMA_PAGE_5); 232384740dcSRalf Baechle break; 233384740dcSRalf Baechle case 6: 234384740dcSRalf Baechle dma_outb(pagenr & 0xfe, DMA_PAGE_6); 235384740dcSRalf Baechle break; 236384740dcSRalf Baechle case 7: 237384740dcSRalf Baechle dma_outb(pagenr & 0xfe, DMA_PAGE_7); 238384740dcSRalf Baechle break; 239384740dcSRalf Baechle } 240384740dcSRalf Baechle } 241384740dcSRalf Baechle 242384740dcSRalf Baechle 243384740dcSRalf Baechle /* Set transfer address & page bits for specific DMA channel. 244384740dcSRalf Baechle * Assumes dma flipflop is clear. 245384740dcSRalf Baechle */ 246384740dcSRalf Baechle static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) 247384740dcSRalf Baechle { 248384740dcSRalf Baechle set_dma_page(dmanr, a>>16); 249384740dcSRalf Baechle if (dmanr <= 3) { 250384740dcSRalf Baechle dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 251384740dcSRalf Baechle dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 252384740dcSRalf Baechle } else { 253384740dcSRalf Baechle dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 254384740dcSRalf Baechle dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 255384740dcSRalf Baechle } 256384740dcSRalf Baechle } 257384740dcSRalf Baechle 258384740dcSRalf Baechle 259384740dcSRalf Baechle /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for 260384740dcSRalf Baechle * a specific DMA channel. 261384740dcSRalf Baechle * You must ensure the parameters are valid. 262384740dcSRalf Baechle * NOTE: from a manual: "the number of transfers is one more 263384740dcSRalf Baechle * than the initial word count"! This is taken into account. 264384740dcSRalf Baechle * Assumes dma flip-flop is clear. 265384740dcSRalf Baechle * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 266384740dcSRalf Baechle */ 267384740dcSRalf Baechle static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 268384740dcSRalf Baechle { 269384740dcSRalf Baechle count--; 270384740dcSRalf Baechle if (dmanr <= 3) { 271384740dcSRalf Baechle dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 272384740dcSRalf Baechle dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 273384740dcSRalf Baechle } else { 274384740dcSRalf Baechle dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 275384740dcSRalf Baechle dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 276384740dcSRalf Baechle } 277384740dcSRalf Baechle } 278384740dcSRalf Baechle 279384740dcSRalf Baechle 280384740dcSRalf Baechle /* Get DMA residue count. After a DMA transfer, this 281384740dcSRalf Baechle * should return zero. Reading this while a DMA transfer is 282384740dcSRalf Baechle * still in progress will return unpredictable results. 283384740dcSRalf Baechle * If called before the channel has been used, it may return 1. 284384740dcSRalf Baechle * Otherwise, it returns the number of _bytes_ left to transfer. 285384740dcSRalf Baechle * 286384740dcSRalf Baechle * Assumes DMA flip-flop is clear. 287384740dcSRalf Baechle */ 288384740dcSRalf Baechle static __inline__ int get_dma_residue(unsigned int dmanr) 289384740dcSRalf Baechle { 290384740dcSRalf Baechle unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 291384740dcSRalf Baechle : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 292384740dcSRalf Baechle 293384740dcSRalf Baechle /* using short to get 16-bit wrap around */ 294384740dcSRalf Baechle unsigned short count; 295384740dcSRalf Baechle 296384740dcSRalf Baechle count = 1 + dma_inb(io_port); 297384740dcSRalf Baechle count += dma_inb(io_port) << 8; 298384740dcSRalf Baechle 299384740dcSRalf Baechle return (dmanr<=3)? count : (count<<1); 300384740dcSRalf Baechle } 301384740dcSRalf Baechle 302384740dcSRalf Baechle 303384740dcSRalf Baechle /* These are in kernel/dma.c: */ 304384740dcSRalf Baechle extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 305384740dcSRalf Baechle extern void free_dma(unsigned int dmanr); /* release it again */ 306384740dcSRalf Baechle 307384740dcSRalf Baechle /* From PCI */ 308384740dcSRalf Baechle 309384740dcSRalf Baechle #ifdef CONFIG_PCI 310384740dcSRalf Baechle extern int isa_dma_bridge_buggy; 311384740dcSRalf Baechle #else 312384740dcSRalf Baechle #define isa_dma_bridge_buggy (0) 313384740dcSRalf Baechle #endif 314384740dcSRalf Baechle 315384740dcSRalf Baechle #endif /* _ASM_DMA_H */ 316