1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * include/asm-mips/dec/kn05.h 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min 5384740dcSRalf Baechle * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or 6384740dcSRalf Baechle * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC 7384740dcSRalf Baechle * definitions. 8384740dcSRalf Baechle * 9384740dcSRalf Baechle * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki 10384740dcSRalf Baechle * 11384740dcSRalf Baechle * This program is free software; you can redistribute it and/or 12384740dcSRalf Baechle * modify it under the terms of the GNU General Public License 13384740dcSRalf Baechle * as published by the Free Software Foundation; either version 14384740dcSRalf Baechle * 2 of the License, or (at your option) any later version. 15384740dcSRalf Baechle * 16384740dcSRalf Baechle * WARNING! All this information is pure guesswork based on the 17384740dcSRalf Baechle * ROM. It is provided here in hope it will give someone some 18384740dcSRalf Baechle * food for thought. No documentation for the KN05 nor the KN04 19384740dcSRalf Baechle * module has been located so far. 20384740dcSRalf Baechle */ 21384740dcSRalf Baechle #ifndef __ASM_MIPS_DEC_KN05_H 22384740dcSRalf Baechle #define __ASM_MIPS_DEC_KN05_H 23384740dcSRalf Baechle 24384740dcSRalf Baechle #include <asm/dec/ioasic_addrs.h> 25384740dcSRalf Baechle 26384740dcSRalf Baechle /* 27384740dcSRalf Baechle * The oncard MB (Memory Buffer) ASIC provides an additional address 28384740dcSRalf Baechle * decoder. Certain address ranges within the "high" 16 slots are 29384740dcSRalf Baechle * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. 30384740dcSRalf Baechle * Others are handled locally. "Low" slots are always passed. 31384740dcSRalf Baechle */ 32384740dcSRalf Baechle #define KN4K_SLOT_BASE 0x1fc00000 33384740dcSRalf Baechle 34384740dcSRalf Baechle #define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ 35384740dcSRalf Baechle #define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ 36384740dcSRalf Baechle #define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ 37384740dcSRalf Baechle #define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ 38384740dcSRalf Baechle #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */ 39384740dcSRalf Baechle #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */ 40384740dcSRalf Baechle #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */ 41384740dcSRalf Baechle #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */ 42384740dcSRalf Baechle #define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */ 43384740dcSRalf Baechle #define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */ 44384740dcSRalf Baechle #define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ 45384740dcSRalf Baechle #define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ 46384740dcSRalf Baechle #define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 47384740dcSRalf Baechle #define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ 48384740dcSRalf Baechle #define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ 49384740dcSRalf Baechle #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 50384740dcSRalf Baechle 51384740dcSRalf Baechle /* 52384740dcSRalf Baechle * Bits for the MB interrupt register. 53384740dcSRalf Baechle * The register appears read-only. 54384740dcSRalf Baechle */ 55384740dcSRalf Baechle #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ 56384740dcSRalf Baechle #define KN4K_MB_INT_RTC (1<<1) /* RTC? */ 57384740dcSRalf Baechle #define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ 58384740dcSRalf Baechle 59384740dcSRalf Baechle /* 60384740dcSRalf Baechle * Bits for the MB control & status register. 61384740dcSRalf Baechle * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. 62384740dcSRalf Baechle */ 63384740dcSRalf Baechle #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ 64384740dcSRalf Baechle #define KN4K_MB_CSR_F (1<<1) /* ??? */ 65384740dcSRalf Baechle #define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ 66384740dcSRalf Baechle #define KN4K_MB_CSR_OD (1<<10) /* ??? */ 67384740dcSRalf Baechle #define KN4K_MB_CSR_CP (1<<11) /* ??? */ 68384740dcSRalf Baechle #define KN4K_MB_CSR_UNC (1<<12) /* ??? */ 69384740dcSRalf Baechle #define KN4K_MB_CSR_IM (1<<13) /* ??? */ 70384740dcSRalf Baechle #define KN4K_MB_CSR_NC (1<<14) /* ??? */ 71384740dcSRalf Baechle #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 72384740dcSRalf Baechle #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ 73384740dcSRalf Baechle #define KN4K_MB_CSR_FW (1<<21) /* ??? */ 74384740dcSRalf Baechle #define KN4K_MB_CSR_W (1<<31) /* ??? */ 75384740dcSRalf Baechle 76384740dcSRalf Baechle #endif /* __ASM_MIPS_DEC_KN05_H */ 77