12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * include/asm-mips/dec/kn05.h 4384740dcSRalf Baechle * 5384740dcSRalf Baechle * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min 6384740dcSRalf Baechle * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or 7384740dcSRalf Baechle * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC 8384740dcSRalf Baechle * definitions. 9384740dcSRalf Baechle * 10384740dcSRalf Baechle * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki 11384740dcSRalf Baechle * 12384740dcSRalf Baechle * WARNING! All this information is pure guesswork based on the 13384740dcSRalf Baechle * ROM. It is provided here in hope it will give someone some 14384740dcSRalf Baechle * food for thought. No documentation for the KN05 nor the KN04 15384740dcSRalf Baechle * module has been located so far. 16384740dcSRalf Baechle */ 17384740dcSRalf Baechle #ifndef __ASM_MIPS_DEC_KN05_H 18384740dcSRalf Baechle #define __ASM_MIPS_DEC_KN05_H 19384740dcSRalf Baechle 20384740dcSRalf Baechle #include <asm/dec/ioasic_addrs.h> 21384740dcSRalf Baechle 22384740dcSRalf Baechle /* 23384740dcSRalf Baechle * The oncard MB (Memory Buffer) ASIC provides an additional address 24384740dcSRalf Baechle * decoder. Certain address ranges within the "high" 16 slots are 25384740dcSRalf Baechle * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. 26384740dcSRalf Baechle * Others are handled locally. "Low" slots are always passed. 27384740dcSRalf Baechle */ 28384740dcSRalf Baechle #define KN4K_SLOT_BASE 0x1fc00000 29384740dcSRalf Baechle 30384740dcSRalf Baechle #define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ 31384740dcSRalf Baechle #define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ 32384740dcSRalf Baechle #define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ 33384740dcSRalf Baechle #define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ 34384740dcSRalf Baechle #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */ 35384740dcSRalf Baechle #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */ 36384740dcSRalf Baechle #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */ 37384740dcSRalf Baechle #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */ 38384740dcSRalf Baechle #define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */ 39384740dcSRalf Baechle #define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */ 40384740dcSRalf Baechle #define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ 41384740dcSRalf Baechle #define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ 42384740dcSRalf Baechle #define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 43384740dcSRalf Baechle #define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ 44384740dcSRalf Baechle #define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ 45384740dcSRalf Baechle #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 46384740dcSRalf Baechle 47384740dcSRalf Baechle /* 48fd28b9acSMaciej W. Rozycki * MB ASIC interrupt bits. 49fd28b9acSMaciej W. Rozycki */ 50fd28b9acSMaciej W. Rozycki #define KN4K_MB_INR_MB 4 /* ??? */ 51fd28b9acSMaciej W. Rozycki #define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */ 52fd28b9acSMaciej W. Rozycki #define KN4K_MB_INR_RES_2 2 /* unused */ 53fd28b9acSMaciej W. Rozycki #define KN4K_MB_INR_RTC 1 /* RTC */ 54fd28b9acSMaciej W. Rozycki #define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */ 55fd28b9acSMaciej W. Rozycki 56fd28b9acSMaciej W. Rozycki /* 57384740dcSRalf Baechle * Bits for the MB interrupt register. 58384740dcSRalf Baechle * The register appears read-only. 59384740dcSRalf Baechle */ 60fd28b9acSMaciej W. Rozycki #define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */ 61fd28b9acSMaciej W. Rozycki #define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */ 62384740dcSRalf Baechle 63384740dcSRalf Baechle /* 64384740dcSRalf Baechle * Bits for the MB control & status register. 65384740dcSRalf Baechle * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. 66384740dcSRalf Baechle */ 67384740dcSRalf Baechle #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ 68384740dcSRalf Baechle #define KN4K_MB_CSR_F (1<<1) /* ??? */ 69384740dcSRalf Baechle #define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ 70384740dcSRalf Baechle #define KN4K_MB_CSR_OD (1<<10) /* ??? */ 71384740dcSRalf Baechle #define KN4K_MB_CSR_CP (1<<11) /* ??? */ 72384740dcSRalf Baechle #define KN4K_MB_CSR_UNC (1<<12) /* ??? */ 73384740dcSRalf Baechle #define KN4K_MB_CSR_IM (1<<13) /* ??? */ 74384740dcSRalf Baechle #define KN4K_MB_CSR_NC (1<<14) /* ??? */ 75384740dcSRalf Baechle #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 76384740dcSRalf Baechle #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ 77fd28b9acSMaciej W. Rozycki #define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */ 78384740dcSRalf Baechle #define KN4K_MB_CSR_FW (1<<21) /* ??? */ 79384740dcSRalf Baechle #define KN4K_MB_CSR_W (1<<31) /* ??? */ 80384740dcSRalf Baechle 81384740dcSRalf Baechle #endif /* __ASM_MIPS_DEC_KN05_H */ 82