1 /* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 6 * Copyright (C) 2004, 2013 Maciej W. Rozycki 7 */ 8 #ifndef _ASM_CPU_H 9 #define _ASM_CPU_H 10 11 /* 12 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 13 register 15, select 0) is defined in this (backwards compatible) way: 14 15 +----------------+----------------+----------------+----------------+ 16 | Company Options| Company ID | Processor ID | Revision | 17 +----------------+----------------+----------------+----------------+ 18 31 24 23 16 15 8 7 19 20 I don't have docs for all the previous processors, but my impression is 21 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 22 spec. 23 */ 24 25 #define PRID_OPT_MASK 0xff000000 26 27 /* 28 * Assigned Company values for bits 23:16 of the PRId register. 29 */ 30 31 #define PRID_COMP_MASK 0xff0000 32 33 #define PRID_COMP_LEGACY 0x000000 34 #define PRID_COMP_MIPS 0x010000 35 #define PRID_COMP_BROADCOM 0x020000 36 #define PRID_COMP_ALCHEMY 0x030000 37 #define PRID_COMP_SIBYTE 0x040000 38 #define PRID_COMP_SANDCRAFT 0x050000 39 #define PRID_COMP_NXP 0x060000 40 #define PRID_COMP_TOSHIBA 0x070000 41 #define PRID_COMP_LSI 0x080000 42 #define PRID_COMP_LEXRA 0x0b0000 43 #define PRID_COMP_NETLOGIC 0x0c0000 44 #define PRID_COMP_CAVIUM 0x0d0000 45 #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */ 46 #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */ 47 #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ 48 49 /* 50 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 51 * register. In order to detect a certain CPU type exactly eventually 52 * additional registers may need to be examined. 53 */ 54 55 #define PRID_IMP_MASK 0xff00 56 57 /* 58 * These are valid when 23:16 == PRID_COMP_LEGACY 59 */ 60 61 #define PRID_IMP_R2000 0x0100 62 #define PRID_IMP_AU1_REV1 0x0100 63 #define PRID_IMP_AU1_REV2 0x0200 64 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 65 #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 66 #define PRID_IMP_R4000 0x0400 67 #define PRID_IMP_R6000A 0x0600 68 #define PRID_IMP_R10000 0x0900 69 #define PRID_IMP_R4300 0x0b00 70 #define PRID_IMP_VR41XX 0x0c00 71 #define PRID_IMP_R12000 0x0e00 72 #define PRID_IMP_R14000 0x0f00 /* R14K && R16K */ 73 #define PRID_IMP_R8000 0x1000 74 #define PRID_IMP_PR4450 0x1200 75 #define PRID_IMP_R4600 0x2000 76 #define PRID_IMP_R4700 0x2100 77 #define PRID_IMP_TX39 0x2200 78 #define PRID_IMP_R4640 0x2200 79 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 80 #define PRID_IMP_R5000 0x2300 81 #define PRID_IMP_TX49 0x2d00 82 #define PRID_IMP_SONIC 0x2400 83 #define PRID_IMP_MAGIC 0x2500 84 #define PRID_IMP_RM7000 0x2700 85 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 86 #define PRID_IMP_RM9000 0x3400 87 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ 88 #define PRID_IMP_R5432 0x5400 89 #define PRID_IMP_R5500 0x5500 90 #define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ 91 92 #define PRID_IMP_UNKNOWN 0xff00 93 94 /* 95 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 96 */ 97 98 #define PRID_IMP_QEMU_GENERIC 0x0000 99 #define PRID_IMP_4KC 0x8000 100 #define PRID_IMP_5KC 0x8100 101 #define PRID_IMP_20KC 0x8200 102 #define PRID_IMP_4KEC 0x8400 103 #define PRID_IMP_4KSC 0x8600 104 #define PRID_IMP_25KF 0x8800 105 #define PRID_IMP_5KE 0x8900 106 #define PRID_IMP_4KECR2 0x9000 107 #define PRID_IMP_4KEMPR2 0x9100 108 #define PRID_IMP_4KSD 0x9200 109 #define PRID_IMP_24K 0x9300 110 #define PRID_IMP_34K 0x9500 111 #define PRID_IMP_24KE 0x9600 112 #define PRID_IMP_74K 0x9700 113 #define PRID_IMP_1004K 0x9900 114 #define PRID_IMP_1074K 0x9a00 115 #define PRID_IMP_M14KC 0x9c00 116 #define PRID_IMP_M14KEC 0x9e00 117 #define PRID_IMP_INTERAPTIV_UP 0xa000 118 #define PRID_IMP_INTERAPTIV_MP 0xa100 119 #define PRID_IMP_PROAPTIV_UP 0xa200 120 #define PRID_IMP_PROAPTIV_MP 0xa300 121 #define PRID_IMP_P6600 0xa400 122 #define PRID_IMP_M5150 0xa700 123 #define PRID_IMP_P5600 0xa800 124 #define PRID_IMP_I6400 0xa900 125 #define PRID_IMP_M6250 0xab00 126 127 /* 128 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 129 */ 130 131 #define PRID_IMP_SB1 0x0100 132 #define PRID_IMP_SB1A 0x1100 133 134 /* 135 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 136 */ 137 138 #define PRID_IMP_SR71000 0x0400 139 140 /* 141 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 142 */ 143 144 #define PRID_IMP_BMIPS32_REV4 0x4000 145 #define PRID_IMP_BMIPS32_REV8 0x8000 146 #define PRID_IMP_BMIPS3300 0x9000 147 #define PRID_IMP_BMIPS3300_ALT 0x9100 148 #define PRID_IMP_BMIPS3300_BUG 0x0000 149 #define PRID_IMP_BMIPS43XX 0xa000 150 #define PRID_IMP_BMIPS5000 0x5a00 151 #define PRID_IMP_BMIPS5200 0x5b00 152 153 #define PRID_REV_BMIPS4380_LO 0x0040 154 #define PRID_REV_BMIPS4380_HI 0x006f 155 156 /* 157 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 158 */ 159 160 #define PRID_IMP_CAVIUM_CN38XX 0x0000 161 #define PRID_IMP_CAVIUM_CN31XX 0x0100 162 #define PRID_IMP_CAVIUM_CN30XX 0x0200 163 #define PRID_IMP_CAVIUM_CN58XX 0x0300 164 #define PRID_IMP_CAVIUM_CN56XX 0x0400 165 #define PRID_IMP_CAVIUM_CN50XX 0x0600 166 #define PRID_IMP_CAVIUM_CN52XX 0x0700 167 #define PRID_IMP_CAVIUM_CN63XX 0x9000 168 #define PRID_IMP_CAVIUM_CN68XX 0x9100 169 #define PRID_IMP_CAVIUM_CN66XX 0x9200 170 #define PRID_IMP_CAVIUM_CN61XX 0x9300 171 #define PRID_IMP_CAVIUM_CNF71XX 0x9400 172 #define PRID_IMP_CAVIUM_CN78XX 0x9500 173 #define PRID_IMP_CAVIUM_CN70XX 0x9600 174 #define PRID_IMP_CAVIUM_CN73XX 0x9700 175 #define PRID_IMP_CAVIUM_CNF75XX 0x9800 176 177 /* 178 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* 179 */ 180 181 #define PRID_IMP_JZRISC 0x0200 182 183 /* 184 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 185 */ 186 #define PRID_IMP_NETLOGIC_XLR732 0x0000 187 #define PRID_IMP_NETLOGIC_XLR716 0x0200 188 #define PRID_IMP_NETLOGIC_XLR532 0x0900 189 #define PRID_IMP_NETLOGIC_XLR308 0x0600 190 #define PRID_IMP_NETLOGIC_XLR532C 0x0800 191 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 192 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 193 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 194 #define PRID_IMP_NETLOGIC_XLS608 0x8000 195 #define PRID_IMP_NETLOGIC_XLS408 0x8800 196 #define PRID_IMP_NETLOGIC_XLS404 0x8c00 197 #define PRID_IMP_NETLOGIC_XLS208 0x8e00 198 #define PRID_IMP_NETLOGIC_XLS204 0x8f00 199 #define PRID_IMP_NETLOGIC_XLS108 0xce00 200 #define PRID_IMP_NETLOGIC_XLS104 0xcf00 201 #define PRID_IMP_NETLOGIC_XLS616B 0x4000 202 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 203 #define PRID_IMP_NETLOGIC_XLS416B 0x4400 204 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 205 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 206 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 207 #define PRID_IMP_NETLOGIC_AU13XX 0x8000 208 209 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 210 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 211 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 212 #define PRID_IMP_NETLOGIC_XLP9XX 0x1500 213 #define PRID_IMP_NETLOGIC_XLP5XX 0x1300 214 215 /* 216 * Particular Revision values for bits 7:0 of the PRId register. 217 */ 218 219 #define PRID_REV_MASK 0x00ff 220 221 /* 222 * Definitions for 7:0 on legacy processors 223 */ 224 225 #define PRID_REV_TX4927 0x0022 226 #define PRID_REV_TX4937 0x0030 227 #define PRID_REV_R4400 0x0040 228 #define PRID_REV_R3000A 0x0030 229 #define PRID_REV_R3000 0x0020 230 #define PRID_REV_R2000A 0x0010 231 #define PRID_REV_TX3912 0x0010 232 #define PRID_REV_TX3922 0x0030 233 #define PRID_REV_TX3927 0x0040 234 #define PRID_REV_VR4111 0x0050 235 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 236 #define PRID_REV_VR4121 0x0060 237 #define PRID_REV_VR4122 0x0070 238 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 239 #define PRID_REV_VR4130 0x0080 240 #define PRID_REV_34K_V1_0_2 0x0022 241 #define PRID_REV_LOONGSON1B 0x0020 242 #define PRID_REV_LOONGSON2E 0x0002 243 #define PRID_REV_LOONGSON2F 0x0003 244 #define PRID_REV_LOONGSON3A 0x0005 245 #define PRID_REV_LOONGSON3B_R1 0x0006 246 #define PRID_REV_LOONGSON3B_R2 0x0007 247 248 /* 249 * Older processors used to encode processor version and revision in two 250 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 251 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 252 * the patch number. *ARGH* 253 */ 254 #define PRID_REV_ENCODE_44(ver, rev) \ 255 ((ver) << 4 | (rev)) 256 #define PRID_REV_ENCODE_332(ver, rev, patch) \ 257 ((ver) << 5 | (rev) << 2 | (patch)) 258 259 /* 260 * FPU implementation/revision register (CP1 control register 0). 261 * 262 * +---------------------------------+----------------+----------------+ 263 * | 0 | Implementation | Revision | 264 * +---------------------------------+----------------+----------------+ 265 * 31 16 15 8 7 0 266 */ 267 268 #define FPIR_IMP_MASK 0xff00 269 270 #define FPIR_IMP_NONE 0x0000 271 272 #if !defined(__ASSEMBLY__) 273 274 enum cpu_type_enum { 275 CPU_UNKNOWN, 276 277 /* 278 * R2000 class processors 279 */ 280 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 281 CPU_R3081, CPU_R3081E, 282 283 /* 284 * R6000 class processors 285 */ 286 CPU_R6000, CPU_R6000A, 287 288 /* 289 * R4000 class processors 290 */ 291 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 292 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 293 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 294 CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 295 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 296 CPU_SR71000, CPU_TX49XX, 297 298 /* 299 * R8000 class processors 300 */ 301 CPU_R8000, 302 303 /* 304 * TX3900 class processors 305 */ 306 CPU_TX3912, CPU_TX3922, CPU_TX3927, 307 308 /* 309 * MIPS32 class processors 310 */ 311 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 312 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 313 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 314 CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, 315 CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250, 316 317 /* 318 * MIPS64 class processors 319 */ 320 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 321 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, 322 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, 323 324 CPU_QEMU_GENERIC, 325 326 CPU_LAST 327 }; 328 329 #endif /* !__ASSEMBLY */ 330 331 /* 332 * ISA Level encodings 333 * 334 */ 335 #define MIPS_CPU_ISA_II 0x00000001 336 #define MIPS_CPU_ISA_III 0x00000002 337 #define MIPS_CPU_ISA_IV 0x00000004 338 #define MIPS_CPU_ISA_V 0x00000008 339 #define MIPS_CPU_ISA_M32R1 0x00000010 340 #define MIPS_CPU_ISA_M32R2 0x00000020 341 #define MIPS_CPU_ISA_M64R1 0x00000040 342 #define MIPS_CPU_ISA_M64R2 0x00000080 343 #define MIPS_CPU_ISA_M32R6 0x00000100 344 #define MIPS_CPU_ISA_M64R6 0x00000200 345 346 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 347 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6) 348 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 349 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ 350 MIPS_CPU_ISA_M64R6) 351 352 /* 353 * Private version of BIT_ULL() to escape include file recursion hell. 354 * We soon will have to switch to another mechanism that will work with 355 * more than 64 bits anyway. 356 */ 357 #define MBIT_ULL(bit) (1ULL << (bit)) 358 359 /* 360 * CPU Option encodings 361 */ 362 #define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */ 363 #define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */ 364 #define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */ 365 #define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */ 366 #define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */ 367 #define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */ 368 #define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */ 369 #define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */ 370 #define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */ 371 #define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */ 372 #define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */ 373 #define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */ 374 #define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */ 375 #define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */ 376 #define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */ 377 #define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */ 378 #define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */ 379 #define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */ 380 #define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */ 381 #define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */ 382 #define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ 383 #define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */ 384 #define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */ 385 #define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */ 386 #define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */ 387 #define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */ 388 #define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */ 389 #define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */ 390 #define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */ 391 #define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 392 #define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */ 393 #define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */ 394 #define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */ 395 #define MIPS_CPU_XPA MBIT_ULL(33) /* CPU supports Extended Physical Addressing */ 396 #define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */ 397 #define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */ 398 #define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */ 399 #define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */ 400 #define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */ 401 #define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */ 402 #define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */ 403 404 /* 405 * CPU ASE encodings 406 */ 407 #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 408 #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 409 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 410 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 411 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 412 #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 413 #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 414 #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ 415 #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ 416 #define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/ 417 418 #endif /* _ASM_CPU_H */ 419