1 /* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 6 * Copyright (C) 2004, 2013 Maciej W. Rozycki 7 */ 8 #ifndef _ASM_CPU_H 9 #define _ASM_CPU_H 10 11 /* 12 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 13 register 15, select 0) is defined in this (backwards compatible) way: 14 15 +----------------+----------------+----------------+----------------+ 16 | Company Options| Company ID | Processor ID | Revision | 17 +----------------+----------------+----------------+----------------+ 18 31 24 23 16 15 8 7 19 20 I don't have docs for all the previous processors, but my impression is 21 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 22 spec. 23 */ 24 25 #define PRID_OPT_MASK 0xff000000 26 27 /* 28 * Assigned Company values for bits 23:16 of the PRId register. 29 */ 30 31 #define PRID_COMP_MASK 0xff0000 32 33 #define PRID_COMP_LEGACY 0x000000 34 #define PRID_COMP_MIPS 0x010000 35 #define PRID_COMP_BROADCOM 0x020000 36 #define PRID_COMP_ALCHEMY 0x030000 37 #define PRID_COMP_SIBYTE 0x040000 38 #define PRID_COMP_SANDCRAFT 0x050000 39 #define PRID_COMP_NXP 0x060000 40 #define PRID_COMP_TOSHIBA 0x070000 41 #define PRID_COMP_LSI 0x080000 42 #define PRID_COMP_LEXRA 0x0b0000 43 #define PRID_COMP_NETLOGIC 0x0c0000 44 #define PRID_COMP_CAVIUM 0x0d0000 45 #define PRID_COMP_INGENIC 0xd00000 46 47 /* 48 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 49 * register. In order to detect a certain CPU type exactly eventually 50 * additional registers may need to be examined. 51 */ 52 53 #define PRID_IMP_MASK 0xff00 54 55 /* 56 * These are valid when 23:16 == PRID_COMP_LEGACY 57 */ 58 59 #define PRID_IMP_R2000 0x0100 60 #define PRID_IMP_AU1_REV1 0x0100 61 #define PRID_IMP_AU1_REV2 0x0200 62 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 63 #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 64 #define PRID_IMP_R4000 0x0400 65 #define PRID_IMP_R6000A 0x0600 66 #define PRID_IMP_R10000 0x0900 67 #define PRID_IMP_R4300 0x0b00 68 #define PRID_IMP_VR41XX 0x0c00 69 #define PRID_IMP_R12000 0x0e00 70 #define PRID_IMP_R14000 0x0f00 71 #define PRID_IMP_R8000 0x1000 72 #define PRID_IMP_PR4450 0x1200 73 #define PRID_IMP_R4600 0x2000 74 #define PRID_IMP_R4700 0x2100 75 #define PRID_IMP_TX39 0x2200 76 #define PRID_IMP_R4640 0x2200 77 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 78 #define PRID_IMP_R5000 0x2300 79 #define PRID_IMP_TX49 0x2d00 80 #define PRID_IMP_SONIC 0x2400 81 #define PRID_IMP_MAGIC 0x2500 82 #define PRID_IMP_RM7000 0x2700 83 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 84 #define PRID_IMP_RM9000 0x3400 85 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ 86 #define PRID_IMP_R5432 0x5400 87 #define PRID_IMP_R5500 0x5500 88 #define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ 89 90 #define PRID_IMP_UNKNOWN 0xff00 91 92 /* 93 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 94 */ 95 96 #define PRID_IMP_4KC 0x8000 97 #define PRID_IMP_5KC 0x8100 98 #define PRID_IMP_20KC 0x8200 99 #define PRID_IMP_4KEC 0x8400 100 #define PRID_IMP_4KSC 0x8600 101 #define PRID_IMP_25KF 0x8800 102 #define PRID_IMP_5KE 0x8900 103 #define PRID_IMP_4KECR2 0x9000 104 #define PRID_IMP_4KEMPR2 0x9100 105 #define PRID_IMP_4KSD 0x9200 106 #define PRID_IMP_24K 0x9300 107 #define PRID_IMP_34K 0x9500 108 #define PRID_IMP_24KE 0x9600 109 #define PRID_IMP_74K 0x9700 110 #define PRID_IMP_1004K 0x9900 111 #define PRID_IMP_1074K 0x9a00 112 #define PRID_IMP_M14KC 0x9c00 113 #define PRID_IMP_M14KEC 0x9e00 114 #define PRID_IMP_INTERAPTIV_UP 0xa000 115 #define PRID_IMP_INTERAPTIV_MP 0xa100 116 #define PRID_IMP_PROAPTIV_UP 0xa200 117 #define PRID_IMP_PROAPTIV_MP 0xa300 118 #define PRID_IMP_M5150 0xa700 119 #define PRID_IMP_P5600 0xa800 120 121 /* 122 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 123 */ 124 125 #define PRID_IMP_SB1 0x0100 126 #define PRID_IMP_SB1A 0x1100 127 128 /* 129 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 130 */ 131 132 #define PRID_IMP_SR71000 0x0400 133 134 /* 135 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 136 */ 137 138 #define PRID_IMP_BMIPS32_REV4 0x4000 139 #define PRID_IMP_BMIPS32_REV8 0x8000 140 #define PRID_IMP_BMIPS3300 0x9000 141 #define PRID_IMP_BMIPS3300_ALT 0x9100 142 #define PRID_IMP_BMIPS3300_BUG 0x0000 143 #define PRID_IMP_BMIPS43XX 0xa000 144 #define PRID_IMP_BMIPS5000 0x5a00 145 146 #define PRID_REV_BMIPS4380_LO 0x0040 147 #define PRID_REV_BMIPS4380_HI 0x006f 148 149 /* 150 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 151 */ 152 153 #define PRID_IMP_CAVIUM_CN38XX 0x0000 154 #define PRID_IMP_CAVIUM_CN31XX 0x0100 155 #define PRID_IMP_CAVIUM_CN30XX 0x0200 156 #define PRID_IMP_CAVIUM_CN58XX 0x0300 157 #define PRID_IMP_CAVIUM_CN56XX 0x0400 158 #define PRID_IMP_CAVIUM_CN50XX 0x0600 159 #define PRID_IMP_CAVIUM_CN52XX 0x0700 160 #define PRID_IMP_CAVIUM_CN63XX 0x9000 161 #define PRID_IMP_CAVIUM_CN68XX 0x9100 162 #define PRID_IMP_CAVIUM_CN66XX 0x9200 163 #define PRID_IMP_CAVIUM_CN61XX 0x9300 164 #define PRID_IMP_CAVIUM_CNF71XX 0x9400 165 #define PRID_IMP_CAVIUM_CN78XX 0x9500 166 #define PRID_IMP_CAVIUM_CN70XX 0x9600 167 168 /* 169 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC 170 */ 171 172 #define PRID_IMP_JZRISC 0x0200 173 174 /* 175 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 176 */ 177 #define PRID_IMP_NETLOGIC_XLR732 0x0000 178 #define PRID_IMP_NETLOGIC_XLR716 0x0200 179 #define PRID_IMP_NETLOGIC_XLR532 0x0900 180 #define PRID_IMP_NETLOGIC_XLR308 0x0600 181 #define PRID_IMP_NETLOGIC_XLR532C 0x0800 182 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 183 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 184 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 185 #define PRID_IMP_NETLOGIC_XLS608 0x8000 186 #define PRID_IMP_NETLOGIC_XLS408 0x8800 187 #define PRID_IMP_NETLOGIC_XLS404 0x8c00 188 #define PRID_IMP_NETLOGIC_XLS208 0x8e00 189 #define PRID_IMP_NETLOGIC_XLS204 0x8f00 190 #define PRID_IMP_NETLOGIC_XLS108 0xce00 191 #define PRID_IMP_NETLOGIC_XLS104 0xcf00 192 #define PRID_IMP_NETLOGIC_XLS616B 0x4000 193 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 194 #define PRID_IMP_NETLOGIC_XLS416B 0x4400 195 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 196 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 197 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 198 #define PRID_IMP_NETLOGIC_AU13XX 0x8000 199 200 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 201 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 202 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 203 #define PRID_IMP_NETLOGIC_XLP9XX 0x1500 204 #define PRID_IMP_NETLOGIC_XLP5XX 0x1300 205 206 /* 207 * Particular Revision values for bits 7:0 of the PRId register. 208 */ 209 210 #define PRID_REV_MASK 0x00ff 211 212 /* 213 * Definitions for 7:0 on legacy processors 214 */ 215 216 #define PRID_REV_TX4927 0x0022 217 #define PRID_REV_TX4937 0x0030 218 #define PRID_REV_R4400 0x0040 219 #define PRID_REV_R3000A 0x0030 220 #define PRID_REV_R3000 0x0020 221 #define PRID_REV_R2000A 0x0010 222 #define PRID_REV_TX3912 0x0010 223 #define PRID_REV_TX3922 0x0030 224 #define PRID_REV_TX3927 0x0040 225 #define PRID_REV_VR4111 0x0050 226 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 227 #define PRID_REV_VR4121 0x0060 228 #define PRID_REV_VR4122 0x0070 229 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 230 #define PRID_REV_VR4130 0x0080 231 #define PRID_REV_34K_V1_0_2 0x0022 232 #define PRID_REV_LOONGSON1B 0x0020 233 #define PRID_REV_LOONGSON2E 0x0002 234 #define PRID_REV_LOONGSON2F 0x0003 235 #define PRID_REV_LOONGSON3A 0x0005 236 #define PRID_REV_LOONGSON3B_R1 0x0006 237 #define PRID_REV_LOONGSON3B_R2 0x0007 238 239 /* 240 * Older processors used to encode processor version and revision in two 241 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 242 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 243 * the patch number. *ARGH* 244 */ 245 #define PRID_REV_ENCODE_44(ver, rev) \ 246 ((ver) << 4 | (rev)) 247 #define PRID_REV_ENCODE_332(ver, rev, patch) \ 248 ((ver) << 5 | (rev) << 2 | (patch)) 249 250 /* 251 * FPU implementation/revision register (CP1 control register 0). 252 * 253 * +---------------------------------+----------------+----------------+ 254 * | 0 | Implementation | Revision | 255 * +---------------------------------+----------------+----------------+ 256 * 31 16 15 8 7 0 257 */ 258 259 #define FPIR_IMP_MASK 0xff00 260 261 #define FPIR_IMP_NONE 0x0000 262 263 #if !defined(__ASSEMBLY__) 264 265 enum cpu_type_enum { 266 CPU_UNKNOWN, 267 268 /* 269 * R2000 class processors 270 */ 271 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 272 CPU_R3081, CPU_R3081E, 273 274 /* 275 * R6000 class processors 276 */ 277 CPU_R6000, CPU_R6000A, 278 279 /* 280 * R4000 class processors 281 */ 282 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 283 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 284 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 285 CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, 286 CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 287 CPU_SR71000, CPU_TX49XX, 288 289 /* 290 * R8000 class processors 291 */ 292 CPU_R8000, 293 294 /* 295 * TX3900 class processors 296 */ 297 CPU_TX3912, CPU_TX3922, CPU_TX3927, 298 299 /* 300 * MIPS32 class processors 301 */ 302 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 303 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 304 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 305 CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150, 306 307 /* 308 * MIPS64 class processors 309 */ 310 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 311 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, 312 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, 313 314 CPU_LAST 315 }; 316 317 #endif /* !__ASSEMBLY */ 318 319 /* 320 * ISA Level encodings 321 * 322 */ 323 #define MIPS_CPU_ISA_II 0x00000001 324 #define MIPS_CPU_ISA_III 0x00000002 325 #define MIPS_CPU_ISA_IV 0x00000004 326 #define MIPS_CPU_ISA_V 0x00000008 327 #define MIPS_CPU_ISA_M32R1 0x00000010 328 #define MIPS_CPU_ISA_M32R2 0x00000020 329 #define MIPS_CPU_ISA_M64R1 0x00000040 330 #define MIPS_CPU_ISA_M64R2 0x00000080 331 332 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 333 MIPS_CPU_ISA_M32R2) 334 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 335 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 336 337 /* 338 * CPU Option encodings 339 */ 340 #define MIPS_CPU_TLB 0x00000001ull /* CPU has TLB */ 341 #define MIPS_CPU_4KEX 0x00000002ull /* "R4K" exception model */ 342 #define MIPS_CPU_3K_CACHE 0x00000004ull /* R3000-style caches */ 343 #define MIPS_CPU_4K_CACHE 0x00000008ull /* R4000-style caches */ 344 #define MIPS_CPU_TX39_CACHE 0x00000010ull /* TX3900-style caches */ 345 #define MIPS_CPU_FPU 0x00000020ull /* CPU has FPU */ 346 #define MIPS_CPU_32FPR 0x00000040ull /* 32 dbl. prec. FP registers */ 347 #define MIPS_CPU_COUNTER 0x00000080ull /* Cycle count/compare */ 348 #define MIPS_CPU_WATCH 0x00000100ull /* watchpoint registers */ 349 #define MIPS_CPU_DIVEC 0x00000200ull /* dedicated interrupt vector */ 350 #define MIPS_CPU_VCE 0x00000400ull /* virt. coherence conflict possible */ 351 #define MIPS_CPU_CACHE_CDEX_P 0x00000800ull /* Create_Dirty_Exclusive CACHE op */ 352 #define MIPS_CPU_CACHE_CDEX_S 0x00001000ull /* ... same for seconary cache ... */ 353 #define MIPS_CPU_MCHECK 0x00002000ull /* Machine check exception */ 354 #define MIPS_CPU_EJTAG 0x00004000ull /* EJTAG exception */ 355 #define MIPS_CPU_NOFPUEX 0x00008000ull /* no FPU exception */ 356 #define MIPS_CPU_LLSC 0x00010000ull /* CPU has ll/sc instructions */ 357 #define MIPS_CPU_INCLUSIVE_CACHES 0x00020000ull /* P-cache subset enforced */ 358 #define MIPS_CPU_PREFETCH 0x00040000ull /* CPU has usable prefetch */ 359 #define MIPS_CPU_VINT 0x00080000ull /* CPU supports MIPSR2 vectored interrupts */ 360 #define MIPS_CPU_VEIC 0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */ 361 #define MIPS_CPU_ULRI 0x00200000ull /* CPU has ULRI feature */ 362 #define MIPS_CPU_PCI 0x00400000ull /* CPU has Perf Ctr Int indicator */ 363 #define MIPS_CPU_RIXI 0x00800000ull /* CPU has TLB Read/eXec Inhibit */ 364 #define MIPS_CPU_MICROMIPS 0x01000000ull /* CPU has microMIPS capability */ 365 #define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */ 366 #define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */ 367 #define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */ 368 #define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */ 369 #define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 370 #define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 371 372 /* 373 * CPU ASE encodings 374 */ 375 #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 376 #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 377 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 378 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 379 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 380 #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 381 #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 382 #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ 383 #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ 384 385 #endif /* _ASM_CPU_H */ 386