1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * cpu.h: Values of the PRId register used to match up 3384740dcSRalf Baechle * various MIPS cpu types. 4384740dcSRalf Baechle * 579add627SJustin P. Mattock * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 68ff374b9SMaciej W. Rozycki * Copyright (C) 2004, 2013 Maciej W. Rozycki 7384740dcSRalf Baechle */ 8384740dcSRalf Baechle #ifndef _ASM_CPU_H 9384740dcSRalf Baechle #define _ASM_CPU_H 10384740dcSRalf Baechle 118ff374b9SMaciej W. Rozycki /* 128ff374b9SMaciej W. Rozycki As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 138ff374b9SMaciej W. Rozycki register 15, select 0) is defined in this (backwards compatible) way: 14384740dcSRalf Baechle 15384740dcSRalf Baechle +----------------+----------------+----------------+----------------+ 16384740dcSRalf Baechle | Company Options| Company ID | Processor ID | Revision | 17384740dcSRalf Baechle +----------------+----------------+----------------+----------------+ 18384740dcSRalf Baechle 31 24 23 16 15 8 7 19384740dcSRalf Baechle 20384740dcSRalf Baechle I don't have docs for all the previous processors, but my impression is 21384740dcSRalf Baechle that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 22384740dcSRalf Baechle spec. 23384740dcSRalf Baechle */ 24384740dcSRalf Baechle 258ff374b9SMaciej W. Rozycki #define PRID_OPT_MASK 0xff000000 268ff374b9SMaciej W. Rozycki 278ff374b9SMaciej W. Rozycki /* 288ff374b9SMaciej W. Rozycki * Assigned Company values for bits 23:16 of the PRId register. 298ff374b9SMaciej W. Rozycki */ 308ff374b9SMaciej W. Rozycki 318ff374b9SMaciej W. Rozycki #define PRID_COMP_MASK 0xff0000 328ff374b9SMaciej W. Rozycki 33384740dcSRalf Baechle #define PRID_COMP_LEGACY 0x000000 34384740dcSRalf Baechle #define PRID_COMP_MIPS 0x010000 35384740dcSRalf Baechle #define PRID_COMP_BROADCOM 0x020000 36384740dcSRalf Baechle #define PRID_COMP_ALCHEMY 0x030000 37384740dcSRalf Baechle #define PRID_COMP_SIBYTE 0x040000 38384740dcSRalf Baechle #define PRID_COMP_SANDCRAFT 0x050000 39384740dcSRalf Baechle #define PRID_COMP_NXP 0x060000 40384740dcSRalf Baechle #define PRID_COMP_TOSHIBA 0x070000 41384740dcSRalf Baechle #define PRID_COMP_LSI 0x080000 42384740dcSRalf Baechle #define PRID_COMP_LEXRA 0x0b0000 43a7117c6bSJayachandran C #define PRID_COMP_NETLOGIC 0x0c0000 440dd4781bSDavid Daney #define PRID_COMP_CAVIUM 0x0d0000 45252617a4SPaul Burton #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */ 46252617a4SPaul Burton #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */ 47252617a4SPaul Burton #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ 48384740dcSRalf Baechle 49384740dcSRalf Baechle /* 508ff374b9SMaciej W. Rozycki * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 518ff374b9SMaciej W. Rozycki * register. In order to detect a certain CPU type exactly eventually 528ff374b9SMaciej W. Rozycki * additional registers may need to be examined. 53384740dcSRalf Baechle */ 548ff374b9SMaciej W. Rozycki 558ff374b9SMaciej W. Rozycki #define PRID_IMP_MASK 0xff00 568ff374b9SMaciej W. Rozycki 578ff374b9SMaciej W. Rozycki /* 588ff374b9SMaciej W. Rozycki * These are valid when 23:16 == PRID_COMP_LEGACY 598ff374b9SMaciej W. Rozycki */ 608ff374b9SMaciej W. Rozycki 61384740dcSRalf Baechle #define PRID_IMP_R2000 0x0100 62384740dcSRalf Baechle #define PRID_IMP_AU1_REV1 0x0100 63384740dcSRalf Baechle #define PRID_IMP_AU1_REV2 0x0200 64384740dcSRalf Baechle #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 65384740dcSRalf Baechle #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 66384740dcSRalf Baechle #define PRID_IMP_R4000 0x0400 67384740dcSRalf Baechle #define PRID_IMP_R6000A 0x0600 68384740dcSRalf Baechle #define PRID_IMP_R10000 0x0900 69384740dcSRalf Baechle #define PRID_IMP_R4300 0x0b00 70384740dcSRalf Baechle #define PRID_IMP_VR41XX 0x0c00 71384740dcSRalf Baechle #define PRID_IMP_R12000 0x0e00 7230577391SJoshua Kinard #define PRID_IMP_R14000 0x0f00 /* R14K && R16K */ 73384740dcSRalf Baechle #define PRID_IMP_R8000 0x1000 74384740dcSRalf Baechle #define PRID_IMP_PR4450 0x1200 75384740dcSRalf Baechle #define PRID_IMP_R4600 0x2000 76384740dcSRalf Baechle #define PRID_IMP_R4700 0x2100 77384740dcSRalf Baechle #define PRID_IMP_TX39 0x2200 78384740dcSRalf Baechle #define PRID_IMP_R4640 0x2200 79384740dcSRalf Baechle #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 80384740dcSRalf Baechle #define PRID_IMP_R5000 0x2300 81384740dcSRalf Baechle #define PRID_IMP_TX49 0x2d00 82384740dcSRalf Baechle #define PRID_IMP_SONIC 0x2400 83384740dcSRalf Baechle #define PRID_IMP_MAGIC 0x2500 84384740dcSRalf Baechle #define PRID_IMP_RM7000 0x2700 85384740dcSRalf Baechle #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 86384740dcSRalf Baechle #define PRID_IMP_RM9000 0x3400 8726859198SHuacai Chen #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ 88384740dcSRalf Baechle #define PRID_IMP_R5432 0x5400 89384740dcSRalf Baechle #define PRID_IMP_R5500 0x5500 9026859198SHuacai Chen #define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ 91384740dcSRalf Baechle 92384740dcSRalf Baechle #define PRID_IMP_UNKNOWN 0xff00 93384740dcSRalf Baechle 94384740dcSRalf Baechle /* 95384740dcSRalf Baechle * These are the PRID's for when 23:16 == PRID_COMP_MIPS 96384740dcSRalf Baechle */ 97384740dcSRalf Baechle 98aca5721eSLeonid Yegoshin #define PRID_IMP_QEMU_GENERIC 0x0000 99384740dcSRalf Baechle #define PRID_IMP_4KC 0x8000 100384740dcSRalf Baechle #define PRID_IMP_5KC 0x8100 101384740dcSRalf Baechle #define PRID_IMP_20KC 0x8200 102384740dcSRalf Baechle #define PRID_IMP_4KEC 0x8400 103384740dcSRalf Baechle #define PRID_IMP_4KSC 0x8600 104384740dcSRalf Baechle #define PRID_IMP_25KF 0x8800 105384740dcSRalf Baechle #define PRID_IMP_5KE 0x8900 106384740dcSRalf Baechle #define PRID_IMP_4KECR2 0x9000 107384740dcSRalf Baechle #define PRID_IMP_4KEMPR2 0x9100 108384740dcSRalf Baechle #define PRID_IMP_4KSD 0x9200 109384740dcSRalf Baechle #define PRID_IMP_24K 0x9300 110384740dcSRalf Baechle #define PRID_IMP_34K 0x9500 111384740dcSRalf Baechle #define PRID_IMP_24KE 0x9600 112384740dcSRalf Baechle #define PRID_IMP_74K 0x9700 113384740dcSRalf Baechle #define PRID_IMP_1004K 0x9900 114006a851bSSteven J. Hill #define PRID_IMP_1074K 0x9a00 115113c62d9SSteven J. Hill #define PRID_IMP_M14KC 0x9c00 116f8fa4811SSteven J. Hill #define PRID_IMP_M14KEC 0x9e00 1170ce7d58eSLeonid Yegoshin #define PRID_IMP_INTERAPTIV_UP 0xa000 1180ce7d58eSLeonid Yegoshin #define PRID_IMP_INTERAPTIV_MP 0xa100 11976f59e32SLeonid Yegoshin #define PRID_IMP_PROAPTIV_UP 0xa200 12076f59e32SLeonid Yegoshin #define PRID_IMP_PROAPTIV_MP 0xa300 1214975b86aSLeonid Yegoshin #define PRID_IMP_M5150 0xa700 122f43e4dfdSJames Hogan #define PRID_IMP_P5600 0xa800 12390b8baa2SMarkos Chandras #define PRID_IMP_I6400 0xa900 124384740dcSRalf Baechle 125384740dcSRalf Baechle /* 126384740dcSRalf Baechle * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 127384740dcSRalf Baechle */ 128384740dcSRalf Baechle 129384740dcSRalf Baechle #define PRID_IMP_SB1 0x0100 130384740dcSRalf Baechle #define PRID_IMP_SB1A 0x1100 131384740dcSRalf Baechle 132384740dcSRalf Baechle /* 133384740dcSRalf Baechle * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 134384740dcSRalf Baechle */ 135384740dcSRalf Baechle 136384740dcSRalf Baechle #define PRID_IMP_SR71000 0x0400 137384740dcSRalf Baechle 138384740dcSRalf Baechle /* 139384740dcSRalf Baechle * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 140384740dcSRalf Baechle */ 141384740dcSRalf Baechle 142190fca3eSKevin Cernekee #define PRID_IMP_BMIPS32_REV4 0x4000 143190fca3eSKevin Cernekee #define PRID_IMP_BMIPS32_REV8 0x8000 144602977b0SKevin Cernekee #define PRID_IMP_BMIPS3300 0x9000 145602977b0SKevin Cernekee #define PRID_IMP_BMIPS3300_ALT 0x9100 146602977b0SKevin Cernekee #define PRID_IMP_BMIPS3300_BUG 0x0000 147602977b0SKevin Cernekee #define PRID_IMP_BMIPS43XX 0xa000 148602977b0SKevin Cernekee #define PRID_IMP_BMIPS5000 0x5a00 14968e6a783SKevin Cernekee #define PRID_IMP_BMIPS5200 0x5b00 150602977b0SKevin Cernekee 151602977b0SKevin Cernekee #define PRID_REV_BMIPS4380_LO 0x0040 152602977b0SKevin Cernekee #define PRID_REV_BMIPS4380_HI 0x006f 153384740dcSRalf Baechle 154384740dcSRalf Baechle /* 1550dd4781bSDavid Daney * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 1560dd4781bSDavid Daney */ 1570dd4781bSDavid Daney 1580dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN38XX 0x0000 1590dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN31XX 0x0100 1600dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN30XX 0x0200 1610dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN58XX 0x0300 1620dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN56XX 0x0400 1630dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN50XX 0x0600 1640dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN52XX 0x0700 1651584d7f2SDavid Daney #define PRID_IMP_CAVIUM_CN63XX 0x9000 166074ef0d2SDavid Daney #define PRID_IMP_CAVIUM_CN68XX 0x9100 167074ef0d2SDavid Daney #define PRID_IMP_CAVIUM_CN66XX 0x9200 168074ef0d2SDavid Daney #define PRID_IMP_CAVIUM_CN61XX 0x9300 16971a8b7d8SDavid Daney #define PRID_IMP_CAVIUM_CNF71XX 0x9400 17071a8b7d8SDavid Daney #define PRID_IMP_CAVIUM_CN78XX 0x9500 17171a8b7d8SDavid Daney #define PRID_IMP_CAVIUM_CN70XX 0x9600 1720dd4781bSDavid Daney 1730dd4781bSDavid Daney /* 174252617a4SPaul Burton * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* 17583ccf69dSLars-Peter Clausen */ 17683ccf69dSLars-Peter Clausen 17783ccf69dSLars-Peter Clausen #define PRID_IMP_JZRISC 0x0200 17883ccf69dSLars-Peter Clausen 17983ccf69dSLars-Peter Clausen /* 180a7117c6bSJayachandran C * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 181a7117c6bSJayachandran C */ 182a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR732 0x0000 183a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR716 0x0200 184a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR532 0x0900 185a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR308 0x0600 186a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR532C 0x0800 187a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 188a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 189a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 190a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS608 0x8000 191a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS408 0x8800 192a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS404 0x8c00 193a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS208 0x8e00 194a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS204 0x8f00 195a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS108 0xce00 196a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS104 0xcf00 197a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS616B 0x4000 198a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 199a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS416B 0x4400 200a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 201a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 202a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 203809f36c6SManuel Lauss #define PRID_IMP_NETLOGIC_AU13XX 0x8000 204a7117c6bSJayachandran C 2052aa54b20SJayachandran C #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 2062aa54b20SJayachandran C #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 2074ca86a2fSJayachandran C #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 2088907c55eSJayachandran C #define PRID_IMP_NETLOGIC_XLP9XX 0x1500 2091c983986SYonghong Song #define PRID_IMP_NETLOGIC_XLP5XX 0x1300 210a7117c6bSJayachandran C 211a7117c6bSJayachandran C /* 2128ff374b9SMaciej W. Rozycki * Particular Revision values for bits 7:0 of the PRId register. 213384740dcSRalf Baechle */ 214384740dcSRalf Baechle 215384740dcSRalf Baechle #define PRID_REV_MASK 0x00ff 216384740dcSRalf Baechle 2178ff374b9SMaciej W. Rozycki /* 2188ff374b9SMaciej W. Rozycki * Definitions for 7:0 on legacy processors 2198ff374b9SMaciej W. Rozycki */ 2208ff374b9SMaciej W. Rozycki 221384740dcSRalf Baechle #define PRID_REV_TX4927 0x0022 222384740dcSRalf Baechle #define PRID_REV_TX4937 0x0030 223384740dcSRalf Baechle #define PRID_REV_R4400 0x0040 224384740dcSRalf Baechle #define PRID_REV_R3000A 0x0030 225384740dcSRalf Baechle #define PRID_REV_R3000 0x0020 226384740dcSRalf Baechle #define PRID_REV_R2000A 0x0010 227384740dcSRalf Baechle #define PRID_REV_TX3912 0x0010 228384740dcSRalf Baechle #define PRID_REV_TX3922 0x0030 229384740dcSRalf Baechle #define PRID_REV_TX3927 0x0040 230384740dcSRalf Baechle #define PRID_REV_VR4111 0x0050 231384740dcSRalf Baechle #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 232384740dcSRalf Baechle #define PRID_REV_VR4121 0x0060 233384740dcSRalf Baechle #define PRID_REV_VR4122 0x0070 234384740dcSRalf Baechle #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 235384740dcSRalf Baechle #define PRID_REV_VR4130 0x0080 236384740dcSRalf Baechle #define PRID_REV_34K_V1_0_2 0x0022 2372fa36399SKelvin Cheung #define PRID_REV_LOONGSON1B 0x0020 238f8ede0f7SWu Zhangjin #define PRID_REV_LOONGSON2E 0x0002 239f8ede0f7SWu Zhangjin #define PRID_REV_LOONGSON2F 0x0003 240152ebb44SHuacai Chen #define PRID_REV_LOONGSON3A 0x0005 241e7841be5SHuacai Chen #define PRID_REV_LOONGSON3B_R1 0x0006 242e7841be5SHuacai Chen #define PRID_REV_LOONGSON3B_R2 0x0007 243384740dcSRalf Baechle 244384740dcSRalf Baechle /* 245384740dcSRalf Baechle * Older processors used to encode processor version and revision in two 246384740dcSRalf Baechle * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 247384740dcSRalf Baechle * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 248384740dcSRalf Baechle * the patch number. *ARGH* 249384740dcSRalf Baechle */ 250384740dcSRalf Baechle #define PRID_REV_ENCODE_44(ver, rev) \ 251384740dcSRalf Baechle ((ver) << 4 | (rev)) 252384740dcSRalf Baechle #define PRID_REV_ENCODE_332(ver, rev, patch) \ 253384740dcSRalf Baechle ((ver) << 5 | (rev) << 2 | (patch)) 254384740dcSRalf Baechle 255384740dcSRalf Baechle /* 256384740dcSRalf Baechle * FPU implementation/revision register (CP1 control register 0). 257384740dcSRalf Baechle * 258384740dcSRalf Baechle * +---------------------------------+----------------+----------------+ 259384740dcSRalf Baechle * | 0 | Implementation | Revision | 260384740dcSRalf Baechle * +---------------------------------+----------------+----------------+ 261384740dcSRalf Baechle * 31 16 15 8 7 0 262384740dcSRalf Baechle */ 263384740dcSRalf Baechle 2648ff374b9SMaciej W. Rozycki #define FPIR_IMP_MASK 0xff00 2658ff374b9SMaciej W. Rozycki 266384740dcSRalf Baechle #define FPIR_IMP_NONE 0x0000 267384740dcSRalf Baechle 26868248d0cSJonas Gorski #if !defined(__ASSEMBLY__) 26968248d0cSJonas Gorski 270384740dcSRalf Baechle enum cpu_type_enum { 271384740dcSRalf Baechle CPU_UNKNOWN, 272384740dcSRalf Baechle 273384740dcSRalf Baechle /* 274384740dcSRalf Baechle * R2000 class processors 275384740dcSRalf Baechle */ 276384740dcSRalf Baechle CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 277384740dcSRalf Baechle CPU_R3081, CPU_R3081E, 278384740dcSRalf Baechle 279384740dcSRalf Baechle /* 280384740dcSRalf Baechle * R6000 class processors 281384740dcSRalf Baechle */ 282384740dcSRalf Baechle CPU_R6000, CPU_R6000A, 283384740dcSRalf Baechle 284384740dcSRalf Baechle /* 285384740dcSRalf Baechle * R4000 class processors 286384740dcSRalf Baechle */ 287384740dcSRalf Baechle CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 288384740dcSRalf Baechle CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 289fb2b1dbaSRalf Baechle CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 29030577391SJoshua Kinard CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 29130577391SJoshua Kinard CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 292321b1863SRalf Baechle CPU_SR71000, CPU_TX49XX, 293384740dcSRalf Baechle 294384740dcSRalf Baechle /* 295384740dcSRalf Baechle * R8000 class processors 296384740dcSRalf Baechle */ 297384740dcSRalf Baechle CPU_R8000, 298384740dcSRalf Baechle 299384740dcSRalf Baechle /* 300384740dcSRalf Baechle * TX3900 class processors 301384740dcSRalf Baechle */ 302384740dcSRalf Baechle CPU_TX3912, CPU_TX3922, CPU_TX3927, 303384740dcSRalf Baechle 304384740dcSRalf Baechle /* 305384740dcSRalf Baechle * MIPS32 class processors 306384740dcSRalf Baechle */ 307384740dcSRalf Baechle CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 308602977b0SKevin Cernekee CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 3092fa36399SKelvin Cheung CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 310f36c4720SLeonid Yegoshin CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150, 31190b8baa2SMarkos Chandras CPU_I6400, 312384740dcSRalf Baechle 313384740dcSRalf Baechle /* 314384740dcSRalf Baechle * MIPS64 class processors 315384740dcSRalf Baechle */ 31678d4803fSLeonid Yegoshin CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 317152ebb44SHuacai Chen CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, 318152ebb44SHuacai Chen CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, 319384740dcSRalf Baechle 320aca5721eSLeonid Yegoshin CPU_QEMU_GENERIC, 321aca5721eSLeonid Yegoshin 322384740dcSRalf Baechle CPU_LAST 323384740dcSRalf Baechle }; 324384740dcSRalf Baechle 32568248d0cSJonas Gorski #endif /* !__ASSEMBLY */ 326384740dcSRalf Baechle 327384740dcSRalf Baechle /* 328384740dcSRalf Baechle * ISA Level encodings 329384740dcSRalf Baechle * 330384740dcSRalf Baechle */ 3311990e542SRalf Baechle #define MIPS_CPU_ISA_II 0x00000001 3321990e542SRalf Baechle #define MIPS_CPU_ISA_III 0x00000002 3331990e542SRalf Baechle #define MIPS_CPU_ISA_IV 0x00000004 3341990e542SRalf Baechle #define MIPS_CPU_ISA_V 0x00000008 3351990e542SRalf Baechle #define MIPS_CPU_ISA_M32R1 0x00000010 3361990e542SRalf Baechle #define MIPS_CPU_ISA_M32R2 0x00000020 3371990e542SRalf Baechle #define MIPS_CPU_ISA_M64R1 0x00000040 3381990e542SRalf Baechle #define MIPS_CPU_ISA_M64R2 0x00000080 33934c56fc1SLeonid Yegoshin #define MIPS_CPU_ISA_M32R6 0x00000100 34034c56fc1SLeonid Yegoshin #define MIPS_CPU_ISA_M64R6 0x00000200 341384740dcSRalf Baechle 3421990e542SRalf Baechle #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 34334c56fc1SLeonid Yegoshin MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6) 344384740dcSRalf Baechle #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 34534c56fc1SLeonid Yegoshin MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ 34634c56fc1SLeonid Yegoshin MIPS_CPU_ISA_M64R6) 347384740dcSRalf Baechle 348384740dcSRalf Baechle /* 349384740dcSRalf Baechle * CPU Option encodings 350384740dcSRalf Baechle */ 35103a58777SMarkos Chandras #define MIPS_CPU_TLB 0x00000001ull /* CPU has TLB */ 35203a58777SMarkos Chandras #define MIPS_CPU_4KEX 0x00000002ull /* "R4K" exception model */ 35303a58777SMarkos Chandras #define MIPS_CPU_3K_CACHE 0x00000004ull /* R3000-style caches */ 35403a58777SMarkos Chandras #define MIPS_CPU_4K_CACHE 0x00000008ull /* R4000-style caches */ 35503a58777SMarkos Chandras #define MIPS_CPU_TX39_CACHE 0x00000010ull /* TX3900-style caches */ 35603a58777SMarkos Chandras #define MIPS_CPU_FPU 0x00000020ull /* CPU has FPU */ 35703a58777SMarkos Chandras #define MIPS_CPU_32FPR 0x00000040ull /* 32 dbl. prec. FP registers */ 35803a58777SMarkos Chandras #define MIPS_CPU_COUNTER 0x00000080ull /* Cycle count/compare */ 35903a58777SMarkos Chandras #define MIPS_CPU_WATCH 0x00000100ull /* watchpoint registers */ 36003a58777SMarkos Chandras #define MIPS_CPU_DIVEC 0x00000200ull /* dedicated interrupt vector */ 36103a58777SMarkos Chandras #define MIPS_CPU_VCE 0x00000400ull /* virt. coherence conflict possible */ 36203a58777SMarkos Chandras #define MIPS_CPU_CACHE_CDEX_P 0x00000800ull /* Create_Dirty_Exclusive CACHE op */ 36303a58777SMarkos Chandras #define MIPS_CPU_CACHE_CDEX_S 0x00001000ull /* ... same for seconary cache ... */ 36403a58777SMarkos Chandras #define MIPS_CPU_MCHECK 0x00002000ull /* Machine check exception */ 36503a58777SMarkos Chandras #define MIPS_CPU_EJTAG 0x00004000ull /* EJTAG exception */ 36603a58777SMarkos Chandras #define MIPS_CPU_NOFPUEX 0x00008000ull /* no FPU exception */ 36703a58777SMarkos Chandras #define MIPS_CPU_LLSC 0x00010000ull /* CPU has ll/sc instructions */ 36803a58777SMarkos Chandras #define MIPS_CPU_INCLUSIVE_CACHES 0x00020000ull /* P-cache subset enforced */ 36903a58777SMarkos Chandras #define MIPS_CPU_PREFETCH 0x00040000ull /* CPU has usable prefetch */ 37003a58777SMarkos Chandras #define MIPS_CPU_VINT 0x00080000ull /* CPU supports MIPSR2 vectored interrupts */ 37103a58777SMarkos Chandras #define MIPS_CPU_VEIC 0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */ 37203a58777SMarkos Chandras #define MIPS_CPU_ULRI 0x00200000ull /* CPU has ULRI feature */ 37303a58777SMarkos Chandras #define MIPS_CPU_PCI 0x00400000ull /* CPU has Perf Ctr Int indicator */ 37403a58777SMarkos Chandras #define MIPS_CPU_RIXI 0x00800000ull /* CPU has TLB Read/eXec Inhibit */ 37503a58777SMarkos Chandras #define MIPS_CPU_MICROMIPS 0x01000000ull /* CPU has microMIPS capability */ 37603a58777SMarkos Chandras #define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */ 37703a58777SMarkos Chandras #define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */ 37803a58777SMarkos Chandras #define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */ 379e647e6b5SMarkos Chandras #define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */ 3806ee729aaSLeonid Yegoshin #define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 3811f6c52ffSPaul Burton #define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 382adac5d53SPaul Burton #define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */ 3835aed9da1SMarkos Chandras #define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */ 384c5b36783SSteven J. Hill #define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */ 3853e20a26bSRalf Baechle #define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */ 3868d5ded16SJoshua Kinard #define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */ 387384740dcSRalf Baechle 388384740dcSRalf Baechle /* 389384740dcSRalf Baechle * CPU ASE encodings 390384740dcSRalf Baechle */ 391384740dcSRalf Baechle #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 392384740dcSRalf Baechle #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 393384740dcSRalf Baechle #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 394384740dcSRalf Baechle #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 395384740dcSRalf Baechle #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 396384740dcSRalf Baechle #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 397ee80f7c7SSteven J. Hill #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 3981e7decdbSDavid Daney #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ 399a5e9a69eSPaul Burton #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ 400384740dcSRalf Baechle 401384740dcSRalf Baechle #endif /* _ASM_CPU_H */ 402