1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 * Copyright (C) 2004 Maciej W. Rozycki 11 */ 12 #ifndef __ASM_CPU_INFO_H 13 #define __ASM_CPU_INFO_H 14 15 #include <linux/types.h> 16 17 #include <asm/cache.h> 18 19 /* 20 * Descriptor for a cache 21 */ 22 struct cache_desc { 23 unsigned int waysize; /* Bytes per way */ 24 unsigned short sets; /* Number of lines per set */ 25 unsigned char ways; /* Number of ways */ 26 unsigned char linesz; /* Size of line in bytes */ 27 unsigned char waybit; /* Bits to select in a cache set */ 28 unsigned char flags; /* Flags describing cache properties */ 29 }; 30 31 /* 32 * Flag definitions 33 */ 34 #define MIPS_CACHE_NOT_PRESENT 0x00000001 35 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ 36 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ 37 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ 38 #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ 39 #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ 40 41 struct cpuinfo_mips { 42 unsigned long asid_cache; 43 44 /* 45 * Capability and feature descriptor structure for MIPS CPU 46 */ 47 unsigned long options; 48 unsigned long ases; 49 unsigned int udelay_val; 50 unsigned int processor_id; 51 unsigned int fpu_id; 52 unsigned int msa_id; 53 unsigned int cputype; 54 int isa_level; 55 int tlbsize; 56 int tlbsizevtlb; 57 int tlbsizeftlbsets; 58 int tlbsizeftlbways; 59 struct cache_desc icache; /* Primary I-cache */ 60 struct cache_desc dcache; /* Primary D or combined I/D cache */ 61 struct cache_desc scache; /* Secondary cache */ 62 struct cache_desc tcache; /* Tertiary/split secondary cache */ 63 int srsets; /* Shadow register sets */ 64 int core; /* physical core number */ 65 #ifdef CONFIG_64BIT 66 int vmbits; /* Virtual memory size in bits */ 67 #endif 68 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 69 /* 70 * In the MIPS MT "SMTC" model, each TC is considered 71 * to be a "CPU" for the purposes of scheduling, but 72 * exception resources, ASID spaces, etc, are common 73 * to all TCs within the same VPE. 74 */ 75 int vpe_id; /* Virtual Processor number */ 76 #endif 77 #ifdef CONFIG_MIPS_MT_SMTC 78 int tc_id; /* Thread Context number */ 79 #endif 80 void *data; /* Additional data */ 81 unsigned int watch_reg_count; /* Number that exist */ 82 unsigned int watch_reg_use_cnt; /* Usable by ptrace */ 83 #define NUM_WATCH_REGS 4 84 u16 watch_reg_masks[NUM_WATCH_REGS]; 85 unsigned int kscratch_mask; /* Usable KScratch mask. */ 86 } __attribute__((aligned(SMP_CACHE_BYTES))); 87 88 extern struct cpuinfo_mips cpu_data[]; 89 #define current_cpu_data cpu_data[smp_processor_id()] 90 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 91 #define boot_cpu_data cpu_data[0] 92 93 extern void cpu_probe(void); 94 extern void cpu_report(void); 95 96 extern const char *__cpu_name[]; 97 #define cpu_name_string() __cpu_name[smp_processor_id()] 98 99 struct seq_file; 100 struct notifier_block; 101 102 extern int register_proc_cpuinfo_notifier(struct notifier_block *nb); 103 extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v); 104 105 #define proc_cpuinfo_notifier(fn, pri) \ 106 ({ \ 107 static struct notifier_block fn##_nb = { \ 108 .notifier_call = fn, \ 109 .priority = pri \ 110 }; \ 111 \ 112 register_proc_cpuinfo_notifier(&fn##_nb); \ 113 }) 114 115 struct proc_cpuinfo_notifier_args { 116 struct seq_file *m; 117 unsigned long n; 118 }; 119 120 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 121 # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id) 122 #else 123 # define cpu_vpe_id(cpuinfo) 0 124 #endif 125 126 #endif /* __ASM_CPU_INFO_H */ 127