1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <cpu-feature-overrides.h> 15 16 #ifndef current_cpu_type 17 #define current_cpu_type() current_cpu_data.cputype 18 #endif 19 20 #define boot_cpu_type() cpu_data[0].cputype 21 22 /* 23 * SMP assumption: Options of CPU 0 are a superset of all processors. 24 * This is true for all known MIPS systems. 25 */ 26 #ifndef cpu_has_tlb 27 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 28 #endif 29 30 /* 31 * For the moment we don't consider R6000 and R8000 so we can assume that 32 * anything that doesn't support R4000-style exceptions and interrupts is 33 * R3000-like. Users should still treat these two macro definitions as 34 * opaque. 35 */ 36 #ifndef cpu_has_3kex 37 #define cpu_has_3kex (!cpu_has_4kex) 38 #endif 39 #ifndef cpu_has_4kex 40 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 41 #endif 42 #ifndef cpu_has_3k_cache 43 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 44 #endif 45 #define cpu_has_6k_cache 0 46 #define cpu_has_8k_cache 0 47 #ifndef cpu_has_4k_cache 48 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 49 #endif 50 #ifndef cpu_has_tx39_cache 51 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 52 #endif 53 #ifndef cpu_has_octeon_cache 54 #define cpu_has_octeon_cache 0 55 #endif 56 #ifndef cpu_has_fpu 57 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 58 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 59 #else 60 #define raw_cpu_has_fpu cpu_has_fpu 61 #endif 62 #ifndef cpu_has_32fpr 63 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 64 #endif 65 #ifndef cpu_has_counter 66 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 67 #endif 68 #ifndef cpu_has_watch 69 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 70 #endif 71 #ifndef cpu_has_divec 72 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 73 #endif 74 #ifndef cpu_has_vce 75 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 76 #endif 77 #ifndef cpu_has_cache_cdex_p 78 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 79 #endif 80 #ifndef cpu_has_cache_cdex_s 81 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 82 #endif 83 #ifndef cpu_has_prefetch 84 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 85 #endif 86 #ifndef cpu_has_mcheck 87 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 88 #endif 89 #ifndef cpu_has_ejtag 90 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 91 #endif 92 #ifndef cpu_has_llsc 93 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 94 #endif 95 #ifndef kernel_uses_llsc 96 #define kernel_uses_llsc cpu_has_llsc 97 #endif 98 #ifndef cpu_has_mips16 99 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 100 #endif 101 #ifndef cpu_has_mdmx 102 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 103 #endif 104 #ifndef cpu_has_mips3d 105 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 106 #endif 107 #ifndef cpu_has_smartmips 108 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 109 #endif 110 #ifndef cpu_has_rixi 111 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 112 #endif 113 #ifndef cpu_has_mmips 114 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 115 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 116 # else 117 # define cpu_has_mmips 0 118 # endif 119 #endif 120 #ifndef cpu_has_vtag_icache 121 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 122 #endif 123 #ifndef cpu_has_dc_aliases 124 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 125 #endif 126 #ifndef cpu_has_ic_fills_f_dc 127 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 128 #endif 129 #ifndef cpu_has_pindexed_dcache 130 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 131 #endif 132 #ifndef cpu_has_local_ebase 133 #define cpu_has_local_ebase 1 134 #endif 135 136 /* 137 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 138 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 139 * don't. For maintaining I-cache coherency this means we need to flush the 140 * D-cache all the way back to whever the I-cache does refills from, so the 141 * I-cache has a chance to see the new data at all. Then we have to flush the 142 * I-cache also. 143 * Note we may have been rescheduled and may no longer be running on the CPU 144 * that did the store so we can't optimize this into only doing the flush on 145 * the local CPU. 146 */ 147 #ifndef cpu_icache_snoops_remote_store 148 #ifdef CONFIG_SMP 149 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 150 #else 151 #define cpu_icache_snoops_remote_store 1 152 #endif 153 #endif 154 155 #ifndef cpu_has_mips_2 156 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 157 #endif 158 #ifndef cpu_has_mips_3 159 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 160 #endif 161 #ifndef cpu_has_mips_4 162 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 163 #endif 164 #ifndef cpu_has_mips_5 165 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 166 #endif 167 #ifndef cpu_has_mips32r1 168 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 169 #endif 170 #ifndef cpu_has_mips32r2 171 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 172 #endif 173 #ifndef cpu_has_mips64r1 174 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 175 #endif 176 #ifndef cpu_has_mips64r2 177 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 178 #endif 179 180 /* 181 * Shortcuts ... 182 */ 183 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) 184 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 185 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 186 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 187 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 188 cpu_has_mips64r1 | cpu_has_mips64r2) 189 190 #ifndef cpu_has_mips_r2_exec_hazard 191 #define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 192 #endif 193 194 /* 195 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 196 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 197 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 198 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 199 */ 200 #ifndef cpu_has_clo_clz 201 #define cpu_has_clo_clz cpu_has_mips_r 202 #endif 203 204 #ifndef cpu_has_dsp 205 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 206 #endif 207 208 #ifndef cpu_has_dsp2 209 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) 210 #endif 211 212 #ifndef cpu_has_mipsmt 213 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 214 #endif 215 216 #ifndef cpu_has_userlocal 217 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 218 #endif 219 220 #ifdef CONFIG_32BIT 221 # ifndef cpu_has_nofpuex 222 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 223 # endif 224 # ifndef cpu_has_64bits 225 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 226 # endif 227 # ifndef cpu_has_64bit_zero_reg 228 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 229 # endif 230 # ifndef cpu_has_64bit_gp_regs 231 # define cpu_has_64bit_gp_regs 0 232 # endif 233 # ifndef cpu_has_64bit_addresses 234 # define cpu_has_64bit_addresses 0 235 # endif 236 # ifndef cpu_vmbits 237 # define cpu_vmbits 31 238 # endif 239 #endif 240 241 #ifdef CONFIG_64BIT 242 # ifndef cpu_has_nofpuex 243 # define cpu_has_nofpuex 0 244 # endif 245 # ifndef cpu_has_64bits 246 # define cpu_has_64bits 1 247 # endif 248 # ifndef cpu_has_64bit_zero_reg 249 # define cpu_has_64bit_zero_reg 1 250 # endif 251 # ifndef cpu_has_64bit_gp_regs 252 # define cpu_has_64bit_gp_regs 1 253 # endif 254 # ifndef cpu_has_64bit_addresses 255 # define cpu_has_64bit_addresses 1 256 # endif 257 # ifndef cpu_vmbits 258 # define cpu_vmbits cpu_data[0].vmbits 259 # define __NEED_VMBITS_PROBE 260 # endif 261 #endif 262 263 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 264 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 265 #elif !defined(cpu_has_vint) 266 # define cpu_has_vint 0 267 #endif 268 269 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 270 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 271 #elif !defined(cpu_has_veic) 272 # define cpu_has_veic 0 273 #endif 274 275 #ifndef cpu_has_inclusive_pcaches 276 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 277 #endif 278 279 #ifndef cpu_dcache_line_size 280 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 281 #endif 282 #ifndef cpu_icache_line_size 283 #define cpu_icache_line_size() cpu_data[0].icache.linesz 284 #endif 285 #ifndef cpu_scache_line_size 286 #define cpu_scache_line_size() cpu_data[0].scache.linesz 287 #endif 288 289 #ifndef cpu_hwrena_impl_bits 290 #define cpu_hwrena_impl_bits 0 291 #endif 292 293 #ifndef cpu_has_perf_cntr_intr_bit 294 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 295 #endif 296 297 #ifndef cpu_has_vz 298 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) 299 #endif 300 301 #endif /* __ASM_CPU_FEATURES_H */ 302