1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <cpu-feature-overrides.h> 15 16 #ifndef current_cpu_type 17 #define current_cpu_type() current_cpu_data.cputype 18 #endif 19 20 /* 21 * SMP assumption: Options of CPU 0 are a superset of all processors. 22 * This is true for all known MIPS systems. 23 */ 24 #ifndef cpu_has_tlb 25 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 26 #endif 27 #ifndef cpu_has_4kex 28 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 29 #endif 30 #ifndef cpu_has_3k_cache 31 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 32 #endif 33 #define cpu_has_6k_cache 0 34 #define cpu_has_8k_cache 0 35 #ifndef cpu_has_4k_cache 36 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 37 #endif 38 #ifndef cpu_has_tx39_cache 39 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 40 #endif 41 #ifndef cpu_has_octeon_cache 42 #define cpu_has_octeon_cache 0 43 #endif 44 #ifndef cpu_has_fpu 45 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 46 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 47 #else 48 #define raw_cpu_has_fpu cpu_has_fpu 49 #endif 50 #ifndef cpu_has_32fpr 51 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 52 #endif 53 #ifndef cpu_has_counter 54 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 55 #endif 56 #ifndef cpu_has_watch 57 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 58 #endif 59 #ifndef cpu_has_divec 60 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 61 #endif 62 #ifndef cpu_has_vce 63 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 64 #endif 65 #ifndef cpu_has_cache_cdex_p 66 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 67 #endif 68 #ifndef cpu_has_cache_cdex_s 69 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 70 #endif 71 #ifndef cpu_has_prefetch 72 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 73 #endif 74 #ifndef cpu_has_mcheck 75 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 76 #endif 77 #ifndef cpu_has_ejtag 78 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 79 #endif 80 #ifndef cpu_has_llsc 81 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 82 #endif 83 #ifndef cpu_has_mips16 84 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 85 #endif 86 #ifndef cpu_has_mdmx 87 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 88 #endif 89 #ifndef cpu_has_mips3d 90 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 91 #endif 92 #ifndef cpu_has_smartmips 93 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 94 #endif 95 #ifndef cpu_has_vtag_icache 96 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 97 #endif 98 #ifndef cpu_has_dc_aliases 99 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 100 #endif 101 #ifndef cpu_has_ic_fills_f_dc 102 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 103 #endif 104 #ifndef cpu_has_pindexed_dcache 105 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 106 #endif 107 108 /* 109 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 110 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 111 * don't. For maintaining I-cache coherency this means we need to flush the 112 * D-cache all the way back to whever the I-cache does refills from, so the 113 * I-cache has a chance to see the new data at all. Then we have to flush the 114 * I-cache also. 115 * Note we may have been rescheduled and may no longer be running on the CPU 116 * that did the store so we can't optimize this into only doing the flush on 117 * the local CPU. 118 */ 119 #ifndef cpu_icache_snoops_remote_store 120 #ifdef CONFIG_SMP 121 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 122 #else 123 #define cpu_icache_snoops_remote_store 1 124 #endif 125 #endif 126 127 # ifndef cpu_has_mips32r1 128 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 129 # endif 130 # ifndef cpu_has_mips32r2 131 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 132 # endif 133 # ifndef cpu_has_mips64r1 134 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 135 # endif 136 # ifndef cpu_has_mips64r2 137 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 138 # endif 139 140 /* 141 * Shortcuts ... 142 */ 143 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) 144 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 145 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 146 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 147 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 148 cpu_has_mips64r1 | cpu_has_mips64r2) 149 150 #ifndef cpu_has_dsp 151 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 152 #endif 153 154 #ifndef cpu_has_mipsmt 155 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 156 #endif 157 158 #ifndef cpu_has_userlocal 159 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 160 #endif 161 162 #ifdef CONFIG_32BIT 163 # ifndef cpu_has_nofpuex 164 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 165 # endif 166 # ifndef cpu_has_64bits 167 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 168 # endif 169 # ifndef cpu_has_64bit_zero_reg 170 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 171 # endif 172 # ifndef cpu_has_64bit_gp_regs 173 # define cpu_has_64bit_gp_regs 0 174 # endif 175 # ifndef cpu_has_64bit_addresses 176 # define cpu_has_64bit_addresses 0 177 # endif 178 #endif 179 180 #ifdef CONFIG_64BIT 181 # ifndef cpu_has_nofpuex 182 # define cpu_has_nofpuex 0 183 # endif 184 # ifndef cpu_has_64bits 185 # define cpu_has_64bits 1 186 # endif 187 # ifndef cpu_has_64bit_zero_reg 188 # define cpu_has_64bit_zero_reg 1 189 # endif 190 # ifndef cpu_has_64bit_gp_regs 191 # define cpu_has_64bit_gp_regs 1 192 # endif 193 # ifndef cpu_has_64bit_addresses 194 # define cpu_has_64bit_addresses 1 195 # endif 196 #endif 197 198 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 199 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 200 #elif !defined(cpu_has_vint) 201 # define cpu_has_vint 0 202 #endif 203 204 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 205 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 206 #elif !defined(cpu_has_veic) 207 # define cpu_has_veic 0 208 #endif 209 210 #ifndef cpu_has_inclusive_pcaches 211 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 212 #endif 213 214 #ifndef cpu_dcache_line_size 215 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 216 #endif 217 #ifndef cpu_icache_line_size 218 #define cpu_icache_line_size() cpu_data[0].icache.linesz 219 #endif 220 #ifndef cpu_scache_line_size 221 #define cpu_scache_line_size() cpu_data[0].scache.linesz 222 #endif 223 224 #endif /* __ASM_CPU_FEATURES_H */ 225