1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2003, 2004 Ralf Baechle
7  * Copyright (C) 2004  Maciej W. Rozycki
8  */
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
11 
12 #include <asm/cpu.h>
13 #include <asm/cpu-info.h>
14 #include <asm/isa-rev.h>
15 #include <cpu-feature-overrides.h>
16 
17 #define __ase(ase)			(cpu_data[0].ases & (ase))
18 #define __isa(isa)			(cpu_data[0].isa_level & (isa))
19 #define __opt(opt)			(cpu_data[0].options & (opt))
20 
21 /*
22  * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during
23  * boot (typically by cpu_probe()).
24  *
25  * Note that these should only be used in cases where a kernel built for an
26  * older ISA *cannot* run on a CPU which supports the feature in question. For
27  * example this may be used for features introduced with MIPSr6, since a kernel
28  * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
29  * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
30  * MIPSr2 CPU.
31  */
32 #define __isa_ge_and_ase(isa, ase)	((MIPS_ISA_REV >= (isa)) && __ase(ase))
33 #define __isa_ge_and_opt(isa, opt)	((MIPS_ISA_REV >= (isa)) && __opt(opt))
34 
35 /*
36  * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during
37  * boot (typically by cpu_probe()).
38  *
39  * These are for use with features that are optional up until a particular ISA
40  * revision & then become required.
41  */
42 #define __isa_ge_or_ase(isa, ase)	((MIPS_ISA_REV >= (isa)) || __ase(ase))
43 #define __isa_ge_or_opt(isa, opt)	((MIPS_ISA_REV >= (isa)) || __opt(opt))
44 
45 /*
46  * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during
47  * boot (typically by cpu_probe()).
48  *
49  * These are for use with features that are optional up until a particular ISA
50  * revision & are then removed - ie. no longer present in any CPU implementing
51  * the given ISA revision.
52  */
53 #define __isa_lt_and_ase(isa, ase)	((MIPS_ISA_REV < (isa)) && __ase(ase))
54 #define __isa_lt_and_opt(isa, opt)	((MIPS_ISA_REV < (isa)) && __opt(opt))
55 
56 /*
57  * Similarly allow for ISA level checks that take into account knowledge of the
58  * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
59  */
60 #define __isa_ge_and_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) && __isa(flag))
61 #define __isa_ge_or_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) || __isa(flag))
62 #define __isa_lt_and_flag(isa, flag)	((MIPS_ISA_REV < (isa)) && __isa(flag))
63 #define __isa_range(ge, lt) \
64 	((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
65 #define __isa_range_or_flag(ge, lt, flag) \
66 	(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
67 #define __isa_range_and_ase(ge, lt, ase) \
68 	(__isa_range(ge, lt) && __ase(ase))
69 
70 /*
71  * SMP assumption: Options of CPU 0 are a superset of all processors.
72  * This is true for all known MIPS systems.
73  */
74 #ifndef cpu_has_tlb
75 #define cpu_has_tlb		__opt(MIPS_CPU_TLB)
76 #endif
77 #ifndef cpu_has_ftlb
78 #define cpu_has_ftlb		__opt(MIPS_CPU_FTLB)
79 #endif
80 #ifndef cpu_has_tlbinv
81 #define cpu_has_tlbinv		__opt(MIPS_CPU_TLBINV)
82 #endif
83 #ifndef cpu_has_segments
84 #define cpu_has_segments	__opt(MIPS_CPU_SEGMENTS)
85 #endif
86 #ifndef cpu_has_eva
87 #define cpu_has_eva		__opt(MIPS_CPU_EVA)
88 #endif
89 #ifndef cpu_has_htw
90 #define cpu_has_htw		__opt(MIPS_CPU_HTW)
91 #endif
92 #ifndef cpu_has_ldpte
93 #define cpu_has_ldpte		__opt(MIPS_CPU_LDPTE)
94 #endif
95 #ifndef cpu_has_rixiex
96 #define cpu_has_rixiex		__isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
97 #endif
98 #ifndef cpu_has_maar
99 #define cpu_has_maar		__opt(MIPS_CPU_MAAR)
100 #endif
101 #ifndef cpu_has_rw_llb
102 #define cpu_has_rw_llb		__isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
103 #endif
104 
105 /*
106  * For the moment we don't consider R6000 and R8000 so we can assume that
107  * anything that doesn't support R4000-style exceptions and interrupts is
108  * R3000-like.  Users should still treat these two macro definitions as
109  * opaque.
110  */
111 #ifndef cpu_has_3kex
112 #define cpu_has_3kex		(!cpu_has_4kex)
113 #endif
114 #ifndef cpu_has_4kex
115 #define cpu_has_4kex		__isa_ge_or_opt(1, MIPS_CPU_4KEX)
116 #endif
117 #ifndef cpu_has_3k_cache
118 #define cpu_has_3k_cache	__isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
119 #endif
120 #ifndef cpu_has_4k_cache
121 #define cpu_has_4k_cache	__isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
122 #endif
123 #ifndef cpu_has_tx39_cache
124 #define cpu_has_tx39_cache	__opt(MIPS_CPU_TX39_CACHE)
125 #endif
126 #ifndef cpu_has_octeon_cache
127 #define cpu_has_octeon_cache	0
128 #endif
129 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
130 #ifndef cpu_has_fpu
131 # ifdef CONFIG_MIPS_FP_SUPPORT
132 #  define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
133 #  define raw_cpu_has_fpu	(raw_current_cpu_data.options & MIPS_CPU_FPU)
134 # else
135 #  define cpu_has_fpu		0
136 #  define raw_cpu_has_fpu	0
137 # endif
138 #else
139 # define raw_cpu_has_fpu	cpu_has_fpu
140 #endif
141 #ifndef cpu_has_32fpr
142 #define cpu_has_32fpr		__isa_ge_or_opt(1, MIPS_CPU_32FPR)
143 #endif
144 #ifndef cpu_has_counter
145 #define cpu_has_counter		__opt(MIPS_CPU_COUNTER)
146 #endif
147 #ifndef cpu_has_watch
148 #define cpu_has_watch		__opt(MIPS_CPU_WATCH)
149 #endif
150 #ifndef cpu_has_divec
151 #define cpu_has_divec		__isa_ge_or_opt(1, MIPS_CPU_DIVEC)
152 #endif
153 #ifndef cpu_has_vce
154 #define cpu_has_vce		__opt(MIPS_CPU_VCE)
155 #endif
156 #ifndef cpu_has_cache_cdex_p
157 #define cpu_has_cache_cdex_p	__opt(MIPS_CPU_CACHE_CDEX_P)
158 #endif
159 #ifndef cpu_has_cache_cdex_s
160 #define cpu_has_cache_cdex_s	__opt(MIPS_CPU_CACHE_CDEX_S)
161 #endif
162 #ifndef cpu_has_prefetch
163 #define cpu_has_prefetch	__isa_ge_or_opt(1, MIPS_CPU_PREFETCH)
164 #endif
165 #ifndef cpu_has_mcheck
166 #define cpu_has_mcheck		__isa_ge_or_opt(1, MIPS_CPU_MCHECK)
167 #endif
168 #ifndef cpu_has_ejtag
169 #define cpu_has_ejtag		__opt(MIPS_CPU_EJTAG)
170 #endif
171 #ifndef cpu_has_llsc
172 #define cpu_has_llsc		__isa_ge_or_opt(1, MIPS_CPU_LLSC)
173 #endif
174 #ifndef kernel_uses_llsc
175 #define kernel_uses_llsc	cpu_has_llsc
176 #endif
177 #ifndef cpu_has_guestctl0ext
178 #define cpu_has_guestctl0ext	__opt(MIPS_CPU_GUESTCTL0EXT)
179 #endif
180 #ifndef cpu_has_guestctl1
181 #define cpu_has_guestctl1	__opt(MIPS_CPU_GUESTCTL1)
182 #endif
183 #ifndef cpu_has_guestctl2
184 #define cpu_has_guestctl2	__opt(MIPS_CPU_GUESTCTL2)
185 #endif
186 #ifndef cpu_has_guestid
187 #define cpu_has_guestid		__opt(MIPS_CPU_GUESTID)
188 #endif
189 #ifndef cpu_has_drg
190 #define cpu_has_drg		__opt(MIPS_CPU_DRG)
191 #endif
192 #ifndef cpu_has_mips16
193 #define cpu_has_mips16		__isa_lt_and_ase(6, MIPS_ASE_MIPS16)
194 #endif
195 #ifndef cpu_has_mips16e2
196 #define cpu_has_mips16e2	__isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
197 #endif
198 #ifndef cpu_has_mdmx
199 #define cpu_has_mdmx		__isa_lt_and_ase(6, MIPS_ASE_MDMX)
200 #endif
201 #ifndef cpu_has_mips3d
202 #define cpu_has_mips3d		__isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
203 #endif
204 #ifndef cpu_has_smartmips
205 #define cpu_has_smartmips	__isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
206 #endif
207 
208 #ifndef cpu_has_rixi
209 #define cpu_has_rixi		__isa_ge_or_opt(6, MIPS_CPU_RIXI)
210 #endif
211 
212 #ifndef cpu_has_mmips
213 # if defined(__mips_micromips)
214 #  define cpu_has_mmips		1
215 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
216 #  define cpu_has_mmips		__opt(MIPS_CPU_MICROMIPS)
217 # else
218 #  define cpu_has_mmips		0
219 # endif
220 #endif
221 
222 #ifndef cpu_has_lpa
223 #define cpu_has_lpa		__opt(MIPS_CPU_LPA)
224 #endif
225 #ifndef cpu_has_mvh
226 #define cpu_has_mvh		__opt(MIPS_CPU_MVH)
227 #endif
228 #ifndef cpu_has_xpa
229 #define cpu_has_xpa		(cpu_has_lpa && cpu_has_mvh)
230 #endif
231 #ifndef cpu_has_vtag_icache
232 #define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
233 #endif
234 #ifndef cpu_has_dc_aliases
235 #define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
236 #endif
237 #ifndef cpu_has_ic_fills_f_dc
238 #define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
239 #endif
240 #ifndef cpu_has_pindexed_dcache
241 #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
242 #endif
243 
244 /*
245  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
246  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
247  * don't.  For maintaining I-cache coherency this means we need to flush the
248  * D-cache all the way back to whever the I-cache does refills from, so the
249  * I-cache has a chance to see the new data at all.  Then we have to flush the
250  * I-cache also.
251  * Note we may have been rescheduled and may no longer be running on the CPU
252  * that did the store so we can't optimize this into only doing the flush on
253  * the local CPU.
254  */
255 #ifndef cpu_icache_snoops_remote_store
256 #ifdef CONFIG_SMP
257 #define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
258 #else
259 #define cpu_icache_snoops_remote_store	1
260 #endif
261 #endif
262 
263 #ifndef cpu_has_mips_1
264 # define cpu_has_mips_1		(MIPS_ISA_REV < 6)
265 #endif
266 #ifndef cpu_has_mips_2
267 # define cpu_has_mips_2		__isa_lt_and_flag(6, MIPS_CPU_ISA_II)
268 #endif
269 #ifndef cpu_has_mips_3
270 # define cpu_has_mips_3		__isa_lt_and_flag(6, MIPS_CPU_ISA_III)
271 #endif
272 #ifndef cpu_has_mips_4
273 # define cpu_has_mips_4		__isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
274 #endif
275 #ifndef cpu_has_mips_5
276 # define cpu_has_mips_5		__isa_lt_and_flag(6, MIPS_CPU_ISA_V)
277 #endif
278 #ifndef cpu_has_mips32r1
279 # define cpu_has_mips32r1	__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
280 #endif
281 #ifndef cpu_has_mips32r2
282 # define cpu_has_mips32r2	__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
283 #endif
284 #ifndef cpu_has_mips32r5
285 # define cpu_has_mips32r5	__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
286 #endif
287 #ifndef cpu_has_mips32r6
288 # define cpu_has_mips32r6	__isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
289 #endif
290 #ifndef cpu_has_mips64r1
291 # define cpu_has_mips64r1	(cpu_has_64bits && \
292 				 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
293 #endif
294 #ifndef cpu_has_mips64r2
295 # define cpu_has_mips64r2	(cpu_has_64bits && \
296 				 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
297 #endif
298 #ifndef cpu_has_mips64r5
299 # define cpu_has_mips64r5	(cpu_has_64bits && \
300 				 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
301 #endif
302 #ifndef cpu_has_mips64r6
303 # define cpu_has_mips64r6	__isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
304 #endif
305 
306 /*
307  * Shortcuts ...
308  */
309 #define cpu_has_mips_2_3_4_5	(cpu_has_mips_2 | cpu_has_mips_3_4_5)
310 #define cpu_has_mips_3_4_5	(cpu_has_mips_3 | cpu_has_mips_4_5)
311 #define cpu_has_mips_4_5	(cpu_has_mips_4 | cpu_has_mips_5)
312 
313 #define cpu_has_mips_2_3_4_5_r	(cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
314 #define cpu_has_mips_3_4_5_r	(cpu_has_mips_3 | cpu_has_mips_4_5_r)
315 #define cpu_has_mips_4_5_r	(cpu_has_mips_4 | cpu_has_mips_5_r)
316 #define cpu_has_mips_5_r	(cpu_has_mips_5 | cpu_has_mips_r)
317 
318 #define cpu_has_mips_3_4_5_64_r2_r6					\
319 				(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
320 #define cpu_has_mips_4_5_64_r2_r6					\
321 				(cpu_has_mips_4_5 | cpu_has_mips64r1 |	\
322 				 cpu_has_mips_r2 | cpu_has_mips_r5 | \
323 				 cpu_has_mips_r6)
324 
325 #define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
326 			 cpu_has_mips32r5 | cpu_has_mips32r6)
327 #define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | \
328 			 cpu_has_mips64r5 | cpu_has_mips64r6)
329 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
330 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
331 #define cpu_has_mips_r5	(cpu_has_mips32r5 | cpu_has_mips64r5)
332 #define cpu_has_mips_r6	(cpu_has_mips32r6 | cpu_has_mips64r6)
333 #define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
334 			 cpu_has_mips32r5 | cpu_has_mips32r6 | \
335 			 cpu_has_mips64r1 | cpu_has_mips64r2 | \
336 			 cpu_has_mips64r5 | cpu_has_mips64r6)
337 
338 /* MIPSR2 - MIPSR6 have a lot of similarities */
339 #define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r5 | \
340 				 cpu_has_mips_r6)
341 
342 /*
343  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
344  *
345  * Returns non-zero value if the current processor implementation requires
346  * an IHB instruction to deal with an instruction hazard as per MIPS R2
347  * architecture specification, zero otherwise.
348  */
349 #ifndef cpu_has_mips_r2_exec_hazard
350 #define cpu_has_mips_r2_exec_hazard					\
351 ({									\
352 	int __res;							\
353 									\
354 	switch (current_cpu_type()) {					\
355 	case CPU_M14KC:							\
356 	case CPU_74K:							\
357 	case CPU_1074K:							\
358 	case CPU_PROAPTIV:						\
359 	case CPU_P5600:							\
360 	case CPU_M5150:							\
361 	case CPU_QEMU_GENERIC:						\
362 	case CPU_CAVIUM_OCTEON:						\
363 	case CPU_CAVIUM_OCTEON_PLUS:					\
364 	case CPU_CAVIUM_OCTEON2:					\
365 	case CPU_CAVIUM_OCTEON3:					\
366 		__res = 0;						\
367 		break;							\
368 									\
369 	default:							\
370 		__res = 1;						\
371 	}								\
372 									\
373 	__res;								\
374 })
375 #endif
376 
377 /*
378  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
379  * pre-MIPS32/MIPS64 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
380  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
381  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
382  */
383 #ifndef cpu_has_clo_clz
384 #define cpu_has_clo_clz	cpu_has_mips_r
385 #endif
386 
387 /*
388  * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
389  * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
390  * This indicates the availability of WSBH and in case of 64 bit CPUs also
391  * DSBH and DSHD.
392  */
393 #ifndef cpu_has_wsbh
394 #define cpu_has_wsbh		cpu_has_mips_r2
395 #endif
396 
397 #ifndef cpu_has_dsp
398 #define cpu_has_dsp		__ase(MIPS_ASE_DSP)
399 #endif
400 
401 #ifndef cpu_has_dsp2
402 #define cpu_has_dsp2		__ase(MIPS_ASE_DSP2P)
403 #endif
404 
405 #ifndef cpu_has_dsp3
406 #define cpu_has_dsp3		__ase(MIPS_ASE_DSP3)
407 #endif
408 
409 #ifndef cpu_has_loongson_mmi
410 #define cpu_has_loongson_mmi		__ase(MIPS_ASE_LOONGSON_MMI)
411 #endif
412 
413 #ifndef cpu_has_loongson_cam
414 #define cpu_has_loongson_cam		__ase(MIPS_ASE_LOONGSON_CAM)
415 #endif
416 
417 #ifndef cpu_has_loongson_ext
418 #define cpu_has_loongson_ext		__ase(MIPS_ASE_LOONGSON_EXT)
419 #endif
420 
421 #ifndef cpu_has_loongson_ext2
422 #define cpu_has_loongson_ext2		__ase(MIPS_ASE_LOONGSON_EXT2)
423 #endif
424 
425 #ifndef cpu_has_mipsmt
426 #define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
427 #endif
428 
429 #ifndef cpu_has_vp
430 #define cpu_has_vp		__isa_ge_and_opt(6, MIPS_CPU_VP)
431 #endif
432 
433 #ifndef cpu_has_userlocal
434 #define cpu_has_userlocal	__isa_ge_or_opt(6, MIPS_CPU_ULRI)
435 #endif
436 
437 #ifdef CONFIG_32BIT
438 # ifndef cpu_has_nofpuex
439 # define cpu_has_nofpuex	__isa_lt_and_opt(1, MIPS_CPU_NOFPUEX)
440 # endif
441 # ifndef cpu_has_64bits
442 # define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
443 # endif
444 # ifndef cpu_has_64bit_zero_reg
445 # define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
446 # endif
447 # ifndef cpu_has_64bit_gp_regs
448 # define cpu_has_64bit_gp_regs		0
449 # endif
450 # ifndef cpu_vmbits
451 # define cpu_vmbits 31
452 # endif
453 #endif
454 
455 #ifdef CONFIG_64BIT
456 # ifndef cpu_has_nofpuex
457 # define cpu_has_nofpuex		0
458 # endif
459 # ifndef cpu_has_64bits
460 # define cpu_has_64bits			1
461 # endif
462 # ifndef cpu_has_64bit_zero_reg
463 # define cpu_has_64bit_zero_reg		1
464 # endif
465 # ifndef cpu_has_64bit_gp_regs
466 # define cpu_has_64bit_gp_regs		1
467 # endif
468 # ifndef cpu_vmbits
469 # define cpu_vmbits cpu_data[0].vmbits
470 # define __NEED_VMBITS_PROBE
471 # endif
472 #endif
473 
474 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
475 # define cpu_has_vint		__opt(MIPS_CPU_VINT)
476 #elif !defined(cpu_has_vint)
477 # define cpu_has_vint			0
478 #endif
479 
480 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
481 # define cpu_has_veic		__opt(MIPS_CPU_VEIC)
482 #elif !defined(cpu_has_veic)
483 # define cpu_has_veic			0
484 #endif
485 
486 #ifndef cpu_has_inclusive_pcaches
487 #define cpu_has_inclusive_pcaches	__opt(MIPS_CPU_INCLUSIVE_CACHES)
488 #endif
489 
490 #ifndef cpu_dcache_line_size
491 #define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
492 #endif
493 #ifndef cpu_icache_line_size
494 #define cpu_icache_line_size()	cpu_data[0].icache.linesz
495 #endif
496 #ifndef cpu_scache_line_size
497 #define cpu_scache_line_size()	cpu_data[0].scache.linesz
498 #endif
499 #ifndef cpu_tcache_line_size
500 #define cpu_tcache_line_size()	cpu_data[0].tcache.linesz
501 #endif
502 
503 #ifndef cpu_hwrena_impl_bits
504 #define cpu_hwrena_impl_bits		0
505 #endif
506 
507 #ifndef cpu_has_perf_cntr_intr_bit
508 #define cpu_has_perf_cntr_intr_bit	__opt(MIPS_CPU_PCI)
509 #endif
510 
511 #ifndef cpu_has_vz
512 #define cpu_has_vz		__ase(MIPS_ASE_VZ)
513 #endif
514 
515 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
516 # define cpu_has_msa		__ase(MIPS_ASE_MSA)
517 #elif !defined(cpu_has_msa)
518 # define cpu_has_msa		0
519 #endif
520 
521 #ifndef cpu_has_ufr
522 # define cpu_has_ufr		__opt(MIPS_CPU_UFR)
523 #endif
524 
525 #ifndef cpu_has_fre
526 # define cpu_has_fre		__opt(MIPS_CPU_FRE)
527 #endif
528 
529 #ifndef cpu_has_cdmm
530 # define cpu_has_cdmm		__opt(MIPS_CPU_CDMM)
531 #endif
532 
533 #ifndef cpu_has_small_pages
534 # define cpu_has_small_pages	__opt(MIPS_CPU_SP)
535 #endif
536 
537 #ifndef cpu_has_nan_legacy
538 #define cpu_has_nan_legacy	__isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
539 #endif
540 #ifndef cpu_has_nan_2008
541 #define cpu_has_nan_2008	__isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
542 #endif
543 
544 #ifndef cpu_has_ebase_wg
545 # define cpu_has_ebase_wg	__opt(MIPS_CPU_EBASE_WG)
546 #endif
547 
548 #ifndef cpu_has_badinstr
549 # define cpu_has_badinstr	__isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
550 #endif
551 
552 #ifndef cpu_has_badinstrp
553 # define cpu_has_badinstrp	__isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
554 #endif
555 
556 #ifndef cpu_has_contextconfig
557 # define cpu_has_contextconfig	__opt(MIPS_CPU_CTXTC)
558 #endif
559 
560 #ifndef cpu_has_perf
561 # define cpu_has_perf		__opt(MIPS_CPU_PERF)
562 #endif
563 
564 #ifndef cpu_has_mac2008_only
565 # define cpu_has_mac2008_only	__opt(MIPS_CPU_MAC_2008_ONLY)
566 #endif
567 
568 #ifndef cpu_has_ftlbparex
569 # define cpu_has_ftlbparex	__opt(MIPS_CPU_FTLBPAREX)
570 #endif
571 
572 #ifndef cpu_has_gsexcex
573 # define cpu_has_gsexcex	__opt(MIPS_CPU_GSEXCEX)
574 #endif
575 
576 #ifdef CONFIG_SMP
577 /*
578  * Some systems share FTLB RAMs between threads within a core (siblings in
579  * kernel parlance). This means that FTLB entries may become invalid at almost
580  * any point when an entry is evicted due to a sibling thread writing an entry
581  * to the shared FTLB RAM.
582  *
583  * This is only relevant to SMP systems, and the only systems that exhibit this
584  * property implement MIPSr6 or higher so we constrain support for this to
585  * kernels that will run on such systems.
586  */
587 # ifndef cpu_has_shared_ftlb_ram
588 #  define cpu_has_shared_ftlb_ram \
589 	__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
590 # endif
591 
592 /*
593  * Some systems take this a step further & share FTLB entries between siblings.
594  * This is implemented as TLB writes happening as usual, but if an entry
595  * written by a sibling exists in the shared FTLB for a translation which would
596  * otherwise cause a TLB refill exception then the CPU will use the entry
597  * written by its sibling rather than triggering a refill & writing a matching
598  * TLB entry for itself.
599  *
600  * This is naturally only valid if a TLB entry is known to be suitable for use
601  * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
602  * rather than ASIDs or when a TLB entry is marked global.
603  */
604 # ifndef cpu_has_shared_ftlb_entries
605 #  define cpu_has_shared_ftlb_entries \
606 	__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
607 # endif
608 #endif /* SMP */
609 
610 #ifndef cpu_has_shared_ftlb_ram
611 # define cpu_has_shared_ftlb_ram 0
612 #endif
613 #ifndef cpu_has_shared_ftlb_entries
614 # define cpu_has_shared_ftlb_entries 0
615 #endif
616 
617 #ifdef CONFIG_MIPS_MT_SMP
618 # define cpu_has_mipsmt_pertccounters \
619 	__isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
620 #else
621 # define cpu_has_mipsmt_pertccounters 0
622 #endif /* CONFIG_MIPS_MT_SMP */
623 
624 /*
625  * We only enable MMID support for configurations which natively support 64 bit
626  * atomics because getting good performance from the allocator relies upon
627  * efficient atomic64_*() functions.
628  */
629 #ifndef cpu_has_mmid
630 # ifdef CONFIG_GENERIC_ATOMIC64
631 #  define cpu_has_mmid		0
632 # else
633 #  define cpu_has_mmid		__isa_ge_and_opt(6, MIPS_CPU_MMID)
634 # endif
635 #endif
636 
637 #ifndef cpu_has_mm_sysad
638 # define cpu_has_mm_sysad	__opt(MIPS_CPU_MM_SYSAD)
639 #endif
640 
641 #ifndef cpu_has_mm_full
642 # define cpu_has_mm_full	__opt(MIPS_CPU_MM_FULL)
643 #endif
644 
645 /*
646  * Guest capabilities
647  */
648 #ifndef cpu_guest_has_conf1
649 #define cpu_guest_has_conf1	(cpu_data[0].guest.conf & (1 << 1))
650 #endif
651 #ifndef cpu_guest_has_conf2
652 #define cpu_guest_has_conf2	(cpu_data[0].guest.conf & (1 << 2))
653 #endif
654 #ifndef cpu_guest_has_conf3
655 #define cpu_guest_has_conf3	(cpu_data[0].guest.conf & (1 << 3))
656 #endif
657 #ifndef cpu_guest_has_conf4
658 #define cpu_guest_has_conf4	(cpu_data[0].guest.conf & (1 << 4))
659 #endif
660 #ifndef cpu_guest_has_conf5
661 #define cpu_guest_has_conf5	(cpu_data[0].guest.conf & (1 << 5))
662 #endif
663 #ifndef cpu_guest_has_conf6
664 #define cpu_guest_has_conf6	(cpu_data[0].guest.conf & (1 << 6))
665 #endif
666 #ifndef cpu_guest_has_conf7
667 #define cpu_guest_has_conf7	(cpu_data[0].guest.conf & (1 << 7))
668 #endif
669 #ifndef cpu_guest_has_fpu
670 #define cpu_guest_has_fpu	(cpu_data[0].guest.options & MIPS_CPU_FPU)
671 #endif
672 #ifndef cpu_guest_has_watch
673 #define cpu_guest_has_watch	(cpu_data[0].guest.options & MIPS_CPU_WATCH)
674 #endif
675 #ifndef cpu_guest_has_contextconfig
676 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
677 #endif
678 #ifndef cpu_guest_has_segments
679 #define cpu_guest_has_segments	(cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
680 #endif
681 #ifndef cpu_guest_has_badinstr
682 #define cpu_guest_has_badinstr	(cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
683 #endif
684 #ifndef cpu_guest_has_badinstrp
685 #define cpu_guest_has_badinstrp	(cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
686 #endif
687 #ifndef cpu_guest_has_htw
688 #define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)
689 #endif
690 #ifndef cpu_guest_has_ldpte
691 #define cpu_guest_has_ldpte	(cpu_data[0].guest.options & MIPS_CPU_LDPTE)
692 #endif
693 #ifndef cpu_guest_has_mvh
694 #define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)
695 #endif
696 #ifndef cpu_guest_has_msa
697 #define cpu_guest_has_msa	(cpu_data[0].guest.ases & MIPS_ASE_MSA)
698 #endif
699 #ifndef cpu_guest_has_kscr
700 #define cpu_guest_has_kscr(n)	(cpu_data[0].guest.kscratch_mask & (1u << (n)))
701 #endif
702 #ifndef cpu_guest_has_rw_llb
703 #define cpu_guest_has_rw_llb	(cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
704 #endif
705 #ifndef cpu_guest_has_perf
706 #define cpu_guest_has_perf	(cpu_data[0].guest.options & MIPS_CPU_PERF)
707 #endif
708 #ifndef cpu_guest_has_maar
709 #define cpu_guest_has_maar	(cpu_data[0].guest.options & MIPS_CPU_MAAR)
710 #endif
711 #ifndef cpu_guest_has_userlocal
712 #define cpu_guest_has_userlocal	(cpu_data[0].guest.options & MIPS_CPU_ULRI)
713 #endif
714 
715 /*
716  * Guest dynamic capabilities
717  */
718 #ifndef cpu_guest_has_dyn_fpu
719 #define cpu_guest_has_dyn_fpu	(cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
720 #endif
721 #ifndef cpu_guest_has_dyn_watch
722 #define cpu_guest_has_dyn_watch	(cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
723 #endif
724 #ifndef cpu_guest_has_dyn_contextconfig
725 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
726 #endif
727 #ifndef cpu_guest_has_dyn_perf
728 #define cpu_guest_has_dyn_perf	(cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
729 #endif
730 #ifndef cpu_guest_has_dyn_msa
731 #define cpu_guest_has_dyn_msa	(cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
732 #endif
733 #ifndef cpu_guest_has_dyn_maar
734 #define cpu_guest_has_dyn_maar	(cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
735 #endif
736 
737 #endif /* __ASM_CPU_FEATURES_H */
738