1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <cpu-feature-overrides.h> 15 16 /* 17 * SMP assumption: Options of CPU 0 are a superset of all processors. 18 * This is true for all known MIPS systems. 19 */ 20 #ifndef cpu_has_tlb 21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 22 #endif 23 #ifndef cpu_has_ftlb 24 #define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB) 25 #endif 26 #ifndef cpu_has_tlbinv 27 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) 28 #endif 29 #ifndef cpu_has_segments 30 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) 31 #endif 32 #ifndef cpu_has_eva 33 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) 34 #endif 35 #ifndef cpu_has_htw 36 #define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW) 37 #endif 38 #ifndef cpu_has_ldpte 39 #define cpu_has_ldpte (cpu_data[0].options & MIPS_CPU_LDPTE) 40 #endif 41 #ifndef cpu_has_rixiex 42 #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX) 43 #endif 44 #ifndef cpu_has_maar 45 #define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR) 46 #endif 47 #ifndef cpu_has_rw_llb 48 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB) 49 #endif 50 51 /* 52 * For the moment we don't consider R6000 and R8000 so we can assume that 53 * anything that doesn't support R4000-style exceptions and interrupts is 54 * R3000-like. Users should still treat these two macro definitions as 55 * opaque. 56 */ 57 #ifndef cpu_has_3kex 58 #define cpu_has_3kex (!cpu_has_4kex) 59 #endif 60 #ifndef cpu_has_4kex 61 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 62 #endif 63 #ifndef cpu_has_3k_cache 64 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 65 #endif 66 #define cpu_has_6k_cache 0 67 #define cpu_has_8k_cache 0 68 #ifndef cpu_has_4k_cache 69 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 70 #endif 71 #ifndef cpu_has_tx39_cache 72 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 73 #endif 74 #ifndef cpu_has_octeon_cache 75 #define cpu_has_octeon_cache 0 76 #endif 77 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 78 #ifndef cpu_has_fpu 79 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 80 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 81 #else 82 #define raw_cpu_has_fpu cpu_has_fpu 83 #endif 84 #ifndef cpu_has_32fpr 85 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 86 #endif 87 #ifndef cpu_has_counter 88 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 89 #endif 90 #ifndef cpu_has_watch 91 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 92 #endif 93 #ifndef cpu_has_divec 94 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 95 #endif 96 #ifndef cpu_has_vce 97 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 98 #endif 99 #ifndef cpu_has_cache_cdex_p 100 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 101 #endif 102 #ifndef cpu_has_cache_cdex_s 103 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 104 #endif 105 #ifndef cpu_has_prefetch 106 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 107 #endif 108 #ifndef cpu_has_mcheck 109 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 110 #endif 111 #ifndef cpu_has_ejtag 112 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 113 #endif 114 #ifndef cpu_has_llsc 115 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 116 #endif 117 #ifndef cpu_has_bp_ghist 118 #define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST) 119 #endif 120 #ifndef kernel_uses_llsc 121 #define kernel_uses_llsc cpu_has_llsc 122 #endif 123 #ifndef cpu_has_guestctl0ext 124 #define cpu_has_guestctl0ext (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT) 125 #endif 126 #ifndef cpu_has_guestctl1 127 #define cpu_has_guestctl1 (cpu_data[0].options & MIPS_CPU_GUESTCTL1) 128 #endif 129 #ifndef cpu_has_guestctl2 130 #define cpu_has_guestctl2 (cpu_data[0].options & MIPS_CPU_GUESTCTL2) 131 #endif 132 #ifndef cpu_has_guestid 133 #define cpu_has_guestid (cpu_data[0].options & MIPS_CPU_GUESTID) 134 #endif 135 #ifndef cpu_has_drg 136 #define cpu_has_drg (cpu_data[0].options & MIPS_CPU_DRG) 137 #endif 138 #ifndef cpu_has_mips16 139 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 140 #endif 141 #ifndef cpu_has_mips16e2 142 #define cpu_has_mips16e2 (cpu_data[0].ases & MIPS_ASE_MIPS16E2) 143 #endif 144 #ifndef cpu_has_mdmx 145 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 146 #endif 147 #ifndef cpu_has_mips3d 148 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 149 #endif 150 #ifndef cpu_has_smartmips 151 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 152 #endif 153 154 #ifndef cpu_has_rixi 155 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 156 #endif 157 158 #ifndef cpu_has_mmips 159 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 160 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 161 # else 162 # define cpu_has_mmips 0 163 # endif 164 #endif 165 166 #ifndef cpu_has_lpa 167 #define cpu_has_lpa (cpu_data[0].options & MIPS_CPU_LPA) 168 #endif 169 #ifndef cpu_has_mvh 170 #define cpu_has_mvh (cpu_data[0].options & MIPS_CPU_MVH) 171 #endif 172 #ifndef cpu_has_xpa 173 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 174 #endif 175 #ifndef cpu_has_vtag_icache 176 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 177 #endif 178 #ifndef cpu_has_dc_aliases 179 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 180 #endif 181 #ifndef cpu_has_ic_fills_f_dc 182 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 183 #endif 184 #ifndef cpu_has_pindexed_dcache 185 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 186 #endif 187 #ifndef cpu_has_local_ebase 188 #define cpu_has_local_ebase 1 189 #endif 190 191 /* 192 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 193 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 194 * don't. For maintaining I-cache coherency this means we need to flush the 195 * D-cache all the way back to whever the I-cache does refills from, so the 196 * I-cache has a chance to see the new data at all. Then we have to flush the 197 * I-cache also. 198 * Note we may have been rescheduled and may no longer be running on the CPU 199 * that did the store so we can't optimize this into only doing the flush on 200 * the local CPU. 201 */ 202 #ifndef cpu_icache_snoops_remote_store 203 #ifdef CONFIG_SMP 204 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 205 #else 206 #define cpu_icache_snoops_remote_store 1 207 #endif 208 #endif 209 210 /* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */ 211 #if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \ 212 (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \ 213 (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \ 214 (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \ 215 (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \ 216 (defined(cpu_has_mips64r6) && cpu_has_mips64r6)) 217 #define CPU_NO_EFFICIENT_FFS 1 218 #endif 219 220 #ifndef cpu_has_mips_1 221 # define cpu_has_mips_1 (!cpu_has_mips_r6) 222 #endif 223 #ifndef cpu_has_mips_2 224 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 225 #endif 226 #ifndef cpu_has_mips_3 227 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 228 #endif 229 #ifndef cpu_has_mips_4 230 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 231 #endif 232 #ifndef cpu_has_mips_5 233 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 234 #endif 235 #ifndef cpu_has_mips32r1 236 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 237 #endif 238 #ifndef cpu_has_mips32r2 239 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 240 #endif 241 #ifndef cpu_has_mips32r6 242 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) 243 #endif 244 #ifndef cpu_has_mips64r1 245 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 246 #endif 247 #ifndef cpu_has_mips64r2 248 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 249 #endif 250 #ifndef cpu_has_mips64r6 251 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) 252 #endif 253 254 /* 255 * Shortcuts ... 256 */ 257 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 258 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 259 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 260 261 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 262 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 263 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 264 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 265 266 #define cpu_has_mips_3_4_5_64_r2_r6 \ 267 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 268 #define cpu_has_mips_4_5_64_r2_r6 \ 269 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 270 cpu_has_mips_r2 | cpu_has_mips_r6) 271 272 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 273 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 274 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 275 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 276 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 277 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 278 cpu_has_mips32r6 | cpu_has_mips64r1 | \ 279 cpu_has_mips64r2 | cpu_has_mips64r6) 280 281 /* MIPSR2 and MIPSR6 have a lot of similarities */ 282 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 283 284 /* 285 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 286 * 287 * Returns non-zero value if the current processor implementation requires 288 * an IHB instruction to deal with an instruction hazard as per MIPS R2 289 * architecture specification, zero otherwise. 290 */ 291 #ifndef cpu_has_mips_r2_exec_hazard 292 #define cpu_has_mips_r2_exec_hazard \ 293 ({ \ 294 int __res; \ 295 \ 296 switch (current_cpu_type()) { \ 297 case CPU_M14KC: \ 298 case CPU_74K: \ 299 case CPU_1074K: \ 300 case CPU_PROAPTIV: \ 301 case CPU_P5600: \ 302 case CPU_M5150: \ 303 case CPU_QEMU_GENERIC: \ 304 case CPU_CAVIUM_OCTEON: \ 305 case CPU_CAVIUM_OCTEON_PLUS: \ 306 case CPU_CAVIUM_OCTEON2: \ 307 case CPU_CAVIUM_OCTEON3: \ 308 __res = 0; \ 309 break; \ 310 \ 311 default: \ 312 __res = 1; \ 313 } \ 314 \ 315 __res; \ 316 }) 317 #endif 318 319 /* 320 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 321 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 322 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 323 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 324 */ 325 #ifndef cpu_has_clo_clz 326 #define cpu_has_clo_clz cpu_has_mips_r 327 #endif 328 329 /* 330 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 331 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 332 * This indicates the availability of WSBH and in case of 64 bit CPUs also 333 * DSBH and DSHD. 334 */ 335 #ifndef cpu_has_wsbh 336 #define cpu_has_wsbh cpu_has_mips_r2 337 #endif 338 339 #ifndef cpu_has_dsp 340 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 341 #endif 342 343 #ifndef cpu_has_dsp2 344 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) 345 #endif 346 347 #ifndef cpu_has_dsp3 348 #define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3) 349 #endif 350 351 #ifndef cpu_has_mipsmt 352 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 353 #endif 354 355 #ifndef cpu_has_vp 356 #define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP) 357 #endif 358 359 #ifndef cpu_has_userlocal 360 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 361 #endif 362 363 #ifdef CONFIG_32BIT 364 # ifndef cpu_has_nofpuex 365 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 366 # endif 367 # ifndef cpu_has_64bits 368 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 369 # endif 370 # ifndef cpu_has_64bit_zero_reg 371 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 372 # endif 373 # ifndef cpu_has_64bit_gp_regs 374 # define cpu_has_64bit_gp_regs 0 375 # endif 376 # ifndef cpu_has_64bit_addresses 377 # define cpu_has_64bit_addresses 0 378 # endif 379 # ifndef cpu_vmbits 380 # define cpu_vmbits 31 381 # endif 382 #endif 383 384 #ifdef CONFIG_64BIT 385 # ifndef cpu_has_nofpuex 386 # define cpu_has_nofpuex 0 387 # endif 388 # ifndef cpu_has_64bits 389 # define cpu_has_64bits 1 390 # endif 391 # ifndef cpu_has_64bit_zero_reg 392 # define cpu_has_64bit_zero_reg 1 393 # endif 394 # ifndef cpu_has_64bit_gp_regs 395 # define cpu_has_64bit_gp_regs 1 396 # endif 397 # ifndef cpu_has_64bit_addresses 398 # define cpu_has_64bit_addresses 1 399 # endif 400 # ifndef cpu_vmbits 401 # define cpu_vmbits cpu_data[0].vmbits 402 # define __NEED_VMBITS_PROBE 403 # endif 404 #endif 405 406 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 407 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 408 #elif !defined(cpu_has_vint) 409 # define cpu_has_vint 0 410 #endif 411 412 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 413 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 414 #elif !defined(cpu_has_veic) 415 # define cpu_has_veic 0 416 #endif 417 418 #ifndef cpu_has_inclusive_pcaches 419 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 420 #endif 421 422 #ifndef cpu_dcache_line_size 423 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 424 #endif 425 #ifndef cpu_icache_line_size 426 #define cpu_icache_line_size() cpu_data[0].icache.linesz 427 #endif 428 #ifndef cpu_scache_line_size 429 #define cpu_scache_line_size() cpu_data[0].scache.linesz 430 #endif 431 #ifndef cpu_tcache_line_size 432 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 433 #endif 434 435 #ifndef cpu_hwrena_impl_bits 436 #define cpu_hwrena_impl_bits 0 437 #endif 438 439 #ifndef cpu_has_perf_cntr_intr_bit 440 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 441 #endif 442 443 #ifndef cpu_has_vz 444 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) 445 #endif 446 447 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 448 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA) 449 #elif !defined(cpu_has_msa) 450 # define cpu_has_msa 0 451 #endif 452 453 #ifndef cpu_has_ufr 454 # define cpu_has_ufr (cpu_data[0].options & MIPS_CPU_UFR) 455 #endif 456 457 #ifndef cpu_has_fre 458 # define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE) 459 #endif 460 461 #ifndef cpu_has_cdmm 462 # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM) 463 #endif 464 465 #ifndef cpu_has_small_pages 466 # define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP) 467 #endif 468 469 #ifndef cpu_has_nan_legacy 470 #define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY) 471 #endif 472 #ifndef cpu_has_nan_2008 473 #define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008) 474 #endif 475 476 #ifndef cpu_has_ebase_wg 477 # define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG) 478 #endif 479 480 #ifndef cpu_has_badinstr 481 # define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR) 482 #endif 483 484 #ifndef cpu_has_badinstrp 485 # define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP) 486 #endif 487 488 #ifndef cpu_has_contextconfig 489 # define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC) 490 #endif 491 492 #ifndef cpu_has_perf 493 # define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF) 494 #endif 495 496 #if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6) 497 /* 498 * Some systems share FTLB RAMs between threads within a core (siblings in 499 * kernel parlance). This means that FTLB entries may become invalid at almost 500 * any point when an entry is evicted due to a sibling thread writing an entry 501 * to the shared FTLB RAM. 502 * 503 * This is only relevant to SMP systems, and the only systems that exhibit this 504 * property implement MIPSr6 or higher so we constrain support for this to 505 * kernels that will run on such systems. 506 */ 507 # ifndef cpu_has_shared_ftlb_ram 508 # define cpu_has_shared_ftlb_ram \ 509 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_RAM) 510 # endif 511 512 /* 513 * Some systems take this a step further & share FTLB entries between siblings. 514 * This is implemented as TLB writes happening as usual, but if an entry 515 * written by a sibling exists in the shared FTLB for a translation which would 516 * otherwise cause a TLB refill exception then the CPU will use the entry 517 * written by its sibling rather than triggering a refill & writing a matching 518 * TLB entry for itself. 519 * 520 * This is naturally only valid if a TLB entry is known to be suitable for use 521 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 522 * rather than ASIDs or when a TLB entry is marked global. 523 */ 524 # ifndef cpu_has_shared_ftlb_entries 525 # define cpu_has_shared_ftlb_entries \ 526 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES) 527 # endif 528 #endif /* SMP && __mips_isa_rev >= 6 */ 529 530 #ifndef cpu_has_shared_ftlb_ram 531 # define cpu_has_shared_ftlb_ram 0 532 #endif 533 #ifndef cpu_has_shared_ftlb_entries 534 # define cpu_has_shared_ftlb_entries 0 535 #endif 536 537 /* 538 * Guest capabilities 539 */ 540 #ifndef cpu_guest_has_conf1 541 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 542 #endif 543 #ifndef cpu_guest_has_conf2 544 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 545 #endif 546 #ifndef cpu_guest_has_conf3 547 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 548 #endif 549 #ifndef cpu_guest_has_conf4 550 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 551 #endif 552 #ifndef cpu_guest_has_conf5 553 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 554 #endif 555 #ifndef cpu_guest_has_conf6 556 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 557 #endif 558 #ifndef cpu_guest_has_conf7 559 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 560 #endif 561 #ifndef cpu_guest_has_fpu 562 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 563 #endif 564 #ifndef cpu_guest_has_watch 565 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 566 #endif 567 #ifndef cpu_guest_has_contextconfig 568 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 569 #endif 570 #ifndef cpu_guest_has_segments 571 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 572 #endif 573 #ifndef cpu_guest_has_badinstr 574 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 575 #endif 576 #ifndef cpu_guest_has_badinstrp 577 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 578 #endif 579 #ifndef cpu_guest_has_htw 580 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 581 #endif 582 #ifndef cpu_guest_has_mvh 583 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 584 #endif 585 #ifndef cpu_guest_has_msa 586 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 587 #endif 588 #ifndef cpu_guest_has_kscr 589 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 590 #endif 591 #ifndef cpu_guest_has_rw_llb 592 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 593 #endif 594 #ifndef cpu_guest_has_perf 595 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 596 #endif 597 #ifndef cpu_guest_has_maar 598 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 599 #endif 600 #ifndef cpu_guest_has_userlocal 601 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 602 #endif 603 604 /* 605 * Guest dynamic capabilities 606 */ 607 #ifndef cpu_guest_has_dyn_fpu 608 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 609 #endif 610 #ifndef cpu_guest_has_dyn_watch 611 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 612 #endif 613 #ifndef cpu_guest_has_dyn_contextconfig 614 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 615 #endif 616 #ifndef cpu_guest_has_dyn_perf 617 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 618 #endif 619 #ifndef cpu_guest_has_dyn_msa 620 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 621 #endif 622 #ifndef cpu_guest_has_dyn_maar 623 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 624 #endif 625 626 #endif /* __ASM_CPU_FEATURES_H */ 627