1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/isa-rev.h> 15 #include <cpu-feature-overrides.h> 16 17 #define __ase(ase) (cpu_data[0].ases & (ase)) 18 #define __isa(isa) (cpu_data[0].isa_level & (isa)) 19 #define __opt(opt) (cpu_data[0].options & (opt)) 20 21 /* 22 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 23 * boot (typically by cpu_probe()). 24 * 25 * Note that these should only be used in cases where a kernel built for an 26 * older ISA *cannot* run on a CPU which supports the feature in question. For 27 * example this may be used for features introduced with MIPSr6, since a kernel 28 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 29 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 30 * MIPSr2 CPU. 31 */ 32 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 33 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 34 35 /* 36 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 37 * boot (typically by cpu_probe()). 38 * 39 * These are for use with features that are optional up until a particular ISA 40 * revision & then become required. 41 */ 42 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 43 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 44 45 /* 46 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 47 * boot (typically by cpu_probe()). 48 * 49 * These are for use with features that are optional up until a particular ISA 50 * revision & are then removed - ie. no longer present in any CPU implementing 51 * the given ISA revision. 52 */ 53 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 54 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 55 56 /* 57 * Similarly allow for ISA level checks that take into account knowledge of the 58 * ISA targeted by the kernel build, provided by MIPS_ISA_REV. 59 */ 60 #define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) 61 #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) 62 #define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) 63 #define __isa_range(ge, lt) \ 64 ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) 65 #define __isa_range_or_flag(ge, lt, flag) \ 66 (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) 67 #define __isa_range_and_ase(ge, lt, ase) \ 68 (__isa_range(ge, lt) && __ase(ase)) 69 70 /* 71 * SMP assumption: Options of CPU 0 are a superset of all processors. 72 * This is true for all known MIPS systems. 73 */ 74 #ifndef cpu_has_tlb 75 #define cpu_has_tlb __opt(MIPS_CPU_TLB) 76 #endif 77 #ifndef cpu_has_ftlb 78 #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 79 #endif 80 #ifndef cpu_has_tlbinv 81 #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 82 #endif 83 #ifndef cpu_has_segments 84 #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 85 #endif 86 #ifndef cpu_has_eva 87 #define cpu_has_eva __opt(MIPS_CPU_EVA) 88 #endif 89 #ifndef cpu_has_htw 90 #define cpu_has_htw __opt(MIPS_CPU_HTW) 91 #endif 92 #ifndef cpu_has_ldpte 93 #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 94 #endif 95 #ifndef cpu_has_rixiex 96 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 97 #endif 98 #ifndef cpu_has_maar 99 #define cpu_has_maar __opt(MIPS_CPU_MAAR) 100 #endif 101 #ifndef cpu_has_rw_llb 102 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 103 #endif 104 105 /* 106 * For the moment we don't consider R6000 and R8000 so we can assume that 107 * anything that doesn't support R4000-style exceptions and interrupts is 108 * R3000-like. Users should still treat these two macro definitions as 109 * opaque. 110 */ 111 #ifndef cpu_has_3kex 112 #define cpu_has_3kex (!cpu_has_4kex) 113 #endif 114 #ifndef cpu_has_4kex 115 #define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 116 #endif 117 #ifndef cpu_has_3k_cache 118 #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 119 #endif 120 #ifndef cpu_has_4k_cache 121 #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 122 #endif 123 #ifndef cpu_has_octeon_cache 124 #define cpu_has_octeon_cache 0 125 #endif 126 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 127 #ifndef cpu_has_fpu 128 # ifdef CONFIG_MIPS_FP_SUPPORT 129 # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 130 # define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 131 # else 132 # define cpu_has_fpu 0 133 # define raw_cpu_has_fpu 0 134 # endif 135 #else 136 # define raw_cpu_has_fpu cpu_has_fpu 137 #endif 138 #ifndef cpu_has_32fpr 139 #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 140 #endif 141 #ifndef cpu_has_counter 142 #define cpu_has_counter __opt(MIPS_CPU_COUNTER) 143 #endif 144 #ifndef cpu_has_watch 145 #define cpu_has_watch __opt(MIPS_CPU_WATCH) 146 #endif 147 #ifndef cpu_has_divec 148 #define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 149 #endif 150 #ifndef cpu_has_vce 151 #define cpu_has_vce __opt(MIPS_CPU_VCE) 152 #endif 153 #ifndef cpu_has_cache_cdex_p 154 #define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 155 #endif 156 #ifndef cpu_has_cache_cdex_s 157 #define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 158 #endif 159 #ifndef cpu_has_prefetch 160 #define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 161 #endif 162 #ifndef cpu_has_mcheck 163 #define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 164 #endif 165 #ifndef cpu_has_ejtag 166 #define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 167 #endif 168 #ifndef cpu_has_llsc 169 #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 170 #endif 171 #ifndef kernel_uses_llsc 172 #define kernel_uses_llsc cpu_has_llsc 173 #endif 174 #ifndef cpu_has_guestctl0ext 175 #define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 176 #endif 177 #ifndef cpu_has_guestctl1 178 #define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 179 #endif 180 #ifndef cpu_has_guestctl2 181 #define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 182 #endif 183 #ifndef cpu_has_guestid 184 #define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 185 #endif 186 #ifndef cpu_has_drg 187 #define cpu_has_drg __opt(MIPS_CPU_DRG) 188 #endif 189 #ifndef cpu_has_mips16 190 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 191 #endif 192 #ifndef cpu_has_mips16e2 193 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 194 #endif 195 #ifndef cpu_has_mdmx 196 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 197 #endif 198 #ifndef cpu_has_mips3d 199 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 200 #endif 201 #ifndef cpu_has_smartmips 202 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 203 #endif 204 205 #ifndef cpu_has_rixi 206 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 207 #endif 208 209 #ifndef cpu_has_mmips 210 # if defined(__mips_micromips) 211 # define cpu_has_mmips 1 212 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 213 # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 214 # else 215 # define cpu_has_mmips 0 216 # endif 217 #endif 218 219 #ifndef cpu_has_lpa 220 #define cpu_has_lpa __opt(MIPS_CPU_LPA) 221 #endif 222 #ifndef cpu_has_mvh 223 #define cpu_has_mvh __opt(MIPS_CPU_MVH) 224 #endif 225 #ifndef cpu_has_xpa 226 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 227 #endif 228 #ifndef cpu_has_vtag_icache 229 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 230 #endif 231 #ifndef cpu_has_dc_aliases 232 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 233 #endif 234 #ifndef cpu_has_ic_fills_f_dc 235 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 236 #endif 237 #ifndef cpu_has_pindexed_dcache 238 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 239 #endif 240 241 /* 242 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 243 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 244 * don't. For maintaining I-cache coherency this means we need to flush the 245 * D-cache all the way back to whever the I-cache does refills from, so the 246 * I-cache has a chance to see the new data at all. Then we have to flush the 247 * I-cache also. 248 * Note we may have been rescheduled and may no longer be running on the CPU 249 * that did the store so we can't optimize this into only doing the flush on 250 * the local CPU. 251 */ 252 #ifndef cpu_icache_snoops_remote_store 253 #ifdef CONFIG_SMP 254 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 255 #else 256 #define cpu_icache_snoops_remote_store 1 257 #endif 258 #endif 259 260 #ifndef cpu_has_mips_1 261 # define cpu_has_mips_1 (MIPS_ISA_REV < 6) 262 #endif 263 #ifndef cpu_has_mips_2 264 # define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II) 265 #endif 266 #ifndef cpu_has_mips_3 267 # define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III) 268 #endif 269 #ifndef cpu_has_mips_4 270 # define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV) 271 #endif 272 #ifndef cpu_has_mips_5 273 # define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V) 274 #endif 275 #ifndef cpu_has_mips32r1 276 # define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1) 277 #endif 278 #ifndef cpu_has_mips32r2 279 # define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) 280 #endif 281 #ifndef cpu_has_mips32r5 282 # define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5) 283 #endif 284 #ifndef cpu_has_mips32r6 285 # define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) 286 #endif 287 #ifndef cpu_has_mips64r1 288 # define cpu_has_mips64r1 (cpu_has_64bits && \ 289 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)) 290 #endif 291 #ifndef cpu_has_mips64r2 292 # define cpu_has_mips64r2 (cpu_has_64bits && \ 293 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)) 294 #endif 295 #ifndef cpu_has_mips64r5 296 # define cpu_has_mips64r5 (cpu_has_64bits && \ 297 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5)) 298 #endif 299 #ifndef cpu_has_mips64r6 300 # define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) 301 #endif 302 303 /* 304 * Shortcuts ... 305 */ 306 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 307 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 308 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 309 310 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 311 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 312 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 313 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 314 315 #define cpu_has_mips_3_4_5_64_r2_r6 \ 316 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 317 #define cpu_has_mips_4_5_64_r2_r6 \ 318 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 319 cpu_has_mips_r2 | cpu_has_mips_r5 | \ 320 cpu_has_mips_r6) 321 322 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 323 cpu_has_mips32r5 | cpu_has_mips32r6) 324 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \ 325 cpu_has_mips64r5 | cpu_has_mips64r6) 326 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 327 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 328 #define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5) 329 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 330 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 331 cpu_has_mips32r5 | cpu_has_mips32r6 | \ 332 cpu_has_mips64r1 | cpu_has_mips64r2 | \ 333 cpu_has_mips64r5 | cpu_has_mips64r6) 334 335 /* MIPSR2 - MIPSR6 have a lot of similarities */ 336 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \ 337 cpu_has_mips_r6) 338 339 /* 340 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 341 * 342 * Returns non-zero value if the current processor implementation requires 343 * an IHB instruction to deal with an instruction hazard as per MIPS R2 344 * architecture specification, zero otherwise. 345 */ 346 #ifndef cpu_has_mips_r2_exec_hazard 347 #define cpu_has_mips_r2_exec_hazard \ 348 ({ \ 349 int __res; \ 350 \ 351 switch (current_cpu_type()) { \ 352 case CPU_M14KC: \ 353 case CPU_74K: \ 354 case CPU_1074K: \ 355 case CPU_PROAPTIV: \ 356 case CPU_P5600: \ 357 case CPU_M5150: \ 358 case CPU_QEMU_GENERIC: \ 359 case CPU_CAVIUM_OCTEON: \ 360 case CPU_CAVIUM_OCTEON_PLUS: \ 361 case CPU_CAVIUM_OCTEON2: \ 362 case CPU_CAVIUM_OCTEON3: \ 363 __res = 0; \ 364 break; \ 365 \ 366 default: \ 367 __res = 1; \ 368 } \ 369 \ 370 __res; \ 371 }) 372 #endif 373 374 /* 375 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 376 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 377 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 378 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 379 */ 380 #ifndef cpu_has_clo_clz 381 #define cpu_has_clo_clz cpu_has_mips_r 382 #endif 383 384 /* 385 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 386 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 387 * This indicates the availability of WSBH and in case of 64 bit CPUs also 388 * DSBH and DSHD. 389 */ 390 #ifndef cpu_has_wsbh 391 #define cpu_has_wsbh cpu_has_mips_r2 392 #endif 393 394 #ifndef cpu_has_dsp 395 #define cpu_has_dsp __ase(MIPS_ASE_DSP) 396 #endif 397 398 #ifndef cpu_has_dsp2 399 #define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 400 #endif 401 402 #ifndef cpu_has_dsp3 403 #define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 404 #endif 405 406 #ifndef cpu_has_loongson_mmi 407 #define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI) 408 #endif 409 410 #ifndef cpu_has_loongson_cam 411 #define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM) 412 #endif 413 414 #ifndef cpu_has_loongson_ext 415 #define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT) 416 #endif 417 418 #ifndef cpu_has_loongson_ext2 419 #define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2) 420 #endif 421 422 #ifndef cpu_has_mipsmt 423 #define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT) 424 #endif 425 426 #ifndef cpu_has_vp 427 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 428 #endif 429 430 #ifndef cpu_has_userlocal 431 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 432 #endif 433 434 #ifdef CONFIG_32BIT 435 # ifndef cpu_has_nofpuex 436 # define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 437 # endif 438 # ifndef cpu_has_64bits 439 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 440 # endif 441 # ifndef cpu_has_64bit_zero_reg 442 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 443 # endif 444 # ifndef cpu_has_64bit_gp_regs 445 # define cpu_has_64bit_gp_regs 0 446 # endif 447 # ifndef cpu_vmbits 448 # define cpu_vmbits 31 449 # endif 450 #endif 451 452 #ifdef CONFIG_64BIT 453 # ifndef cpu_has_nofpuex 454 # define cpu_has_nofpuex 0 455 # endif 456 # ifndef cpu_has_64bits 457 # define cpu_has_64bits 1 458 # endif 459 # ifndef cpu_has_64bit_zero_reg 460 # define cpu_has_64bit_zero_reg 1 461 # endif 462 # ifndef cpu_has_64bit_gp_regs 463 # define cpu_has_64bit_gp_regs 1 464 # endif 465 # ifndef cpu_vmbits 466 # define cpu_vmbits cpu_data[0].vmbits 467 # define __NEED_VMBITS_PROBE 468 # endif 469 #endif 470 471 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 472 # define cpu_has_vint __opt(MIPS_CPU_VINT) 473 #elif !defined(cpu_has_vint) 474 # define cpu_has_vint 0 475 #endif 476 477 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 478 # define cpu_has_veic __opt(MIPS_CPU_VEIC) 479 #elif !defined(cpu_has_veic) 480 # define cpu_has_veic 0 481 #endif 482 483 #ifndef cpu_has_inclusive_pcaches 484 #define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 485 #endif 486 487 #ifndef cpu_dcache_line_size 488 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 489 #endif 490 #ifndef cpu_icache_line_size 491 #define cpu_icache_line_size() cpu_data[0].icache.linesz 492 #endif 493 #ifndef cpu_scache_line_size 494 #define cpu_scache_line_size() cpu_data[0].scache.linesz 495 #endif 496 #ifndef cpu_tcache_line_size 497 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 498 #endif 499 500 #ifndef cpu_hwrena_impl_bits 501 #define cpu_hwrena_impl_bits 0 502 #endif 503 504 #ifndef cpu_has_perf_cntr_intr_bit 505 #define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 506 #endif 507 508 #ifndef cpu_has_vz 509 #define cpu_has_vz __ase(MIPS_ASE_VZ) 510 #endif 511 512 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 513 # define cpu_has_msa __ase(MIPS_ASE_MSA) 514 #elif !defined(cpu_has_msa) 515 # define cpu_has_msa 0 516 #endif 517 518 #ifndef cpu_has_ufr 519 # define cpu_has_ufr __opt(MIPS_CPU_UFR) 520 #endif 521 522 #ifndef cpu_has_fre 523 # define cpu_has_fre __opt(MIPS_CPU_FRE) 524 #endif 525 526 #ifndef cpu_has_cdmm 527 # define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 528 #endif 529 530 #ifndef cpu_has_small_pages 531 # define cpu_has_small_pages __opt(MIPS_CPU_SP) 532 #endif 533 534 #ifndef cpu_has_nan_legacy 535 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 536 #endif 537 #ifndef cpu_has_nan_2008 538 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 539 #endif 540 541 #ifndef cpu_has_ebase_wg 542 # define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 543 #endif 544 545 #ifndef cpu_has_badinstr 546 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 547 #endif 548 549 #ifndef cpu_has_badinstrp 550 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 551 #endif 552 553 #ifndef cpu_has_contextconfig 554 # define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 555 #endif 556 557 #ifndef cpu_has_perf 558 # define cpu_has_perf __opt(MIPS_CPU_PERF) 559 #endif 560 561 #ifndef cpu_has_mac2008_only 562 # define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) 563 #endif 564 565 #ifndef cpu_has_ftlbparex 566 # define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) 567 #endif 568 569 #ifndef cpu_has_gsexcex 570 # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) 571 #endif 572 573 #ifdef CONFIG_SMP 574 /* 575 * Some systems share FTLB RAMs between threads within a core (siblings in 576 * kernel parlance). This means that FTLB entries may become invalid at almost 577 * any point when an entry is evicted due to a sibling thread writing an entry 578 * to the shared FTLB RAM. 579 * 580 * This is only relevant to SMP systems, and the only systems that exhibit this 581 * property implement MIPSr6 or higher so we constrain support for this to 582 * kernels that will run on such systems. 583 */ 584 # ifndef cpu_has_shared_ftlb_ram 585 # define cpu_has_shared_ftlb_ram \ 586 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 587 # endif 588 589 /* 590 * Some systems take this a step further & share FTLB entries between siblings. 591 * This is implemented as TLB writes happening as usual, but if an entry 592 * written by a sibling exists in the shared FTLB for a translation which would 593 * otherwise cause a TLB refill exception then the CPU will use the entry 594 * written by its sibling rather than triggering a refill & writing a matching 595 * TLB entry for itself. 596 * 597 * This is naturally only valid if a TLB entry is known to be suitable for use 598 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 599 * rather than ASIDs or when a TLB entry is marked global. 600 */ 601 # ifndef cpu_has_shared_ftlb_entries 602 # define cpu_has_shared_ftlb_entries \ 603 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 604 # endif 605 #endif /* SMP */ 606 607 #ifndef cpu_has_shared_ftlb_ram 608 # define cpu_has_shared_ftlb_ram 0 609 #endif 610 #ifndef cpu_has_shared_ftlb_entries 611 # define cpu_has_shared_ftlb_entries 0 612 #endif 613 614 #ifdef CONFIG_MIPS_MT_SMP 615 # define cpu_has_mipsmt_pertccounters \ 616 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 617 #else 618 # define cpu_has_mipsmt_pertccounters 0 619 #endif /* CONFIG_MIPS_MT_SMP */ 620 621 /* 622 * We only enable MMID support for configurations which natively support 64 bit 623 * atomics because getting good performance from the allocator relies upon 624 * efficient atomic64_*() functions. 625 */ 626 #ifndef cpu_has_mmid 627 # ifdef CONFIG_GENERIC_ATOMIC64 628 # define cpu_has_mmid 0 629 # else 630 # define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID) 631 # endif 632 #endif 633 634 #ifndef cpu_has_mm_sysad 635 # define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD) 636 #endif 637 638 #ifndef cpu_has_mm_full 639 # define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL) 640 #endif 641 642 /* 643 * Guest capabilities 644 */ 645 #ifndef cpu_guest_has_conf1 646 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 647 #endif 648 #ifndef cpu_guest_has_conf2 649 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 650 #endif 651 #ifndef cpu_guest_has_conf3 652 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 653 #endif 654 #ifndef cpu_guest_has_conf4 655 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 656 #endif 657 #ifndef cpu_guest_has_conf5 658 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 659 #endif 660 #ifndef cpu_guest_has_conf6 661 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 662 #endif 663 #ifndef cpu_guest_has_conf7 664 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 665 #endif 666 #ifndef cpu_guest_has_fpu 667 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 668 #endif 669 #ifndef cpu_guest_has_watch 670 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 671 #endif 672 #ifndef cpu_guest_has_contextconfig 673 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 674 #endif 675 #ifndef cpu_guest_has_segments 676 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 677 #endif 678 #ifndef cpu_guest_has_badinstr 679 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 680 #endif 681 #ifndef cpu_guest_has_badinstrp 682 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 683 #endif 684 #ifndef cpu_guest_has_htw 685 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 686 #endif 687 #ifndef cpu_guest_has_ldpte 688 #define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE) 689 #endif 690 #ifndef cpu_guest_has_mvh 691 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 692 #endif 693 #ifndef cpu_guest_has_msa 694 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 695 #endif 696 #ifndef cpu_guest_has_kscr 697 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 698 #endif 699 #ifndef cpu_guest_has_rw_llb 700 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 701 #endif 702 #ifndef cpu_guest_has_perf 703 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 704 #endif 705 #ifndef cpu_guest_has_maar 706 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 707 #endif 708 #ifndef cpu_guest_has_userlocal 709 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 710 #endif 711 712 /* 713 * Guest dynamic capabilities 714 */ 715 #ifndef cpu_guest_has_dyn_fpu 716 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 717 #endif 718 #ifndef cpu_guest_has_dyn_watch 719 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 720 #endif 721 #ifndef cpu_guest_has_dyn_contextconfig 722 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 723 #endif 724 #ifndef cpu_guest_has_dyn_perf 725 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 726 #endif 727 #ifndef cpu_guest_has_dyn_msa 728 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 729 #endif 730 #ifndef cpu_guest_has_dyn_maar 731 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 732 #endif 733 734 #endif /* __ASM_CPU_FEATURES_H */ 735