1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2003, 2004 Ralf Baechle
7  * Copyright (C) 2004  Maciej W. Rozycki
8  */
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
11 
12 #include <asm/cpu.h>
13 #include <asm/cpu-info.h>
14 #include <cpu-feature-overrides.h>
15 
16 #ifndef current_cpu_type
17 #define current_cpu_type()      current_cpu_data.cputype
18 #endif
19 
20 /*
21  * SMP assumption: Options of CPU 0 are a superset of all processors.
22  * This is true for all known MIPS systems.
23  */
24 #ifndef cpu_has_tlb
25 #define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)
26 #endif
27 #ifndef cpu_has_4kex
28 #define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
29 #endif
30 #ifndef cpu_has_3k_cache
31 #define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
32 #endif
33 #define cpu_has_6k_cache	0
34 #define cpu_has_8k_cache	0
35 #ifndef cpu_has_4k_cache
36 #define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
37 #endif
38 #ifndef cpu_has_tx39_cache
39 #define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40 #endif
41 #ifndef cpu_has_octeon_cache
42 #define cpu_has_octeon_cache	0
43 #endif
44 #ifndef cpu_has_fpu
45 #define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
46 #define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
47 #else
48 #define raw_cpu_has_fpu		cpu_has_fpu
49 #endif
50 #ifndef cpu_has_32fpr
51 #define cpu_has_32fpr		(cpu_data[0].options & MIPS_CPU_32FPR)
52 #endif
53 #ifndef cpu_has_counter
54 #define cpu_has_counter		(cpu_data[0].options & MIPS_CPU_COUNTER)
55 #endif
56 #ifndef cpu_has_watch
57 #define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
58 #endif
59 #ifndef cpu_has_divec
60 #define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
61 #endif
62 #ifndef cpu_has_vce
63 #define cpu_has_vce		(cpu_data[0].options & MIPS_CPU_VCE)
64 #endif
65 #ifndef cpu_has_cache_cdex_p
66 #define cpu_has_cache_cdex_p	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
67 #endif
68 #ifndef cpu_has_cache_cdex_s
69 #define cpu_has_cache_cdex_s	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
70 #endif
71 #ifndef cpu_has_prefetch
72 #define cpu_has_prefetch	(cpu_data[0].options & MIPS_CPU_PREFETCH)
73 #endif
74 #ifndef cpu_has_mcheck
75 #define cpu_has_mcheck		(cpu_data[0].options & MIPS_CPU_MCHECK)
76 #endif
77 #ifndef cpu_has_ejtag
78 #define cpu_has_ejtag		(cpu_data[0].options & MIPS_CPU_EJTAG)
79 #endif
80 #ifndef cpu_has_llsc
81 #define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
82 #endif
83 #ifndef kernel_uses_llsc
84 #define kernel_uses_llsc	cpu_has_llsc
85 #endif
86 #ifndef cpu_has_mips16
87 #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
88 #endif
89 #ifndef cpu_has_mdmx
90 #define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
91 #endif
92 #ifndef cpu_has_mips3d
93 #define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
94 #endif
95 #ifndef cpu_has_smartmips
96 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97 #endif
98 #ifndef kernel_uses_smartmips_rixi
99 #define kernel_uses_smartmips_rixi 0
100 #endif
101 #ifndef cpu_has_vtag_icache
102 #define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
103 #endif
104 #ifndef cpu_has_dc_aliases
105 #define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
106 #endif
107 #ifndef cpu_has_ic_fills_f_dc
108 #define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
109 #endif
110 #ifndef cpu_has_pindexed_dcache
111 #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
112 #endif
113 
114 /*
115  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
116  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
117  * don't.  For maintaining I-cache coherency this means we need to flush the
118  * D-cache all the way back to whever the I-cache does refills from, so the
119  * I-cache has a chance to see the new data at all.  Then we have to flush the
120  * I-cache also.
121  * Note we may have been rescheduled and may no longer be running on the CPU
122  * that did the store so we can't optimize this into only doing the flush on
123  * the local CPU.
124  */
125 #ifndef cpu_icache_snoops_remote_store
126 #ifdef CONFIG_SMP
127 #define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
128 #else
129 #define cpu_icache_snoops_remote_store	1
130 #endif
131 #endif
132 
133 # ifndef cpu_has_mips32r1
134 # define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
135 # endif
136 # ifndef cpu_has_mips32r2
137 # define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
138 # endif
139 # ifndef cpu_has_mips64r1
140 # define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
141 # endif
142 # ifndef cpu_has_mips64r2
143 # define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
144 # endif
145 
146 /*
147  * Shortcuts ...
148  */
149 #define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2)
150 #define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2)
151 #define cpu_has_mips_r1	(cpu_has_mips32r1 | cpu_has_mips64r1)
152 #define cpu_has_mips_r2	(cpu_has_mips32r2 | cpu_has_mips64r2)
153 #define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
154 			 cpu_has_mips64r1 | cpu_has_mips64r2)
155 
156 #ifndef cpu_has_mips_r2_exec_hazard
157 #define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
158 #endif
159 
160 /*
161  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
162  * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
163  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
164  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
165  */
166 # ifndef cpu_has_clo_clz
167 # define cpu_has_clo_clz	cpu_has_mips_r
168 # endif
169 
170 #ifndef cpu_has_dsp
171 #define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
172 #endif
173 
174 #ifndef cpu_has_mipsmt
175 #define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
176 #endif
177 
178 #ifndef cpu_has_userlocal
179 #define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
180 #endif
181 
182 #ifdef CONFIG_32BIT
183 # ifndef cpu_has_nofpuex
184 # define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)
185 # endif
186 # ifndef cpu_has_64bits
187 # define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
188 # endif
189 # ifndef cpu_has_64bit_zero_reg
190 # define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
191 # endif
192 # ifndef cpu_has_64bit_gp_regs
193 # define cpu_has_64bit_gp_regs		0
194 # endif
195 # ifndef cpu_has_64bit_addresses
196 # define cpu_has_64bit_addresses	0
197 # endif
198 # ifndef cpu_vmbits
199 # define cpu_vmbits 31
200 # endif
201 #endif
202 
203 #ifdef CONFIG_64BIT
204 # ifndef cpu_has_nofpuex
205 # define cpu_has_nofpuex		0
206 # endif
207 # ifndef cpu_has_64bits
208 # define cpu_has_64bits			1
209 # endif
210 # ifndef cpu_has_64bit_zero_reg
211 # define cpu_has_64bit_zero_reg		1
212 # endif
213 # ifndef cpu_has_64bit_gp_regs
214 # define cpu_has_64bit_gp_regs		1
215 # endif
216 # ifndef cpu_has_64bit_addresses
217 # define cpu_has_64bit_addresses	1
218 # endif
219 # ifndef cpu_vmbits
220 # define cpu_vmbits cpu_data[0].vmbits
221 # define __NEED_VMBITS_PROBE
222 # endif
223 #endif
224 
225 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
226 # define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
227 #elif !defined(cpu_has_vint)
228 # define cpu_has_vint			0
229 #endif
230 
231 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
232 # define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
233 #elif !defined(cpu_has_veic)
234 # define cpu_has_veic			0
235 #endif
236 
237 #ifndef cpu_has_inclusive_pcaches
238 #define cpu_has_inclusive_pcaches	(cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
239 #endif
240 
241 #ifndef cpu_dcache_line_size
242 #define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
243 #endif
244 #ifndef cpu_icache_line_size
245 #define cpu_icache_line_size()	cpu_data[0].icache.linesz
246 #endif
247 #ifndef cpu_scache_line_size
248 #define cpu_scache_line_size()	cpu_data[0].scache.linesz
249 #endif
250 
251 #ifndef cpu_hwrena_impl_bits
252 #define cpu_hwrena_impl_bits		0
253 #endif
254 
255 #endif /* __ASM_CPU_FEATURES_H */
256