1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/isa-rev.h> 15 #include <cpu-feature-overrides.h> 16 17 #define __ase(ase) (cpu_data[0].ases & (ase)) 18 #define __isa(isa) (cpu_data[0].isa_level & (isa)) 19 #define __opt(opt) (cpu_data[0].options & (opt)) 20 21 /* 22 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 23 * boot (typically by cpu_probe()). 24 * 25 * Note that these should only be used in cases where a kernel built for an 26 * older ISA *cannot* run on a CPU which supports the feature in question. For 27 * example this may be used for features introduced with MIPSr6, since a kernel 28 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 29 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 30 * MIPSr2 CPU. 31 */ 32 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 33 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 34 35 /* 36 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 37 * boot (typically by cpu_probe()). 38 * 39 * These are for use with features that are optional up until a particular ISA 40 * revision & then become required. 41 */ 42 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 43 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 44 45 /* 46 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 47 * boot (typically by cpu_probe()). 48 * 49 * These are for use with features that are optional up until a particular ISA 50 * revision & are then removed - ie. no longer present in any CPU implementing 51 * the given ISA revision. 52 */ 53 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 54 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 55 56 /* 57 * Similarly allow for ISA level checks that take into account knowledge of the 58 * ISA targeted by the kernel build, provided by MIPS_ISA_REV. 59 */ 60 #define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) 61 #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) 62 #define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) 63 #define __isa_range(ge, lt) \ 64 ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) 65 #define __isa_range_or_flag(ge, lt, flag) \ 66 (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) 67 68 /* 69 * SMP assumption: Options of CPU 0 are a superset of all processors. 70 * This is true for all known MIPS systems. 71 */ 72 #ifndef cpu_has_tlb 73 #define cpu_has_tlb __opt(MIPS_CPU_TLB) 74 #endif 75 #ifndef cpu_has_ftlb 76 #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 77 #endif 78 #ifndef cpu_has_tlbinv 79 #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 80 #endif 81 #ifndef cpu_has_segments 82 #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 83 #endif 84 #ifndef cpu_has_eva 85 #define cpu_has_eva __opt(MIPS_CPU_EVA) 86 #endif 87 #ifndef cpu_has_htw 88 #define cpu_has_htw __opt(MIPS_CPU_HTW) 89 #endif 90 #ifndef cpu_has_ldpte 91 #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 92 #endif 93 #ifndef cpu_has_rixiex 94 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 95 #endif 96 #ifndef cpu_has_maar 97 #define cpu_has_maar __opt(MIPS_CPU_MAAR) 98 #endif 99 #ifndef cpu_has_rw_llb 100 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 101 #endif 102 103 /* 104 * For the moment we don't consider R6000 and R8000 so we can assume that 105 * anything that doesn't support R4000-style exceptions and interrupts is 106 * R3000-like. Users should still treat these two macro definitions as 107 * opaque. 108 */ 109 #ifndef cpu_has_3kex 110 #define cpu_has_3kex (!cpu_has_4kex) 111 #endif 112 #ifndef cpu_has_4kex 113 #define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 114 #endif 115 #ifndef cpu_has_3k_cache 116 #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 117 #endif 118 #ifndef cpu_has_4k_cache 119 #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 120 #endif 121 #ifndef cpu_has_tx39_cache 122 #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) 123 #endif 124 #ifndef cpu_has_octeon_cache 125 #define cpu_has_octeon_cache 0 126 #endif 127 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 128 #ifndef cpu_has_fpu 129 # ifdef CONFIG_MIPS_FP_SUPPORT 130 # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 131 # define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 132 # else 133 # define cpu_has_fpu 0 134 # define raw_cpu_has_fpu 0 135 # endif 136 #else 137 # define raw_cpu_has_fpu cpu_has_fpu 138 #endif 139 #ifndef cpu_has_32fpr 140 #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 141 #endif 142 #ifndef cpu_has_counter 143 #define cpu_has_counter __opt(MIPS_CPU_COUNTER) 144 #endif 145 #ifndef cpu_has_watch 146 #define cpu_has_watch __opt(MIPS_CPU_WATCH) 147 #endif 148 #ifndef cpu_has_divec 149 #define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 150 #endif 151 #ifndef cpu_has_vce 152 #define cpu_has_vce __opt(MIPS_CPU_VCE) 153 #endif 154 #ifndef cpu_has_cache_cdex_p 155 #define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 156 #endif 157 #ifndef cpu_has_cache_cdex_s 158 #define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 159 #endif 160 #ifndef cpu_has_prefetch 161 #define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 162 #endif 163 #ifndef cpu_has_mcheck 164 #define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 165 #endif 166 #ifndef cpu_has_ejtag 167 #define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 168 #endif 169 #ifndef cpu_has_llsc 170 #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 171 #endif 172 #ifndef kernel_uses_llsc 173 #define kernel_uses_llsc cpu_has_llsc 174 #endif 175 #ifndef cpu_has_guestctl0ext 176 #define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 177 #endif 178 #ifndef cpu_has_guestctl1 179 #define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 180 #endif 181 #ifndef cpu_has_guestctl2 182 #define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 183 #endif 184 #ifndef cpu_has_guestid 185 #define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 186 #endif 187 #ifndef cpu_has_drg 188 #define cpu_has_drg __opt(MIPS_CPU_DRG) 189 #endif 190 #ifndef cpu_has_mips16 191 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 192 #endif 193 #ifndef cpu_has_mips16e2 194 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 195 #endif 196 #ifndef cpu_has_mdmx 197 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 198 #endif 199 #ifndef cpu_has_mips3d 200 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 201 #endif 202 #ifndef cpu_has_smartmips 203 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 204 #endif 205 206 #ifndef cpu_has_rixi 207 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 208 #endif 209 210 #ifndef cpu_has_mmips 211 # if defined(__mips_micromips) 212 # define cpu_has_mmips 1 213 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 214 # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 215 # else 216 # define cpu_has_mmips 0 217 # endif 218 #endif 219 220 #ifndef cpu_has_lpa 221 #define cpu_has_lpa __opt(MIPS_CPU_LPA) 222 #endif 223 #ifndef cpu_has_mvh 224 #define cpu_has_mvh __opt(MIPS_CPU_MVH) 225 #endif 226 #ifndef cpu_has_xpa 227 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 228 #endif 229 #ifndef cpu_has_vtag_icache 230 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 231 #endif 232 #ifndef cpu_has_dc_aliases 233 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 234 #endif 235 #ifndef cpu_has_ic_fills_f_dc 236 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 237 #endif 238 #ifndef cpu_has_pindexed_dcache 239 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 240 #endif 241 242 /* 243 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 244 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 245 * don't. For maintaining I-cache coherency this means we need to flush the 246 * D-cache all the way back to whever the I-cache does refills from, so the 247 * I-cache has a chance to see the new data at all. Then we have to flush the 248 * I-cache also. 249 * Note we may have been rescheduled and may no longer be running on the CPU 250 * that did the store so we can't optimize this into only doing the flush on 251 * the local CPU. 252 */ 253 #ifndef cpu_icache_snoops_remote_store 254 #ifdef CONFIG_SMP 255 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 256 #else 257 #define cpu_icache_snoops_remote_store 1 258 #endif 259 #endif 260 261 #ifndef cpu_has_mips_1 262 # define cpu_has_mips_1 (MIPS_ISA_REV < 6) 263 #endif 264 #ifndef cpu_has_mips_2 265 # define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II) 266 #endif 267 #ifndef cpu_has_mips_3 268 # define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III) 269 #endif 270 #ifndef cpu_has_mips_4 271 # define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV) 272 #endif 273 #ifndef cpu_has_mips_5 274 # define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V) 275 #endif 276 #ifndef cpu_has_mips32r1 277 # define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1) 278 #endif 279 #ifndef cpu_has_mips32r2 280 # define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) 281 #endif 282 #ifndef cpu_has_mips32r5 283 # define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5) 284 #endif 285 #ifndef cpu_has_mips32r6 286 # define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) 287 #endif 288 #ifndef cpu_has_mips64r1 289 # define cpu_has_mips64r1 (cpu_has_64bits && \ 290 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)) 291 #endif 292 #ifndef cpu_has_mips64r2 293 # define cpu_has_mips64r2 (cpu_has_64bits && \ 294 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)) 295 #endif 296 #ifndef cpu_has_mips64r5 297 # define cpu_has_mips64r5 (cpu_has_64bits && \ 298 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5)) 299 #endif 300 #ifndef cpu_has_mips64r6 301 # define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) 302 #endif 303 304 /* 305 * Shortcuts ... 306 */ 307 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 308 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 309 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 310 311 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 312 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 313 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 314 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 315 316 #define cpu_has_mips_3_4_5_64_r2_r6 \ 317 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 318 #define cpu_has_mips_4_5_64_r2_r6 \ 319 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 320 cpu_has_mips_r2 | cpu_has_mips_r5 | \ 321 cpu_has_mips_r6) 322 323 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 324 cpu_has_mips32r5 | cpu_has_mips32r6) 325 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | \ 326 cpu_has_mips64r5 | cpu_has_mips64r6) 327 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 328 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 329 #define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5) 330 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 331 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 332 cpu_has_mips32r5 | cpu_has_mips32r6 | \ 333 cpu_has_mips64r1 | cpu_has_mips64r2 | \ 334 cpu_has_mips64r5 | cpu_has_mips64r6) 335 336 /* MIPSR2 - MIPSR6 have a lot of similarities */ 337 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \ 338 cpu_has_mips_r6) 339 340 /* 341 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 342 * 343 * Returns non-zero value if the current processor implementation requires 344 * an IHB instruction to deal with an instruction hazard as per MIPS R2 345 * architecture specification, zero otherwise. 346 */ 347 #ifndef cpu_has_mips_r2_exec_hazard 348 #define cpu_has_mips_r2_exec_hazard \ 349 ({ \ 350 int __res; \ 351 \ 352 switch (current_cpu_type()) { \ 353 case CPU_M14KC: \ 354 case CPU_74K: \ 355 case CPU_1074K: \ 356 case CPU_PROAPTIV: \ 357 case CPU_P5600: \ 358 case CPU_M5150: \ 359 case CPU_QEMU_GENERIC: \ 360 case CPU_CAVIUM_OCTEON: \ 361 case CPU_CAVIUM_OCTEON_PLUS: \ 362 case CPU_CAVIUM_OCTEON2: \ 363 case CPU_CAVIUM_OCTEON3: \ 364 __res = 0; \ 365 break; \ 366 \ 367 default: \ 368 __res = 1; \ 369 } \ 370 \ 371 __res; \ 372 }) 373 #endif 374 375 /* 376 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 377 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 378 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 379 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 380 */ 381 #ifndef cpu_has_clo_clz 382 #define cpu_has_clo_clz cpu_has_mips_r 383 #endif 384 385 /* 386 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 387 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 388 * This indicates the availability of WSBH and in case of 64 bit CPUs also 389 * DSBH and DSHD. 390 */ 391 #ifndef cpu_has_wsbh 392 #define cpu_has_wsbh cpu_has_mips_r2 393 #endif 394 395 #ifndef cpu_has_dsp 396 #define cpu_has_dsp __ase(MIPS_ASE_DSP) 397 #endif 398 399 #ifndef cpu_has_dsp2 400 #define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 401 #endif 402 403 #ifndef cpu_has_dsp3 404 #define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 405 #endif 406 407 #ifndef cpu_has_loongson_mmi 408 #define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI) 409 #endif 410 411 #ifndef cpu_has_loongson_cam 412 #define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM) 413 #endif 414 415 #ifndef cpu_has_loongson_ext 416 #define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT) 417 #endif 418 419 #ifndef cpu_has_loongson_ext2 420 #define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2) 421 #endif 422 423 #ifndef cpu_has_mipsmt 424 #define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) 425 #endif 426 427 #ifndef cpu_has_vp 428 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 429 #endif 430 431 #ifndef cpu_has_userlocal 432 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 433 #endif 434 435 #ifdef CONFIG_32BIT 436 # ifndef cpu_has_nofpuex 437 # define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 438 # endif 439 # ifndef cpu_has_64bits 440 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 441 # endif 442 # ifndef cpu_has_64bit_zero_reg 443 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 444 # endif 445 # ifndef cpu_has_64bit_gp_regs 446 # define cpu_has_64bit_gp_regs 0 447 # endif 448 # ifndef cpu_vmbits 449 # define cpu_vmbits 31 450 # endif 451 #endif 452 453 #ifdef CONFIG_64BIT 454 # ifndef cpu_has_nofpuex 455 # define cpu_has_nofpuex 0 456 # endif 457 # ifndef cpu_has_64bits 458 # define cpu_has_64bits 1 459 # endif 460 # ifndef cpu_has_64bit_zero_reg 461 # define cpu_has_64bit_zero_reg 1 462 # endif 463 # ifndef cpu_has_64bit_gp_regs 464 # define cpu_has_64bit_gp_regs 1 465 # endif 466 # ifndef cpu_vmbits 467 # define cpu_vmbits cpu_data[0].vmbits 468 # define __NEED_VMBITS_PROBE 469 # endif 470 #endif 471 472 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 473 # define cpu_has_vint __opt(MIPS_CPU_VINT) 474 #elif !defined(cpu_has_vint) 475 # define cpu_has_vint 0 476 #endif 477 478 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 479 # define cpu_has_veic __opt(MIPS_CPU_VEIC) 480 #elif !defined(cpu_has_veic) 481 # define cpu_has_veic 0 482 #endif 483 484 #ifndef cpu_has_inclusive_pcaches 485 #define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 486 #endif 487 488 #ifndef cpu_dcache_line_size 489 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 490 #endif 491 #ifndef cpu_icache_line_size 492 #define cpu_icache_line_size() cpu_data[0].icache.linesz 493 #endif 494 #ifndef cpu_scache_line_size 495 #define cpu_scache_line_size() cpu_data[0].scache.linesz 496 #endif 497 #ifndef cpu_tcache_line_size 498 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 499 #endif 500 501 #ifndef cpu_hwrena_impl_bits 502 #define cpu_hwrena_impl_bits 0 503 #endif 504 505 #ifndef cpu_has_perf_cntr_intr_bit 506 #define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 507 #endif 508 509 #ifndef cpu_has_vz 510 #define cpu_has_vz __ase(MIPS_ASE_VZ) 511 #endif 512 513 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 514 # define cpu_has_msa __ase(MIPS_ASE_MSA) 515 #elif !defined(cpu_has_msa) 516 # define cpu_has_msa 0 517 #endif 518 519 #ifndef cpu_has_ufr 520 # define cpu_has_ufr __opt(MIPS_CPU_UFR) 521 #endif 522 523 #ifndef cpu_has_fre 524 # define cpu_has_fre __opt(MIPS_CPU_FRE) 525 #endif 526 527 #ifndef cpu_has_cdmm 528 # define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 529 #endif 530 531 #ifndef cpu_has_small_pages 532 # define cpu_has_small_pages __opt(MIPS_CPU_SP) 533 #endif 534 535 #ifndef cpu_has_nan_legacy 536 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 537 #endif 538 #ifndef cpu_has_nan_2008 539 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 540 #endif 541 542 #ifndef cpu_has_ebase_wg 543 # define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 544 #endif 545 546 #ifndef cpu_has_badinstr 547 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 548 #endif 549 550 #ifndef cpu_has_badinstrp 551 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 552 #endif 553 554 #ifndef cpu_has_contextconfig 555 # define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 556 #endif 557 558 #ifndef cpu_has_perf 559 # define cpu_has_perf __opt(MIPS_CPU_PERF) 560 #endif 561 562 #ifndef cpu_has_mac2008_only 563 # define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) 564 #endif 565 566 #ifndef cpu_has_ftlbparex 567 # define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) 568 #endif 569 570 #ifndef cpu_has_gsexcex 571 # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) 572 #endif 573 574 #ifdef CONFIG_SMP 575 /* 576 * Some systems share FTLB RAMs between threads within a core (siblings in 577 * kernel parlance). This means that FTLB entries may become invalid at almost 578 * any point when an entry is evicted due to a sibling thread writing an entry 579 * to the shared FTLB RAM. 580 * 581 * This is only relevant to SMP systems, and the only systems that exhibit this 582 * property implement MIPSr6 or higher so we constrain support for this to 583 * kernels that will run on such systems. 584 */ 585 # ifndef cpu_has_shared_ftlb_ram 586 # define cpu_has_shared_ftlb_ram \ 587 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 588 # endif 589 590 /* 591 * Some systems take this a step further & share FTLB entries between siblings. 592 * This is implemented as TLB writes happening as usual, but if an entry 593 * written by a sibling exists in the shared FTLB for a translation which would 594 * otherwise cause a TLB refill exception then the CPU will use the entry 595 * written by its sibling rather than triggering a refill & writing a matching 596 * TLB entry for itself. 597 * 598 * This is naturally only valid if a TLB entry is known to be suitable for use 599 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 600 * rather than ASIDs or when a TLB entry is marked global. 601 */ 602 # ifndef cpu_has_shared_ftlb_entries 603 # define cpu_has_shared_ftlb_entries \ 604 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 605 # endif 606 #endif /* SMP */ 607 608 #ifndef cpu_has_shared_ftlb_ram 609 # define cpu_has_shared_ftlb_ram 0 610 #endif 611 #ifndef cpu_has_shared_ftlb_entries 612 # define cpu_has_shared_ftlb_entries 0 613 #endif 614 615 #ifdef CONFIG_MIPS_MT_SMP 616 # define cpu_has_mipsmt_pertccounters \ 617 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 618 #else 619 # define cpu_has_mipsmt_pertccounters 0 620 #endif /* CONFIG_MIPS_MT_SMP */ 621 622 /* 623 * We only enable MMID support for configurations which natively support 64 bit 624 * atomics because getting good performance from the allocator relies upon 625 * efficient atomic64_*() functions. 626 */ 627 #ifndef cpu_has_mmid 628 # ifdef CONFIG_GENERIC_ATOMIC64 629 # define cpu_has_mmid 0 630 # else 631 # define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID) 632 # endif 633 #endif 634 635 #ifndef cpu_has_mm_sysad 636 # define cpu_has_mm_sysad __opt(MIPS_CPU_MM_SYSAD) 637 #endif 638 639 #ifndef cpu_has_mm_full 640 # define cpu_has_mm_full __opt(MIPS_CPU_MM_FULL) 641 #endif 642 643 /* 644 * Guest capabilities 645 */ 646 #ifndef cpu_guest_has_conf1 647 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 648 #endif 649 #ifndef cpu_guest_has_conf2 650 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 651 #endif 652 #ifndef cpu_guest_has_conf3 653 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 654 #endif 655 #ifndef cpu_guest_has_conf4 656 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 657 #endif 658 #ifndef cpu_guest_has_conf5 659 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 660 #endif 661 #ifndef cpu_guest_has_conf6 662 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 663 #endif 664 #ifndef cpu_guest_has_conf7 665 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 666 #endif 667 #ifndef cpu_guest_has_fpu 668 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 669 #endif 670 #ifndef cpu_guest_has_watch 671 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 672 #endif 673 #ifndef cpu_guest_has_contextconfig 674 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 675 #endif 676 #ifndef cpu_guest_has_segments 677 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 678 #endif 679 #ifndef cpu_guest_has_badinstr 680 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 681 #endif 682 #ifndef cpu_guest_has_badinstrp 683 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 684 #endif 685 #ifndef cpu_guest_has_htw 686 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 687 #endif 688 #ifndef cpu_guest_has_ldpte 689 #define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE) 690 #endif 691 #ifndef cpu_guest_has_mvh 692 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 693 #endif 694 #ifndef cpu_guest_has_msa 695 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 696 #endif 697 #ifndef cpu_guest_has_kscr 698 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 699 #endif 700 #ifndef cpu_guest_has_rw_llb 701 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 702 #endif 703 #ifndef cpu_guest_has_perf 704 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 705 #endif 706 #ifndef cpu_guest_has_maar 707 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 708 #endif 709 #ifndef cpu_guest_has_userlocal 710 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 711 #endif 712 713 /* 714 * Guest dynamic capabilities 715 */ 716 #ifndef cpu_guest_has_dyn_fpu 717 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 718 #endif 719 #ifndef cpu_guest_has_dyn_watch 720 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 721 #endif 722 #ifndef cpu_guest_has_dyn_contextconfig 723 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 724 #endif 725 #ifndef cpu_guest_has_dyn_perf 726 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 727 #endif 728 #ifndef cpu_guest_has_dyn_msa 729 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 730 #endif 731 #ifndef cpu_guest_has_dyn_maar 732 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 733 #endif 734 735 #endif /* __ASM_CPU_FEATURES_H */ 736